[PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0

Max Chou posted 14 patches 1 year, 1 month ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20231025151341.725477-1-max.chou@sifive.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
There is a newer version of this series
disas/riscv.c                            | 154 ++++++++++++++++++++++-
disas/riscv.h                            |   2 +
target/riscv/cpu.c                       |  36 ++++--
target/riscv/cpu_cfg.h                   |   8 ++
target/riscv/insn_trans/trans_rvvk.c.inc |  37 ++++--
target/riscv/tcg/tcg-cpu.c               |  48 ++++++-
6 files changed, 256 insertions(+), 29 deletions(-)
[PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0
Posted by Max Chou 1 year, 1 month ago
This patchset updates the RISC-V vector cryptography support to the
ratified version v1.0.0 (commit 1769c26, released on 2023/10) with
following items:

- Add Zvkb, Zvkt, and other shorthand extensions(Zvkn, Zvknc, Zvkng,
  Zvks, Zvksc, Zvksg).
- Supports the disassembler for vector crypto extensions.
- Move vector crypto extensions from experimental extensions to ratified
  extensions.
- Replace TAB indentations with spaces in disas/riscv.c.

https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0

Max Chou (14):
  target/riscv: Add cfg property for Zvkt extension
  target/riscv: Expose Zvkt extension property
  target/riscv: Add cfg property for Zvkb extension
  target/riscv: Replace Zvbb checking by Zvkb
  target/riscv: Expose Zvkb extension property
  target/riscv: Add cfg properties for Zvkn[c|g] extensions
  target/riscv: Expose Zvkn[c|g] extnesion properties
  target/riscv: Add cfg properties for Zvks[c|g] extensions
  target/riscv: Expose Zvks[c|g] extnesion properties
  target/riscv: Move vector crypto extensions to riscv_cpu_extensions
  disas/riscv: Add rv_fmt_vd_vs2_uimm format
  disas/riscv: Add rv_codec_vror_vi for vror.vi
  disas/riscv: Add support for vector crypto extensions
  disas/riscv: Replace TABs with space

 disas/riscv.c                            | 154 ++++++++++++++++++++++-
 disas/riscv.h                            |   2 +
 target/riscv/cpu.c                       |  36 ++++--
 target/riscv/cpu_cfg.h                   |   8 ++
 target/riscv/insn_trans/trans_rvvk.c.inc |  37 ++++--
 target/riscv/tcg/tcg-cpu.c               |  48 ++++++-
 6 files changed, 256 insertions(+), 29 deletions(-)

-- 
2.34.1