Series comparison

-[PULL 00/12] aspeed queue
+[PULL v2 00/17] aspeed queue
-The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:
+The following changes since commit bd2e12310b18b51aefbf834e6d54989fd175976f:
-  Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)
+  Merge tag 'qga-pull-2024-01-30' of https://github.com/kostyanf14/qemu into staging (2024-01-30 15:53:46 +0000)
 are available in the Git repository at:
-  https://github.com/legoater/qemu/ tags/pull-aspeed-20231025
+  https://github.com/legoater/qemu/ tags/pull-aspeed-20240201
-for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:
+for you to fetch changes up to 649b8ed20543f1b7f7e3dd8fd409092639bb345e:
-  hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)
+  hw/fsi: Update MAINTAINER list (2024-02-01 08:33:18 +0100)
 ----------------------------------------------------------------
 aspeed queue:
-* Update of Andrew's email
+* Update of buildroot images to 2023.11 (6.6.3 kernel)
-* Split of AspeedSoCState per 2400/2600/10x0
+* Check of the valid CPU type supported by aspeed machines
 * Simplified models for the IBM's FSI bus and the Aspeed
   controller bridge
+Changes since v1:
+- Endianness fix
+- Renamed test file to match other filenames
+- Fixed file list in MAINTAINER
 ----------------------------------------------------------------
-Andrew Jeffery (1):
+Cédric Le Goater (1):
-      MAINTAINERS: aspeed: Update Andrew's email address
+      tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11
-Philippe Mathieu-Daudé (11):
+Ninad Palsule (11):
-      hw/arm/aspeed: Extract code common to all boards to a common file
+      hw/fsi: Introduce IBM's Local bus
-      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
+      hw/fsi: Introduce IBM's scratchpad device
-      hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
+      hw/fsi: Introduce IBM's FSI Bus
-      hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
+      hw/fsi: Introduce IBM's fsi-slave model
-      hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
+      hw/fsi: Introduce IBM's cfam
-      hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
+      hw/fsi: Introduce IBM's FSI master
-      hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
+      hw/fsi: Aspeed APB2OPB & On-chip peripheral bus
-      hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
+      hw/arm: Hook up FSI module in AST2600
-      hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
+      hw/fsi: Added qtest
-      hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
+      hw/fsi: Added FSI documentation
-      hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
+      hw/fsi: Update MAINTAINER list
- MAINTAINERS                               |   2 +-
+Philippe Mathieu-Daudé (5):
- include/hw/arm/aspeed_soc.h               |  35 +++++-
+      hw/arm/aspeed: Remove dead code
- hw/arm/aspeed.c                           | 101 +++++++--------
+      hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
- hw/arm/aspeed_ast10x0.c                   |  53 ++++----
+      hw/arm/aspeed: Init CPU defaults in a common helper
- hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
+      hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
- hw/arm/aspeed_ast2600.c                   |  75 ++++++------
+      hw/arm/aspeed: Check for CPU types in machine_run_board_init()
  hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
  hw/arm/fby35.c                            |  27 ++--
  hw/arm/meson.build                        |   3 +-
 files changed, 363 insertions(+), 284 deletions(-)
  rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
  create mode 100644 hw/arm/aspeed_soc_common.c
+ MAINTAINERS                     |   9 +
+ docs/specs/fsi.rst              | 122 +++++++++++++
+ docs/specs/index.rst            |   1 +
+ meson.build                     |   1 +
+ hw/fsi/trace.h                  |   1 +
+ include/hw/arm/aspeed_soc.h     |   8 +-
+ include/hw/fsi/aspeed_apb2opb.h |  46 +++++
+ include/hw/fsi/cfam.h           |  34 ++++
+ include/hw/fsi/fsi-master.h     |  32 ++++
+ include/hw/fsi/fsi.h            |  37 ++++
+ include/hw/fsi/lbus.h           |  43 +++++
+ hw/arm/aspeed.c                 |  70 ++++----
+ hw/arm/aspeed_ast10x0.c         |   8 +-
+ hw/arm/aspeed_ast2400.c         |  15 +-
+ hw/arm/aspeed_ast2600.c         |  28 ++-
+ hw/arm/aspeed_soc_common.c      |   8 +
+ hw/fsi/aspeed_apb2opb.c         | 367 ++++++++++++++++++++++++++++++++++++++++
+ hw/fsi/cfam.c                   | 168 ++++++++++++++++++
+ hw/fsi/fsi-master.c             | 170 +++++++++++++++++++
+ hw/fsi/fsi.c                    | 102 +++++++++++
+ hw/fsi/lbus.c                   | 117 +++++++++++++
+ tests/qtest/aspeed_fsi-test.c   | 205 ++++++++++++++++++++++
+ hw/Kconfig                      |   1 +
+ hw/arm/Kconfig                  |   1 +
+ hw/fsi/Kconfig                  |   7 +
+ hw/fsi/meson.build              |   2 +
+ hw/fsi/trace-events             |  13 ++
+ hw/meson.build                  |   1 +
+ tests/avocado/machine_aspeed.py |  18 +-
+ tests/qtest/meson.build         |   1 +
+files changed, 1578 insertions(+), 58 deletions(-)
+ create mode 100644 docs/specs/fsi.rst
+ create mode 100644 hw/fsi/trace.h
+ create mode 100644 include/hw/fsi/aspeed_apb2opb.h
+ create mode 100644 include/hw/fsi/cfam.h
+ create mode 100644 include/hw/fsi/fsi-master.h
+ create mode 100644 include/hw/fsi/fsi.h
+ create mode 100644 include/hw/fsi/lbus.h
+ create mode 100644 hw/fsi/aspeed_apb2opb.c
+ create mode 100644 hw/fsi/cfam.c
+ create mode 100644 hw/fsi/fsi-master.c
+ create mode 100644 hw/fsi/fsi.c
+ create mode 100644 hw/fsi/lbus.c
+ create mode 100644 tests/qtest/aspeed_fsi-test.c
+ create mode 100644 hw/fsi/Kconfig
+ create mode 100644 hw/fsi/meson.build
+ create mode 100644 hw/fsi/trace-events

-[PULL 12/12] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
+[PULL 01/17] tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Compared to mainline buildroot, these images have some customization :
-The ARM array and VIC peripheral are only used by the
+- Linux version is bumped to 6.6.3 and built with a custom config
-series, remove them from the common AspeedSoCState.
+- U-Boot is switched to the one provided by OpenBMC for more support
 - defconfigs extra tools for dev
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+See branch [1] for more details.
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
 There are a few changes since last update, commit ed1f5ff84209. Images
 all have a password now and I2C devices have been updated in the Linux
 ast2600-evb device tree [2]. Do the necessary adjustements.
 [1] https://github.com/legoater/buildroot/commits/aspeed-2023.11
 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9deb10cf160e
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h               |  5 +++--
+ tests/avocado/machine_aspeed.py | 18 +++++++++---------
- hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
+file changed, 9 insertions(+), 9 deletions(-)
  hw/arm/meson.build                        |  2 +-
 files changed, 19 insertions(+), 15 deletions(-)
  rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)
-diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed_soc.h
+--- a/tests/avocado/machine_aspeed.py
-+++ b/include/hw/arm/aspeed_soc.h
++++ b/tests/avocado/machine_aspeed.py
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'
- struct AspeedSoCState {
+         time.sleep(0.1)
-     DeviceState parent;
+         exec_command(self, 'root')
+         time.sleep(0.1)
--    ARMCPU cpu[ASPEED_CPUS_NUM];
++        exec_command(self, "passw0rd")
-     MemoryRegion *memory;
-     MemoryRegion *dram_mr;
+     def do_test_arm_aspeed_buildroot_poweroff(self):
-     MemoryRegion dram_container;
+         exec_command_and_wait_for_pattern(self, 'poweroff',
-     MemoryRegion sram;
+@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_buildroot(self):
-     MemoryRegion spi_boot_container;
+         """
-     MemoryRegion spi_boot;
--    AspeedVICState vic;
+         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-     AspeedRtcState rtc;
+-                     'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
-     AspeedTimerCtrlState timerctrl;
+-        image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
-     AspeedI2CState i2c;
++                     'images/ast2500-evb/buildroot-2023.11/flash.img')
-@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
++        image_hash = ('c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
+         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
- struct Aspeed2400SoCState {
+                                       algorithm='sha256')
-     AspeedSoCState parent;
-+
+         self.vm.add_args('-device',
-+    ARMCPU cpu[ASPEED_CPUS_NUM];
+                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
-+    AspeedVICState vic;
+-        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0')
- };
++        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0', 'Aspeed AST2500 EVB')
- #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+         exec_command_and_wait_for_pattern(self,
-diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c
+              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
-similarity index 95%
+@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
-rename from hw/arm/aspeed_soc.c
+         """
-rename to hw/arm/aspeed_ast2400.c
-index XXXXXXX..XXXXXXX 100644
+         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
---- a/hw/arm/aspeed_soc.c
+-                     'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
-+++ b/hw/arm/aspeed_ast2400.c
+-        image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
-@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
++                     'images/ast2600-evb/buildroot-2023.11/flash.img')
++        image_hash = ('b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
- static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
+         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
- {
+                                       algorithm='sha256')
-+    Aspeed2400SoCState *a = ASPEED2400_SOC(s);
-     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
+                          'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
--    return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
+         self.vm.add_args('-device',
-+    return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
+                          'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
- }
+-        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
++        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
- static void aspeed_ast2400_soc_init(Object *obj)
- {
+         exec_command_and_wait_for_pattern(self,
-+    Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
+              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
-     AspeedSoCState *s = ASPEED_SOC(obj);
+              'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
-     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+         exec_command_and_wait_for_pattern(self,
-     int i;
+-                             'cat /sys/class/hwmon/hwmon0/temp1_input', '0')
-@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
++                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
-     }
+         self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
+                     property='temperature', value=18000);
-     for (i = 0; i < sc->num_cpus; i++) {
+         exec_command_and_wait_for_pattern(self,
--        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+-                             'cat /sys/class/hwmon/hwmon0/temp1_input', '18000')
-+        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
++                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
-     }
+         exec_command_and_wait_for_pattern(self,
-     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+              'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
-@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot_tpm(self):
-     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
+         self.vm.add_args('-device',
-                               "hw-prot-key");
+                          'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
+         self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
--    object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
+-        exec_command(self, "passw0rd")
-+    object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
+         exec_command_and_wait_for_pattern(self,
-     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
+             'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
  static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
  {
      int i;
 +    Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
      AspeedSoCState *s = ASPEED_SOC(dev);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      /* CPU */
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
 +        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                   OBJECT(s->memory), &error_abort);
 -        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 +        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
              return;
          }
      }
      /* SRAM */
 -    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
 +    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
      /* VIC */
 -    if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
          return;
      }
 -    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
 -    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 -                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 -    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 -                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 +    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
 +                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
 +                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
      /* RTC */
      if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'
  arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
  arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
  arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
 -  'aspeed_soc.c',
    'aspeed.c',
    'aspeed_soc_common.c',
 +  'aspeed_ast2400.c',
    'aspeed_ast2600.c',
    'aspeed_ast10x0.c',
    'aspeed_eeprom.c',
 --
-.41.0
+.43.0

-[PULL 10/12] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
+[PULL 02/17] hw/arm/aspeed: Remove dead code
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-The v7-M core is specific to the Aspeed 10x0 series,
+Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
-remove it from the common AspeedSoCState.
+Adding new machine Tiogapass in QEMU").
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Gavin Shan <gshan@redhat.com>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h |  5 ++---
+ hw/arm/aspeed.c | 1 -
- hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
+file changed, 1 deletion(-)
  hw/arm/fby35.c              | 13 ++++++++-----
 files changed, 25 insertions(+), 20 deletions(-)
-diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed_soc.h
+--- a/hw/arm/aspeed.c
-+++ b/include/hw/arm/aspeed_soc.h
++++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
- #define ASPEED_JTAG_NUM  2
+     mc->default_ram_size       = 1 * GiB;
+     mc->default_cpus = mc->min_cpus = mc->max_cpus =
- struct AspeedSoCState {
+         aspeed_soc_num_cpus(amc->soc_name);
--    /*< private >*/
+-        aspeed_soc_num_cpus(amc->soc_name);
      DeviceState parent;
 -    /*< public >*/
      ARMCPU cpu[ASPEED_CPUS_NUM];
      A15MPPrivState     a7mpcore;
 -    ARMv7MState        armv7m;
      MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
  struct Aspeed10x0SoCState {
      AspeedSoCState parent;
 +
 +    ARMv7MState armv7m;
  };
- #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
+ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast10x0.c
 +++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
  static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
 +    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
  }
  static void aspeed_soc_ast1030_init(Object *obj)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
          g_assert_not_reached();
      }
 -    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
 +    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
      s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
  static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
      AspeedSoCState *s = ASPEED_SOC(dev_soc);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 x40000);
      /* AST1030 CPU Core */
 -    armv7m = DEVICE(&s->armv7m);
 +    armv7m = DEVICE(&a->armv7m);
      qdev_prop_set_uint32(armv7m, "num-irq", 256);
      qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
      qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
 -    object_property_set_link(OBJECT(&s->armv7m), "memory",
 +    object_property_set_link(OBJECT(&a->armv7m), "memory",
                               OBJECT(s->memory), &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
 +    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
      /* Internal SRAM */
      sram_name = g_strdup_printf("aspeed.sram.%d",
 -                                CPU(s->armv7m.cpu)->cpu_index);
 +                                CPU(a->armv7m.cpu)->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err != NULL) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST1030 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST1030 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
       * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
      /* UART */
 diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fby35.c
 +++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
      Clock *bic_sysclk;
      AspeedSoCState bmc;
 -    AspeedSoCState bic;
 +    Aspeed10x0SoCState bic;
      bool mmio_exec;
  };
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
  static void fby35_bic_init(Fby35State *s)
  {
 +    AspeedSoCState *soc;
 +
      s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
      clock_set_hz(s->bic_sysclk, 200000000ULL);
      object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
 +    soc = ASPEED_SOC(&s->bic);
      memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
                         UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
      qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
      object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                               &error_abort);
 -    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
 +    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
      qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 -    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
 -    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
 -    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
 +    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
 +    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
 +    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
  }
  static void fby35_init(MachineState *machine)
 --
-.41.0
+.43.0

-[PULL 04/12] hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
+[PULL 03/17] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Keep aspeed_soc_class_init() generic, set the realize handler
+Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
-to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.
+of CPUs from the SoC definition") Aspeed machines use the
 aspeed_soc_num_cpus() helper to set the number of CPUs.
 Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
 Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e
 "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Gavin Shan <gshan@redhat.com>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_soc.c | 15 +++++++++++----
+ hw/arm/aspeed.c | 5 ++++-
-file changed, 11 insertions(+), 4 deletions(-)
+file changed, 4 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
+diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc.c
+--- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed_soc.c
++++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
-     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
+     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
      amc->i2c_init  = palmetto_bmc_i2c_init;
      mc->default_ram_size = 256 * MiB;
 +    mc->default_cpus = mc->min_cpus = mc->max_cpus =
 +        aspeed_soc_num_cpus(amc->soc_name);
  }
--static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
-+static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
- {
+     mc->init = aspeed_minibmc_machine_init;
-     int i;
+     amc->i2c_init = ast1030_evb_i2c_init;
-     AspeedSoCState *s = ASPEED_SOC(dev);
+     mc->default_ram_size = 0;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
- {
+     amc->fmc_model = "sst25vf032b";
-     DeviceClass *dc = DEVICE_CLASS(oc);
+     amc->spi_model = "sst25vf032b";
+     amc->num_cs = 2;
--    dc->realize = aspeed_soc_realize;
+     amc->macs_mask = 0;
--    /* Reason: Uses serial_hds and nd_table in realize() directly */
++    mc->default_cpus = mc->min_cpus = mc->max_cpus =
--    dc->user_creatable = false;
++        aspeed_soc_num_cpus(amc->soc_name);
      device_class_set_props(dc, aspeed_soc_properties);
  }
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
+ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
  static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
  {
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
 +    dc->realize = aspeed_ast2400_soc_realize;
 +    /* Reason: Uses serial_hds and nd_table in realize() directly */
 +    dc->user_creatable = false;
      sc->name         = "ast2400-a1";
      sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
  static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
  {
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
 +    dc->realize = aspeed_ast2400_soc_realize;
 +    /* Reason: Uses serial_hds and nd_table in realize() directly */
 +    dc->user_creatable = false;
      sc->name         = "ast2500-a1";
      sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
 --
-.41.0
+.43.0

-[PULL 05/12] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
+[PULL 04/17] hw/arm/aspeed: Init CPU defaults in a common helper
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-We want to derivate the big AspeedSoCState object in some more
+Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
-SoC-specific ones. Since the object size will vary, allocate it
+helper to reduce code duplication.
-dynamically.
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Gavin Shan <gshan@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 101 +++++++++++++++++++++++++-----------------------
+ hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------
-file changed, 52 insertions(+), 49 deletions(-)
+file changed, 28 insertions(+), 43 deletions(-)
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
-     MachineState parent_obj;
+                                           "Change the SPI Flash model");
-     /* Public */
+ }
--    AspeedSoCState soc;
+-static int aspeed_soc_num_cpus(const char *soc_name)
-+    AspeedSoCState *soc;
++static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
      MemoryRegion boot_rom;
      bool mmio_exec;
      uint32_t uart_chosen;
@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
  static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
                                      uint64_t rom_size)
  {
--    AspeedSoCState *soc = &bmc->soc;
+-   AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
-+    AspeedSoCState *soc = bmc->soc;
+-   return sc->num_cpus;
++    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
-     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
++    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
-                            &error_abort);
++
-@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
++    mc->default_cpus = sc->num_cpus;
- static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
++    mc->min_cpus = sc->num_cpus;
- {
++    mc->max_cpus = sc->num_cpus;
-     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
+ }
--    AspeedSoCState *s = &bmc->soc;
-+    AspeedSoCState *s = bmc->soc;
+ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
-     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
-     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
+     amc->num_cs    = 1;
+     amc->i2c_init  = palmetto_bmc_i2c_init;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
+     mc->default_ram_size       = 256 * MiB;
-     int i;
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-     NICInfo *nd = &nd_table[0];
+-        aspeed_soc_num_cpus(amc->soc_name);
++    aspeed_machine_class_init_cpus_defaults(mc);
--    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
+ };
--
--    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
-+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
-+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+     amc->num_cs    = 1;
-+    object_unref(OBJECT(bmc->soc));
+     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
-+    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
+     mc->default_ram_size       = 128 * MiB;
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-     /*
+-        aspeed_soc_num_cpus(amc->soc_name);
-      * This will error out if the RAM size is not supported by the
++    aspeed_machine_class_init_cpus_defaults(mc);
-      * memory controller of the SoC.
+ }
-      */
--    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
+ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
-+    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
-                              &error_fatal);
+     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+     amc->i2c_init  = palmetto_bmc_i2c_init;
-     for (i = 0; i < sc->macs_num; i++) {
+     mc->default_ram_size = 256 * MiB;
-         if ((amc->macs_mask & (1 << i)) && nd->used) {
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-             qemu_check_nic_model(nd, TYPE_FTGMAC100);
+-        aspeed_soc_num_cpus(amc->soc_name);
--            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
++    aspeed_machine_class_init_cpus_defaults(mc);
-+            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
+ }
-             nd++;
-         }
+ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
-     }
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
+     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
--    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
+     amc->i2c_init  = palmetto_bmc_i2c_init;
-+    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
+     mc->default_ram_size = 512 * MiB;
-                             &error_abort);
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
--    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
+-        aspeed_soc_num_cpus(amc->soc_name);
-+    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
++    aspeed_machine_class_init_cpus_defaults(mc);
-                             &error_abort);
+ }
--    object_property_set_link(OBJECT(&bmc->soc), "memory",
-+    object_property_set_link(OBJECT(bmc->soc), "memory",
+ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
-                              OBJECT(get_system_memory()), &error_abort);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
--    object_property_set_link(OBJECT(&bmc->soc), "dram",
+     amc->num_cs    = 1;
-+    object_property_set_link(OBJECT(bmc->soc), "dram",
+     amc->i2c_init  = ast2500_evb_i2c_init;
-                              OBJECT(machine->ram), &error_abort);
+     mc->default_ram_size       = 512 * MiB;
-     if (machine->kernel_filename) {
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-         /*
+-        aspeed_soc_num_cpus(amc->soc_name);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
++    aspeed_machine_class_init_cpus_defaults(mc);
-          * that runs to unlock the SCU. In this case set the default to
+ };
-          * be unlocked as the kernel expects
-          */
+ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
--        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
-+        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
+     amc->num_cs    = 2;
-                                 ASPEED_SCU_PROT_KEY, &error_abort);
+     amc->i2c_init  = yosemitev2_bmc_i2c_init;
-     }
+     mc->default_ram_size       = 512 * MiB;
-     connect_serial_hds_to_uarts(bmc);
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
--    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+-        aspeed_soc_num_cpus(amc->soc_name);
-+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
++    aspeed_machine_class_init_cpus_defaults(mc);
+ };
-     if (defaults_enabled()) {
--        aspeed_board_init_flashes(&bmc->soc.fmc,
+ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
-+        aspeed_board_init_flashes(&bmc->soc->fmc,
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
-                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
+     amc->num_cs    = 2;
-                               amc->num_cs, 0);
+     amc->i2c_init  = romulus_bmc_i2c_init;
--        aspeed_board_init_flashes(&bmc->soc.spi[0],
+     mc->default_ram_size       = 512 * MiB;
-+        aspeed_board_init_flashes(&bmc->soc->spi[0],
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
+-        aspeed_soc_num_cpus(amc->soc_name);
-, amc->num_cs);
++    aspeed_machine_class_init_cpus_defaults(mc);
-     }
+ };
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
-         amc->i2c_init(bmc);
+ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
-     }
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
+     amc->num_cs    = 2;
--    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
+     amc->i2c_init  = tiogapass_bmc_i2c_init;
--        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
+     mc->default_ram_size       = 1 * GiB;
-+    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-+        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
+-        aspeed_soc_num_cpus(amc->soc_name);
-                            drive_get(IF_SD, 0, i));
++    aspeed_machine_class_init_cpus_defaults(mc);
-     }
+ };
--    if (bmc->soc.emmc.num_slots) {
+ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
--        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
--                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
+     amc->num_cs    = 2;
-+    if (bmc->soc->emmc.num_slots) {
+     amc->i2c_init  = sonorapass_bmc_i2c_init;
-+        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
+     mc->default_ram_size       = 512 * MiB;
-+                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-     }
+-        aspeed_soc_num_cpus(amc->soc_name);
++    aspeed_machine_class_init_cpus_defaults(mc);
-     if (!bmc->mmio_exec) {
+ };
--        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
-+        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
+ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
-         BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
+     amc->num_cs    = 2;
-         if (fmc0) {
+     amc->i2c_init  = witherspoon_bmc_i2c_init;
--            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+     mc->default_ram_size = 512 * MiB;
-+            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-             aspeed_install_boot_rom(bmc, fmc0, rom_size);
+-        aspeed_soc_num_cpus(amc->soc_name);
-         }
++    aspeed_machine_class_init_cpus_defaults(mc);
-     }
+ };
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
+ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
- static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
- {
+                      ASPEED_MAC3_ON;
--    AspeedSoCState *soc = &bmc->soc;
+     amc->i2c_init  = ast2600_evb_i2c_init;
-+    AspeedSoCState *soc = bmc->soc;
+     mc->default_ram_size = 1 * GiB;
-     DeviceState *dev;
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
+-        aspeed_soc_num_cpus(amc->soc_name);
++    aspeed_machine_class_init_cpus_defaults(mc);
-@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
+ };
- static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
+ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
- {
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
--    AspeedSoCState *soc = &bmc->soc;
+     amc->macs_mask  = ASPEED_MAC2_ON;
-+    AspeedSoCState *soc = bmc->soc;
+     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
+     mc->default_ram_size = 1 * GiB;
-     /*
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-      * The quanta-q71l platform expects tmp75s which are compatible with
+-        aspeed_soc_num_cpus(amc->soc_name);
-@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
++    aspeed_machine_class_init_cpus_defaults(mc);
+ };
- static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
- {
+ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
--    AspeedSoCState *soc = &bmc->soc;
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
-+    AspeedSoCState *soc = bmc->soc;
+     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
-     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
+     amc->i2c_init  = g220a_bmc_i2c_init;
+     mc->default_ram_size = 1024 * MiB;
-     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
+-        aspeed_soc_num_cpus(amc->soc_name);
++    aspeed_machine_class_init_cpus_defaults(mc);
- static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
+ };
- {
--    AspeedSoCState *soc = &bmc->soc;
+ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
-+    AspeedSoCState *soc = bmc->soc;
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
-     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
+     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+     amc->i2c_init  = fp5280g2_bmc_i2c_init;
-     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
+     mc->default_ram_size = 512 * MiB;
-@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
+-        aspeed_soc_num_cpus(amc->soc_name);
- static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
++    aspeed_machine_class_init_cpus_defaults(mc);
- {
+ };
--    AspeedSoCState *soc = &bmc->soc;
-+    AspeedSoCState *soc = bmc->soc;
+ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
-     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
+     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
-     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
+     amc->i2c_init  = rainier_bmc_i2c_init;
-@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
+     mc->default_ram_size = 1 * GiB;
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
- static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
+-        aspeed_soc_num_cpus(amc->soc_name);
- {
++    aspeed_machine_class_init_cpus_defaults(mc);
--    AspeedSoCState *soc = &bmc->soc;
+ };
-+    AspeedSoCState *soc = bmc->soc;
+ #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
-     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
-      * good enough */
+     amc->i2c_init = fuji_bmc_i2c_init;
-@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
+     amc->uart_default = ASPEED_DEV_UART1;
+     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
- static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
- {
+-        aspeed_soc_num_cpus(amc->soc_name);
--    AspeedSoCState *soc = &bmc->soc;
++    aspeed_machine_class_init_cpus_defaults(mc);
-+    AspeedSoCState *soc = bmc->soc;
+ };
-     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
+ #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
      at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
  static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* bus 2 : */
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
          {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
          {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
      };
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      DeviceState *dev;
      LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
  static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      DeviceState *dev;
      dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
  static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[144] = {};
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[13] = {};
      for (int i = 0; i < 13; i++) {
          if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  static void fby35_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[16];
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
  static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
  }
  static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *therm_mux, *cpuvr_mux;
      /* Create the generic DC-SCM hardware */
 @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
+     amc->macs_mask = ASPEED_MAC2_ON;
+     amc->i2c_init  = bletchley_bmc_i2c_init;
+     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
+-        aspeed_soc_num_cpus(amc->soc_name);
++    aspeed_machine_class_init_cpus_defaults(mc);
+ }
  static void fby35_reset(MachineState *state, ShutdownCause reason)
- {
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
-     AspeedMachineState *bmc = ASPEED_MACHINE(state);
+     amc->i2c_init  = fby35_i2c_init;
--    AspeedGPIOState *gpio = &bmc->soc.gpio;
+     /* FIXME: Replace this macro with something more general */
-+    AspeedGPIOState *gpio = &bmc->soc->gpio;
+     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
++    aspeed_machine_class_init_cpus_defaults(mc);
-     qemu_devices_reset(reason);
+ }
-@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
+ #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
-     sysclk = clock_new(OBJECT(machine), "SYSCLK");
+@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
-     clock_set_hz(sysclk, SYSCLK_FRQ);
+     amc->spi_model = "sst25vf032b";
+     amc->num_cs = 2;
--    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
+     amc->macs_mask = 0;
--    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+-        aspeed_soc_num_cpus(amc->soc_name);
-+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
++    aspeed_machine_class_init_cpus_defaults(mc);
-+    object_unref(OBJECT(bmc->soc));
+ }
-+    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
+ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
--    object_property_set_link(OBJECT(&bmc->soc), "memory",
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
-+    object_property_set_link(OBJECT(bmc->soc), "memory",
+     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
-                              OBJECT(get_system_memory()), &error_abort);
+     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
-     connect_serial_hds_to_uarts(bmc);
+     mc->default_ram_size = 1 * GiB;
--    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
+-        aspeed_soc_num_cpus(amc->soc_name);
++    aspeed_machine_class_init_cpus_defaults(mc);
--    aspeed_board_init_flashes(&bmc->soc.fmc,
+ };
-+    aspeed_board_init_flashes(&bmc->soc->fmc,
-                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
+ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
-                               amc->num_cs,
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
-);
+     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
+     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
--    aspeed_board_init_flashes(&bmc->soc.spi[0],
+     mc->default_ram_size = 1 * GiB;
-+    aspeed_board_init_flashes(&bmc->soc->spi[0],
+-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
+-        aspeed_soc_num_cpus(amc->soc_name);
-                               amc->num_cs, amc->num_cs);
++    aspeed_machine_class_init_cpus_defaults(mc);
+ };
--    aspeed_board_init_flashes(&bmc->soc.spi[1],
-+    aspeed_board_init_flashes(&bmc->soc->spi[1],
+ static const TypeInfo aspeed_machine_types[] = {
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
                                amc->num_cs, (amc->num_cs * 2));
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
  static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* U10 24C08 connects to SDA/SCL Group 1 by default */
      uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 --
-.41.0
+.43.0

-[PULL 11/12] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
+[PULL 05/17] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-The v7-A cluster is specific to the Aspeed 2600 series,
+In order to alter AspeedSoCClass::cpu_type in the next
-remove it from the common AspeedSoCState.
+commit, introduce the aspeed_soc_cpu_type() helper to
+retrieve the per-SoC CPU type from AspeedSoCClass.
 The ARM cores belong to the MP cluster, but the array
 is currently used by TYPE_ASPEED2600_SOC. We'll clean
 that soon, but for now keep it in Aspeed2600SoCState.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Gavin Shan <gshan@redhat.com>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h |  4 ++-
+ include/hw/arm/aspeed_soc.h | 1 +
- hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
+ hw/arm/aspeed_ast10x0.c     | 2 +-
- hw/arm/fby35.c              | 14 ++++++-----
+ hw/arm/aspeed_ast2400.c     | 3 ++-
-files changed, 37 insertions(+), 30 deletions(-)
+ hw/arm/aspeed_ast2600.c     | 3 ++-
  hw/arm/aspeed_soc_common.c  | 5 +++++
 files changed, 11 insertions(+), 3 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass {
-     DeviceState parent;
+     qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
      ARMCPU cpu[ASPEED_CPUS_NUM];
 -    A15MPPrivState     a7mpcore;
      MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
  struct Aspeed2600SoCState {
      AspeedSoCState parent;
 +
 +    A15MPPrivState a7mpcore;
 +    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
  };
- #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
++const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
  enum {
      ASPEED_DEV_SPI_BOOT,
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast10x0.c
 +++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      /* AST1030 CPU Core */
      armv7m = DEVICE(&a->armv7m);
      qdev_prop_set_uint32(armv7m, "num-irq", 256);
 -    qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
 +    qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
      qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
      object_property_set_link(OBJECT(&a->armv7m), "memory",
                               OBJECT(s->memory), &error_abort);
 diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2400.c
 +++ b/hw/arm/aspeed_ast2400.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
      }
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
 +        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
 +                                aspeed_soc_cpu_type(sc));
      }
      snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
-@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
- static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
- {
-+    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
-     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
--    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
-+    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
- }
- static void aspeed_soc_ast2600_init(Object *obj)
- {
-+    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
-     AspeedSoCState *s = ASPEED_SOC(obj);
-     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     int i;
 @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      }
      for (i = 0; i < sc->num_cpus; i++) {
--        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+-        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
-+        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
++        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
 +                                aspeed_soc_cpu_type(sc));
      }
      snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
+diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
-     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
+index XXXXXXX..XXXXXXX 100644
-                               "hw-prot-key");
+--- a/hw/arm/aspeed_soc_common.c
++++ b/hw/arm/aspeed_soc_common.c
--    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+@@ -XXX,XX +XXX,XX @@
-+    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
+ #include "hw/char/serial.h"
-                             TYPE_A15MPCORE_PRIV);
-     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
++const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
-@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
++{
- static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
++    return sc->cpu_type;
 +}
 +
  qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
  {
-     int i;
+     return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
      AspeedSoCState *s = ASPEED_SOC(dev);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      /* CPU */
      for (i = 0; i < sc->num_cpus; i++) {
          if (sc->num_cpus > 1) {
 -            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
 +            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                      ASPEED_A7MPCORE_ADDR, &error_abort);
          }
 -        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
 +        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                  aspeed_calc_affinity(i), &error_abort);
 -        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
 +        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                  &error_abort);
 -        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
 +        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
                                  &error_abort);
 -        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
 +        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                  &error_abort);
 -        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
 +        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                   OBJECT(s->memory), &error_abort);
 -        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 +        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
              return;
          }
      }
      /* A7MPCORE */
 -    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
 +    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
                              &error_abort);
 -    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
 +    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
                              ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
                              &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
 -    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
 +    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
 +    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
      for (i = 0; i < sc->num_cpus; i++) {
 -        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 -        DeviceState  *d   = DEVICE(&s->cpu[i]);
 +        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
 +        DeviceState  *d   = DEVICE(&a->cpu[i]);
          irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
          sysbus_connect_irq(sbd, i, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      /* SRAM */
 -    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
 +    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
 -        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST2600 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
       * offset 0.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
      /* HACE */
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
 -        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST2600 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
 diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fby35.c
 +++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
      MemoryRegion bic_memory;
      Clock *bic_sysclk;
 -    AspeedSoCState bmc;
 +    Aspeed2600SoCState bmc;
      Aspeed10x0SoCState bic;
      bool mmio_exec;
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
  static void fby35_bmc_init(Fby35State *s)
  {
 +    AspeedSoCState *soc;
 +
      object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
 +    soc = ASPEED_SOC(&s->bmc);
      memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
                         UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
                              &error_abort);
      object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
                              &error_abort);
 -    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
 +    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
      qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
 -    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
 +    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
      /* Install first FMC flash content as a boot rom. */
      if (!s->mmio_exec) {
          DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
          if (mtd0) {
 -            AspeedSoCState *bmc = &s->bmc;
 -            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
 +            uint64_t rom_size = memory_region_size(&soc->spi_boot);
              memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
                                     rom_size, &error_abort);
 -            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
 +            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
                                                  &s->bmc_boot_rom, 1);
              fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
 --
-.41.0
+.43.0

-[PULL 08/12] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
+[PULL 06/17] hw/arm/aspeed: Check for CPU types in machine_run_board_init()
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
+Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
-In few commits we'll add more fields, but to keep
+Convert it to a NULL-terminated array (of a single non-NULL element).
 review process simple, don't add any yet.
-TYPE_ASPEED_SOC is common to various Aspeed SoCs,
+Set MachineClass::valid_cpu_types[] to use the common machine code
-define it in aspeed_soc_common.c.
+to provide hints when the requested CPU is invalid (see commit
 e702cbc19e ("machine: Improve is_cpu_type_supported()").
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Gavin Shan <gshan@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h |  7 +++++
+ include/hw/arm/aspeed_soc.h |  3 ++-
- hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
+ hw/arm/aspeed.c             |  1 +
- hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
+ hw/arm/aspeed_ast10x0.c     |  6 +++++-
-files changed, 53 insertions(+), 44 deletions(-)
+ hw/arm/aspeed_ast2400.c     | 12 ++++++++++--
  hw/arm/aspeed_ast2600.c     |  6 +++++-
  hw/arm/aspeed_soc_common.c  |  5 ++++-
 files changed, 27 insertions(+), 6 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass {
- #define TYPE_ASPEED_SOC "aspeed-soc"
+     DeviceClass parent_class;
- OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
+     const char *name;
-+struct Aspeed2400SoCState {
+-    const char *cpu_type;
-+    AspeedSoCState parent;
++    /** valid_cpu_types: NULL terminated array of a single CPU type. */
-+};
++    const char * const *valid_cpu_types;
-+
+     uint32_t silicon_rev;
-+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+     uint64_t sram_size;
-+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
+     uint64_t secsram_size;
-+
+diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
  struct Aspeed2600SoCState {
      AspeedSoCState parent;
  };
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc.c
+--- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed_soc.c
++++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
      mc->default_cpus = sc->num_cpus;
      mc->min_cpus = sc->num_cpus;
      mc->max_cpus = sc->num_cpus;
 +    mc->valid_cpu_types = sc->valid_cpu_types;
  }
  static void aspeed_machine_class_init(ObjectClass *oc, void *data)
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast10x0.c
 +++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
  static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
  {
 +    static const char * const valid_cpu_types[] = {
 +        ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
 +        NULL
 +    };
      DeviceClass *dc = DEVICE_CLASS(klass);
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
      dc->realize = aspeed_soc_ast1030_realize;
      sc->name = "ast1030-a1";
 -    sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
 +    sc->valid_cpu_types = valid_cpu_types;
      sc->silicon_rev = AST1030_A1_SILICON_REV;
      sc->sram_size = 0xc0000;
      sc->secsram_size = 0x40000; /* 256 * KiB */
 diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2400.c
 +++ b/hw/arm/aspeed_ast2400.c
 @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
-     sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
-                        aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
- }
--static Property aspeed_soc_properties[] = {
--    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
--                     MemoryRegion *),
--    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
--                     MemoryRegion *),
--    DEFINE_PROP_END_OF_LIST(),
--};
--
--static void aspeed_soc_class_init(ObjectClass *oc, void *data)
--{
--    DeviceClass *dc = DEVICE_CLASS(oc);
--
--    device_class_set_props(dc, aspeed_soc_properties);
--}
--
--static const TypeInfo aspeed_soc_type_info = {
--    .name           = TYPE_ASPEED_SOC,
--    .parent         = TYPE_DEVICE,
--    .instance_size  = sizeof(AspeedSoCState),
--    .class_size     = sizeof(AspeedSoCClass),
--    .class_init     = aspeed_soc_class_init,
--    .abstract       = true,
--};
  static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
  {
++    static const char * const valid_cpu_types[] = {
++        ARM_CPU_TYPE_NAME("arm926"),
++        NULL
++    };
+     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+     DeviceClass *dc = DEVICE_CLASS(oc);
 @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
-     sc->get_irq      = aspeed_soc_ast2400_get_irq;
+     dc->user_creatable = false;
- }
+     sc->name         = "ast2400-a1";
--static const TypeInfo aspeed_soc_ast2400_type_info = {
+-    sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
--    .name           = "ast2400-a1",
++    sc->valid_cpu_types = valid_cpu_types;
--    .parent         = TYPE_ASPEED_SOC,
+     sc->silicon_rev  = AST2400_A1_SILICON_REV;
--    .instance_init  = aspeed_ast2400_soc_init,
+     sc->sram_size    = 0x8000;
--    .instance_size  = sizeof(AspeedSoCState),
+     sc->spis_num     = 1;
--    .class_init     = aspeed_soc_ast2400_class_init,
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
--};
 -
  static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
  {
++    static const char * const valid_cpu_types[] = {
++        ARM_CPU_TYPE_NAME("arm1176"),
++        NULL
++    };
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+     DeviceClass *dc = DEVICE_CLASS(oc);
 @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
-     sc->get_irq      = aspeed_soc_ast2400_get_irq;
+     dc->user_creatable = false;
- }
+     sc->name         = "ast2500-a1";
--static const TypeInfo aspeed_soc_ast2500_type_info = {
+-    sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
--    .name           = "ast2500-a1",
++    sc->valid_cpu_types = valid_cpu_types;
--    .parent         = TYPE_ASPEED_SOC,
+     sc->silicon_rev  = AST2500_A1_SILICON_REV;
--    .instance_init  = aspeed_ast2400_soc_init,
+     sc->sram_size    = 0x9000;
--    .instance_size  = sizeof(AspeedSoCState),
+     sc->spis_num     = 2;
--    .class_init     = aspeed_soc_ast2500_class_init,
+diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
--};
+index XXXXXXX..XXXXXXX 100644
--static void aspeed_soc_register_types(void)
+--- a/hw/arm/aspeed_ast2600.c
--{
++++ b/hw/arm/aspeed_ast2600.c
--    type_register_static(&aspeed_soc_type_info);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
--    type_register_static(&aspeed_soc_ast2400_type_info);
--    type_register_static(&aspeed_soc_ast2500_type_info);
+ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
-+static const TypeInfo aspeed_soc_ast2400_types[] = {
+ {
-+    {
++    static const char * const valid_cpu_types[] = {
-+        .name           = TYPE_ASPEED2400_SOC,
++        ARM_CPU_TYPE_NAME("cortex-a7"),
-+        .parent         = TYPE_ASPEED_SOC,
++        NULL
-+        .instance_init  = aspeed_ast2400_soc_init,
++    };
-+        .instance_size  = sizeof(Aspeed2400SoCState),
+     DeviceClass *dc = DEVICE_CLASS(oc);
-+        .abstract       = true,
+     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
-+    }, {
-+        .name           = "ast2400-a1",
+     dc->realize      = aspeed_soc_ast2600_realize;
-+        .parent         = TYPE_ASPEED2400_SOC,
-+        .class_init     = aspeed_soc_ast2400_class_init,
+     sc->name         = "ast2600-a3";
-+    }, {
+-    sc->cpu_type     = ARM_CPU_TYPE_NAME("cortex-a7");
-+        .name           = "ast2500-a1",
++    sc->valid_cpu_types = valid_cpu_types;
-+        .parent         = TYPE_ASPEED2400_SOC,
+     sc->silicon_rev  = AST2600_A3_SILICON_REV;
-+        .class_init     = aspeed_soc_ast2500_class_init,
+     sc->sram_size    = 0x16400;
-+    },
+     sc->spis_num     = 2;
  };
 -type_init(aspeed_soc_register_types);
 +DEFINE_TYPES(aspeed_soc_ast2400_types)
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc_common.c
 +++ b/hw/arm/aspeed_soc_common.c
 @@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
+ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
- #include "qapi/error.h"
+ {
-+#include "hw/qdev-properties.h"
+-    return sc->cpu_type;
- #include "hw/misc/unimp.h"
++    assert(sc->valid_cpu_types);
- #include "hw/arm/aspeed_soc.h"
++    assert(sc->valid_cpu_types[0]);
- #include "hw/char/serial.h"
++    assert(!sc->valid_cpu_types[1]);
-@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
++    return sc->valid_cpu_types[0];
      memory_region_add_subregion_overlap(s->memory, addr,
                                          sysbus_mmio_get_region(dev, 0), -1000);
  }
-+
-+static Property aspeed_soc_properties[] = {
+ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
 +    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
 +                     MemoryRegion *),
 +    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
 +                     MemoryRegion *),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
 +    device_class_set_props(dc, aspeed_soc_properties);
 +}
 +
 +static const TypeInfo aspeed_soc_types[] = {
 +    {
 +        .name           = TYPE_ASPEED_SOC,
 +        .parent         = TYPE_DEVICE,
 +        .instance_size  = sizeof(AspeedSoCState),
 +        .class_size     = sizeof(AspeedSoCClass),
 +        .class_init     = aspeed_soc_class_init,
 +        .abstract       = true,
 +    },
 +};
 +
 +DEFINE_TYPES(aspeed_soc_types)
 --
-.41.0
+.43.0

-[PULL 02/12] hw/arm/aspeed: Extract code common to all boards to a common file
+[PULL 07/17] hw/fsi: Introduce IBM's Local bus
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Ninad Palsule <ninad@linux.ibm.com>
-aspeed_soc.c contains definitions specific to the AST2400
+This is a part of patchset where IBM's Flexible Service Interface is
-and AST2500 SoCs, but also some definitions for other AST
+introduced.
 SoCs: move them to a common file.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+The LBUS is modelled to maintain mapped memory for the devices. The
 memory is mapped after CFAM config, peek table and FSI slave registers.
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
+[ clg: - removed lbus_add_device() bc unused
+       - removed lbus_create_device() bc used only once
+       - removed "address" property
+       - updated meson.build to build fsi dir
+       - included an empty hw/fsi/trace-events ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_soc.c        |  96 -------------------------------
+ meson.build           |  1 +
- hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
+ hw/fsi/trace.h        |  1 +
- hw/arm/meson.build         |   1 +
+ include/hw/fsi/lbus.h | 32 ++++++++++++++++++++++++++++++++
-files changed, 115 insertions(+), 96 deletions(-)
+ hw/fsi/lbus.c         | 43 +++++++++++++++++++++++++++++++++++++++++++
- create mode 100644 hw/arm/aspeed_soc_common.c
+ hw/Kconfig            |  1 +
  hw/fsi/Kconfig        |  2 ++
  hw/fsi/meson.build    |  1 +
  hw/fsi/trace-events   |  0
  hw/meson.build        |  1 +
 files changed, 82 insertions(+)
  create mode 100644 hw/fsi/trace.h
  create mode 100644 include/hw/fsi/lbus.h
  create mode 100644 hw/fsi/lbus.c
  create mode 100644 hw/fsi/Kconfig
  create mode 100644 hw/fsi/meson.build
  create mode 100644 hw/fsi/trace-events
-diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
+diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc.c
+--- a/meson.build
-+++ b/hw/arm/aspeed_soc.c
++++ b/meson.build
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
+@@ -XXX,XX +XXX,XX @@ if have_system
- };
+     'hw/char',
+     'hw/display',
- type_init(aspeed_soc_register_types);
+     'hw/dma',
--
++    'hw/fsi',
--qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+     'hw/hyperv',
--{
+     'hw/i2c',
--    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+     'hw/i386',
--}
+diff --git a/hw/fsi/trace.h b/hw/fsi/trace.h
 -
 -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    SerialMM *smm;
 -
 -    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 -        smm = &s->uart[i];
 -
 -        /* Chardev property is set by the machine. */
 -        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
 -        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
 -        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
 -        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
 -        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
 -            return false;
 -        }
 -
 -        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
 -        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
 -    }
 -
 -    return true;
 -}
 -
 -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    int i = dev - ASPEED_DEV_UART1;
 -
 -    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
 -    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 -}
 -
 -/*
 - * SDMC should be realized first to get correct RAM size and max size
 - * values
 - */
 -bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    ram_addr_t ram_size, max_ram_size;
 -
 -    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
 -                                        &error_abort);
 -    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
 -                                            &error_abort);
 -
 -    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
 -                       max_ram_size);
 -    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
 -
 -    /*
 -     * Add a memory region beyond the RAM region to let firmwares scan
 -     * the address space with load/store and guess how much RAM the
 -     * SoC has.
 -     */
 -    if (ram_size < max_ram_size) {
 -        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 -
 -        qdev_prop_set_string(dev, "name", "ram-empty");
 -        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
 -        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
 -            return false;
 -        }
 -
 -        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
 -                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
 -    }
 -
 -    memory_region_add_subregion(s->memory,
 -                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
 -    return true;
 -}
 -
 -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
 -{
 -    memory_region_add_subregion(s->memory, addr,
 -                                sysbus_mmio_get_region(dev, n));
 -}
 -
 -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 -                                   const char *name, hwaddr addr, uint64_t size)
 -{
 -    qdev_prop_set_string(DEVICE(dev), "name", name);
 -    qdev_prop_set_uint64(DEVICE(dev), "size", size);
 -    sysbus_realize(dev, &error_abort);
 -
 -    memory_region_add_subregion_overlap(s->memory, addr,
 -                                        sysbus_mmio_get_region(dev, 0), -1000);
 -}
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/arm/aspeed_soc_common.c
++++ b/hw/fsi/trace.h
@@ -0,0 +1 @@
 +#include "trace/trace-hw_fsi.h"
 diff --git a/include/hw/fsi/lbus.h b/include/hw/fsi/lbus.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/fsi/lbus.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * ASPEED SoC family
++ * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
-+ * Andrew Jeffery <andrew@aj.id.au>
++ * IBM Local bus and connected device structures.
-+ * Jeremy Kerr <jk@ozlabs.org>
++ */
 +#ifndef FSI_LBUS_H
 +#define FSI_LBUS_H
 +
 +#include "hw/qdev-core.h"
 +#include "qemu/units.h"
 +#include "exec/memory.h"
 +
 +#define TYPE_FSI_LBUS_DEVICE "fsi.lbus.device"
 +OBJECT_DECLARE_SIMPLE_TYPE(FSILBusDevice, FSI_LBUS_DEVICE)
 +
 +typedef struct FSILBusDevice {
 +    DeviceState parent;
 +
 +    MemoryRegion iomem;
 +} FSILBusDevice;
 +
 +#define TYPE_FSI_LBUS "fsi.lbus"
 +OBJECT_DECLARE_SIMPLE_TYPE(FSILBus, FSI_LBUS)
 +
 +typedef struct FSILBus {
 +    BusState bus;
 +
 +    MemoryRegion mr;
 +} FSILBus;
 +
 +#endif /* FSI_LBUS_H */
 diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/fsi/lbus.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
-+ * Copyright 2016 IBM Corp.
++ * IBM Local bus where FSI slaves are connected
 + *
 + * This code is licensed under the GPL version 2 or later.  See
 + * the COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
-+#include "hw/misc/unimp.h"
++#include "hw/fsi/lbus.h"
 +#include "hw/arm/aspeed_soc.h"
 +#include "hw/char/serial.h"
 +
++#include "hw/qdev-properties.h"
 +
-+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
++#include "trace.h"
 +
 +static void fsi_lbus_init(Object *o)
 +{
-+    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
++    FSILBus *lbus = FSI_LBUS(o);
 +
 +    memory_region_init(&lbus->mr, OBJECT(lbus), TYPE_FSI_LBUS, 1 * MiB);
 +}
 +
-+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
++static const TypeInfo fsi_lbus_info = {
 +    .name = TYPE_FSI_LBUS,
 +    .parent = TYPE_BUS,
 +    .instance_init = fsi_lbus_init,
 +    .instance_size = sizeof(FSILBus),
 +};
 +
 +static const TypeInfo fsi_lbus_device_type_info = {
 +    .name = TYPE_FSI_LBUS_DEVICE,
 +    .parent = TYPE_DEVICE,
 +    .instance_size = sizeof(FSILBusDevice),
 +    .abstract = true,
 +};
 +
 +static void fsi_lbus_register_types(void)
 +{
-+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
++    type_register_static(&fsi_lbus_info);
-+    SerialMM *smm;
++    type_register_static(&fsi_lbus_device_type_info);
 +
 +    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 +        smm = &s->uart[i];
 +
 +        /* Chardev property is set by the machine. */
 +        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
 +        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
 +        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
 +        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
 +        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
 +            return false;
 +        }
 +
 +        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
 +        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
 +    }
 +
 +    return true;
 +}
 +
-+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
++type_init(fsi_lbus_register_types);
-+{
+diff --git a/hw/Kconfig b/hw/Kconfig
 +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 +    int i = dev - ASPEED_DEV_UART1;
 +
 +    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
 +    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 +}
 +
 +/*
 + * SDMC should be realized first to get correct RAM size and max size
 + * values
 + */
 +bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
 +{
 +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 +    ram_addr_t ram_size, max_ram_size;
 +
 +    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
 +                                        &error_abort);
 +    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
 +                                            &error_abort);
 +
 +    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
 +                       max_ram_size);
 +    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
 +
 +    /*
 +     * Add a memory region beyond the RAM region to let firmwares scan
 +     * the address space with load/store and guess how much RAM the
 +     * SoC has.
 +     */
 +    if (ram_size < max_ram_size) {
 +        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 +
 +        qdev_prop_set_string(dev, "name", "ram-empty");
 +        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
 +        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
 +            return false;
 +        }
 +
 +        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
 +                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
 +    }
 +
 +    memory_region_add_subregion(s->memory,
 +                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
 +    return true;
 +}
 +
 +void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
 +{
 +    memory_region_add_subregion(s->memory, addr,
 +                                sysbus_mmio_get_region(dev, n));
 +}
 +
 +void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 +                                   const char *name, hwaddr addr, uint64_t size)
 +{
 +    qdev_prop_set_string(DEVICE(dev), "name", name);
 +    qdev_prop_set_uint64(DEVICE(dev), "size", size);
 +    sysbus_realize(dev, &error_abort);
 +
 +    memory_region_add_subregion_overlap(s->memory, addr,
 +                                        sysbus_mmio_get_region(dev, 0), -1000);
 +}
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/meson.build
+--- a/hw/Kconfig
-+++ b/hw/arm/meson.build
++++ b/hw/Kconfig
-@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
+@@ -XXX,XX +XXX,XX @@ source core/Kconfig
- arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+ source cxl/Kconfig
-   'aspeed_soc.c',
+ source display/Kconfig
-   'aspeed.c',
+ source dma/Kconfig
-+  'aspeed_soc_common.c',
++source fsi/Kconfig
-   'aspeed_ast2600.c',
+ source gpio/Kconfig
-   'aspeed_ast10x0.c',
+ source hyperv/Kconfig
-   'aspeed_eeprom.c',
+ source i2c/Kconfig
 diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/fsi/Kconfig
@@ -XXX,XX +XXX,XX @@
 +config FSI
 +    bool
 diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/fsi/meson.build
@@ -0,0 +1 @@
 +system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c'))
 diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
 new file mode 100644
 index XXXXXXX..XXXXXXX
 diff --git a/hw/meson.build b/hw/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/meson.build
 +++ b/hw/meson.build
@@ -XXX,XX +XXX,XX @@ subdir('virtio')
  subdir('watchdog')
  subdir('xen')
  subdir('xenpv')
 +subdir('fsi')
  subdir('alpha')
  subdir('arm')
 --
-.41.0
+.43.0

-[PULL 03/12] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
+[PULL 08/17] hw/fsi: Introduce IBM's scratchpad device
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Ninad Palsule <ninad@linux.ibm.com>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+This is a part of patchset where IBM's Flexible Service Interface is
 introduced.
 The scratchpad provides a set of non-functional registers. The firmware
 is free to use them, hardware does not support any special management
 support. The scratchpad registers can be read or written from LBUS
 slave. The scratch pad is managed under FSI CFAM state.
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
+[ clg: - moved object FSIScratchPad under FSICFAMState
+       - moved FSIScratchPad code under cfam.c ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_soc.c | 6 +++---
+ include/hw/fsi/lbus.h | 11 ++++++
-file changed, 3 insertions(+), 3 deletions(-)
+ hw/fsi/lbus.c         | 78 +++++++++++++++++++++++++++++++++++++++++--
  hw/fsi/trace-events   |  2 ++
 files changed, 89 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
+diff --git a/include/hw/fsi/lbus.h b/include/hw/fsi/lbus.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc.c
+--- a/include/hw/fsi/lbus.h
-+++ b/hw/arm/aspeed_soc.c
++++ b/include/hw/fsi/lbus.h
-@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
+@@ -XXX,XX +XXX,XX @@ typedef struct FSILBus {
-     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
+     MemoryRegion mr;
  } FSILBus;
 +#define TYPE_FSI_SCRATCHPAD "fsi.scratchpad"
 +#define SCRATCHPAD(obj) OBJECT_CHECK(FSIScratchPad, (obj), TYPE_FSI_SCRATCHPAD)
 +
 +#define FSI_SCRATCHPAD_NR_REGS 4
 +
 +typedef struct FSIScratchPad {
 +        FSILBusDevice parent;
 +
 +        uint32_t regs[FSI_SCRATCHPAD_NR_REGS];
 +} FSIScratchPad;
 +
  #endif /* FSI_LBUS_H */
 diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/lbus.c
 +++ b/hw/fsi/lbus.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "qapi/error.h"
  #include "hw/fsi/lbus.h"
 -
  #include "hw/qdev-properties.h"
 -
 +#include "qemu/log.h"
  #include "trace.h"
 +#define TO_REG(offset) ((offset) >> 2)
 +
  static void fsi_lbus_init(Object *o)
  {
      FSILBus *lbus = FSI_LBUS(o);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo fsi_lbus_device_type_info = {
      .abstract = true,
  };
 +static uint64_t fsi_scratchpad_read(void *opaque, hwaddr addr, unsigned size)
 +{
 +    FSIScratchPad *s = SCRATCHPAD(opaque);
 +    int reg = TO_REG(addr);
 +
 +    trace_fsi_scratchpad_read(addr, size);
 +
 +    if (reg >= FSI_SCRATCHPAD_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, addr);
 +        return 0;
 +    }
 +
 +    return s->regs[reg];
 +}
 +
 +static void fsi_scratchpad_write(void *opaque, hwaddr addr, uint64_t data,
 +                                 unsigned size)
 +{
 +    FSIScratchPad *s = SCRATCHPAD(opaque);
 +
 +    trace_fsi_scratchpad_write(addr, size, data);
 +    int reg = TO_REG(addr);
 +
 +    if (reg >= FSI_SCRATCHPAD_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, addr);
 +        return;
 +    }
 +
 +    s->regs[reg] = data;
 +}
 +
 +static const struct MemoryRegionOps scratchpad_ops = {
 +    .read = fsi_scratchpad_read,
 +    .write = fsi_scratchpad_write,
 +    .endianness = DEVICE_BIG_ENDIAN,
 +};
 +
 +static void fsi_scratchpad_realize(DeviceState *dev, Error **errp)
 +{
 +    FSILBusDevice *ldev = FSI_LBUS_DEVICE(dev);
 +
 +    memory_region_init_io(&ldev->iomem, OBJECT(ldev), &scratchpad_ops,
 +                          ldev, TYPE_FSI_SCRATCHPAD, 0x400);
 +}
 +
 +static void fsi_scratchpad_reset(DeviceState *dev)
 +{
 +    FSIScratchPad *s = SCRATCHPAD(dev);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +}
 +
 +static void fsi_scratchpad_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->bus_type = TYPE_FSI_LBUS;
 +    dc->realize = fsi_scratchpad_realize;
 +    dc->reset = fsi_scratchpad_reset;
 +}
 +
 +static const TypeInfo fsi_scratchpad_info = {
 +    .name = TYPE_FSI_SCRATCHPAD,
 +    .parent = TYPE_FSI_LBUS_DEVICE,
 +    .instance_size = sizeof(FSIScratchPad),
 +    .class_init = fsi_scratchpad_class_init,
 +};
 +
  static void fsi_lbus_register_types(void)
  {
      type_register_static(&fsi_lbus_info);
      type_register_static(&fsi_lbus_device_type_info);
 +    type_register_static(&fsi_scratchpad_info);
  }
--static void aspeed_soc_init(Object *obj)
+ type_init(fsi_lbus_register_types);
-+static void aspeed_ast2400_soc_init(Object *obj)
+diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
- {
+index XXXXXXX..XXXXXXX 100644
-     AspeedSoCState *s = ASPEED_SOC(obj);
+--- a/hw/fsi/trace-events
-     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
++++ b/hw/fsi/trace-events
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@
- static const TypeInfo aspeed_soc_ast2400_type_info = {
++fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
-     .name           = "ast2400-a1",
++fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
      .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_soc_init,
 +    .instance_init  = aspeed_ast2400_soc_init,
      .instance_size  = sizeof(AspeedSoCState),
      .class_init     = aspeed_soc_ast2400_class_init,
  };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
  static const TypeInfo aspeed_soc_ast2500_type_info = {
      .name           = "ast2500-a1",
      .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_soc_init,
 +    .instance_init  = aspeed_ast2400_soc_init,
      .instance_size  = sizeof(AspeedSoCState),
      .class_init     = aspeed_soc_ast2500_class_init,
  };
 --
-.41.0
+.43.0

-[PULL 06/12] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
+[PULL 09/17] hw/fsi: Introduce IBM's FSI Bus
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Ninad Palsule <ninad@linux.ibm.com>
-TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
+This is a part of patchset where FSI bus is introduced.
 In few commits we'll add more fields, but to keep
 review process simple, don't add any yet.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+The FSI bus is a simple bus where FSI master is attached.
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
+[ clg: - removed include/hw/fsi/engine-scratchpad.h and
+            hw/fsi/engine-scratchpad.c
+       - dropped FSI_SCRATCHPAD
+       - included FSIBus definition
+       - dropped hw/fsi/trace-events changes ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h |  7 +++++++
+ include/hw/fsi/fsi.h | 19 +++++++++++++++++++
- hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
+ hw/fsi/fsi.c         | 22 ++++++++++++++++++++++
-files changed, 20 insertions(+), 13 deletions(-)
+ hw/fsi/meson.build   |  2 +-
 files changed, 42 insertions(+), 1 deletion(-)
  create mode 100644 include/hw/fsi/fsi.h
  create mode 100644 hw/fsi/fsi.c
-diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+diff --git a/include/hw/fsi/fsi.h b/include/hw/fsi/fsi.h
-index XXXXXXX..XXXXXXX 100644
+new file mode 100644
---- a/include/hw/arm/aspeed_soc.h
+index XXXXXXX..XXXXXXX
-+++ b/include/hw/arm/aspeed_soc.h
+--- /dev/null
-@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
++++ b/include/hw/fsi/fsi.h
- #define TYPE_ASPEED_SOC "aspeed-soc"
+@@ -XXX,XX +XXX,XX @@
- OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
++/*
++ * SPDX-License-Identifier: GPL-2.0-or-later
-+struct Aspeed10x0SoCState {
++ * Copyright (C) 2024 IBM Corp.
-+    AspeedSoCState parent;
++ *
 + * IBM Flexible Service Interface
 + */
 +#ifndef FSI_FSI_H
 +#define FSI_FSI_H
 +
 +#include "hw/qdev-core.h"
 +
 +#define TYPE_FSI_BUS "fsi.bus"
 +OBJECT_DECLARE_SIMPLE_TYPE(FSIBus, FSI_BUS)
 +
 +typedef struct FSIBus {
 +    BusState bus;
 +} FSIBus;
 +
 +#endif /* FSI_FSI_H */
 diff --git a/hw/fsi/fsi.c b/hw/fsi/fsi.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/fsi/fsi.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
 + * IBM Flexible Service Interface
 + */
 +#include "qemu/osdep.h"
 +
 +#include "hw/fsi/fsi.h"
 +
 +static const TypeInfo fsi_bus_info = {
 +    .name = TYPE_FSI_BUS,
 +    .parent = TYPE_BUS,
 +    .instance_size = sizeof(FSIBus),
 +};
 +
-+#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
++static void fsi_bus_register_types(void)
-+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
++{
 +    type_register_static(&fsi_bus_info);
 +}
 +
- struct AspeedSoCClass {
++type_init(fsi_bus_register_types);
-     DeviceClass parent_class;
+diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_ast10x0.c
+--- a/hw/fsi/meson.build
-+++ b/hw/arm/aspeed_ast10x0.c
++++ b/hw/fsi/meson.build
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
+@@ -1 +1 @@
-     sc->get_irq = aspeed_soc_ast1030_get_irq;
+-system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c'))
- }
++system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c'))
 -static const TypeInfo aspeed_soc_ast1030_type_info = {
 -    .name          = "ast1030-a1",
 -    .parent        = TYPE_ASPEED_SOC,
 -    .instance_size = sizeof(AspeedSoCState),
 -    .instance_init = aspeed_soc_ast1030_init,
 -    .class_init    = aspeed_soc_ast1030_class_init,
 -    .class_size    = sizeof(AspeedSoCClass),
 +static const TypeInfo aspeed_soc_ast10x0_types[] = {
 +    {
 +        .name           = TYPE_ASPEED10X0_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_size  = sizeof(Aspeed10x0SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast1030-a1",
 +        .parent         = TYPE_ASPEED10X0_SOC,
 +        .instance_init  = aspeed_soc_ast1030_init,
 +        .class_init     = aspeed_soc_ast1030_class_init,
 +    },
  };
 -static void aspeed_soc_register_types(void)
 -{
 -    type_register_static(&aspeed_soc_ast1030_type_info);
 -}
 -
 -type_init(aspeed_soc_register_types)
 +DEFINE_TYPES(aspeed_soc_ast10x0_types)
 --
-.41.0
+.43.0

-[PULL 09/12] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
+[PULL 10/17] hw/fsi: Introduce IBM's fsi-slave model
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Ninad Palsule <ninad@linux.ibm.com>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+This is a part of patchset where IBM's Flexible Service Interface is
 introduced.
 The FSI slave: The slave is the terminal point of the FSI bus for
 FSI symbols addressed to it. Slaves can be cascaded off of one
 another. The slave's configuration registers appear in address space
 of the CFAM to which it is attached.
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_soc_common.c | 11 +++++++++++
+ include/hw/fsi/fsi.h | 18 ++++++++++
-file changed, 11 insertions(+)
+ hw/fsi/fsi.c         | 84 ++++++++++++++++++++++++++++++++++++++++++--
  hw/fsi/trace-events  |  2 ++
 files changed, 102 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
+diff --git a/include/hw/fsi/fsi.h b/include/hw/fsi/fsi.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc_common.c
+--- a/include/hw/fsi/fsi.h
-+++ b/hw/arm/aspeed_soc_common.c
++++ b/include/hw/fsi/fsi.h
-@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+@@ -XXX,XX +XXX,XX @@
-                                         sysbus_mmio_get_region(dev, 0), -1000);
+ #ifndef FSI_FSI_H
- }
+ #define FSI_FSI_H
-+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
++#include "exec/memory.h"
  #include "hw/qdev-core.h"
 +#include "hw/fsi/lbus.h"
 +#include "qemu/bitops.h"
 +
 +/* Bitwise operations at the word level. */
 +#define BE_GENMASK(hb, lb)  MAKE_64BIT_MASK((lb), ((hb) - (lb) + 1))
  #define TYPE_FSI_BUS "fsi.bus"
  OBJECT_DECLARE_SIMPLE_TYPE(FSIBus, FSI_BUS)
@@ -XXX,XX +XXX,XX @@ typedef struct FSIBus {
      BusState bus;
  } FSIBus;
 +#define TYPE_FSI_SLAVE "fsi.slave"
 +OBJECT_DECLARE_SIMPLE_TYPE(FSISlaveState, FSI_SLAVE)
 +
 +#define FSI_SLAVE_CONTROL_NR_REGS ((0x40 >> 2) + 1)
 +
 +typedef struct FSISlaveState {
 +    DeviceState parent;
 +
 +    MemoryRegion iomem;
 +    uint32_t regs[FSI_SLAVE_CONTROL_NR_REGS];
 +} FSISlaveState;
 +
  #endif /* FSI_FSI_H */
 diff --git a/hw/fsi/fsi.c b/hw/fsi/fsi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/fsi.c
 +++ b/hw/fsi/fsi.c
@@ -XXX,XX +XXX,XX @@
   * IBM Flexible Service Interface
   */
  #include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "qemu/log.h"
 +#include "trace.h"
  #include "hw/fsi/fsi.h"
 +#define TO_REG(x)                               ((x) >> 2)
 +
  static const TypeInfo fsi_bus_info = {
      .name = TYPE_FSI_BUS,
      .parent = TYPE_BUS,
      .instance_size = sizeof(FSIBus),
  };
 -static void fsi_bus_register_types(void)
 +static uint64_t fsi_slave_read(void *opaque, hwaddr addr, unsigned size)
 +{
-+    AspeedSoCState *s = ASPEED_SOC(dev);
++    FSISlaveState *s = FSI_SLAVE(opaque);
 +    int reg = TO_REG(addr);
 +
-+    if (!s->memory) {
++    trace_fsi_slave_read(addr, size);
-+        error_setg(errp, "'memory' link is not set");
++
 +    if (reg >= FSI_SLAVE_CONTROL_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
 +                      __func__, addr, size);
 +        return 0;
 +    }
 +
 +    return s->regs[reg];
 +}
 +
 +static void fsi_slave_write(void *opaque, hwaddr addr, uint64_t data,
 +                                 unsigned size)
 +{
 +    FSISlaveState *s = FSI_SLAVE(opaque);
 +    int reg = TO_REG(addr);
 +
 +    trace_fsi_slave_write(addr, size, data);
 +
 +    if (reg >= FSI_SLAVE_CONTROL_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out of bounds write: 0x%"HWADDR_PRIx" for %u\n",
 +                      __func__, addr, size);
 +        return;
 +    }
++
++    s->regs[reg] = data;
 +}
 +
- static Property aspeed_soc_properties[] = {
++static const struct MemoryRegionOps fsi_slave_ops = {
-     DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
++    .read = fsi_slave_read,
-                      MemoryRegion *),
++    .write = fsi_slave_write,
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
++    .endianness = DEVICE_BIG_ENDIAN,
 +};
 +
 +static void fsi_slave_reset(DeviceState *dev)
 +{
 +    FSISlaveState *s = FSI_SLAVE(dev);
 +
 +    /* Initialize registers */
 +    memset(s->regs, 0, sizeof(s->regs));
 +}
 +
 +static void fsi_slave_init(Object *o)
 +{
 +    FSISlaveState *s = FSI_SLAVE(o);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &fsi_slave_ops,
 +                          s, TYPE_FSI_SLAVE, 0x400);
 +}
 +
 +static void fsi_slave_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->bus_type = TYPE_FSI_BUS;
 +    dc->desc = "FSI Slave";
 +    dc->reset = fsi_slave_reset;
 +}
 +
 +static const TypeInfo fsi_slave_info = {
 +    .name = TYPE_FSI_SLAVE,
 +    .parent = TYPE_DEVICE,
 +    .instance_init = fsi_slave_init,
 +    .instance_size = sizeof(FSISlaveState),
 +    .class_init = fsi_slave_class_init,
 +};
 +
 +static void fsi_register_types(void)
  {
-     DeviceClass *dc = DEVICE_CLASS(oc);
+     type_register_static(&fsi_bus_info);
++    type_register_static(&fsi_slave_info);
 +    dc->realize = aspeed_soc_realize;
      device_class_set_props(dc, aspeed_soc_properties);
  }
+-type_init(fsi_bus_register_types);
++type_init(fsi_register_types);
+diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/fsi/trace-events
++++ b/hw/fsi/trace-events
+@@ -XXX,XX +XXX,XX @@
+ fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
+ fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
++fsi_slave_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
++fsi_slave_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 --
-.41.0
+.43.0

-New patch
+[PULL 11/17] hw/fsi: Introduce IBM's cfam
+From: Ninad Palsule <ninad@linux.ibm.com>
 This is a part of patchset where IBM's Flexible Service Interface is
 introduced.
 The Common FRU Access Macro (CFAM), an address space containing
 various "engines" that drive accesses on busses internal and external
 to the POWER chip. Examples include the SBEFIFO and I2C masters. The
 engines hang off of an internal Local Bus (LBUS) which is described
 by the CFAM configuration block.
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 [ clg: - moved object FSIScratchPad under FSICFAMState
        - moved FSIScratchPad code under cfam.c
        - introduced fsi_cfam_instance_init()
        - reworked fsi_cfam_realize() ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  include/hw/fsi/cfam.h |  34 +++++++++
  hw/fsi/cfam.c         | 168 ++++++++++++++++++++++++++++++++++++++++++
  hw/fsi/meson.build    |   2 +-
  hw/fsi/trace-events   |   5 ++
 files changed, 208 insertions(+), 1 deletion(-)
  create mode 100644 include/hw/fsi/cfam.h
  create mode 100644 hw/fsi/cfam.c
 diff --git a/include/hw/fsi/cfam.h b/include/hw/fsi/cfam.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/fsi/cfam.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
 + * IBM Common FRU Access Macro
 + */
 +#ifndef FSI_CFAM_H
 +#define FSI_CFAM_H
 +
 +#include "exec/memory.h"
 +
 +#include "hw/fsi/fsi.h"
 +#include "hw/fsi/lbus.h"
 +
 +#define TYPE_FSI_CFAM "cfam"
 +#define FSI_CFAM(obj) OBJECT_CHECK(FSICFAMState, (obj), TYPE_FSI_CFAM)
 +
 +/* P9-ism */
 +#define CFAM_CONFIG_NR_REGS 0x28
 +
 +typedef struct FSICFAMState {
 +    /* < private > */
 +    FSISlaveState parent;
 +
 +    /* CFAM config address space */
 +    MemoryRegion config_iomem;
 +
 +    MemoryRegion mr;
 +
 +    FSILBus lbus;
 +    FSIScratchPad scratchpad;
 +} FSICFAMState;
 +
 +#endif /* FSI_CFAM_H */
 diff --git a/hw/fsi/cfam.c b/hw/fsi/cfam.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/fsi/cfam.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
 + * IBM Common FRU Access Macro
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/units.h"
 +
 +#include "qapi/error.h"
 +#include "trace.h"
 +
 +#include "hw/fsi/cfam.h"
 +#include "hw/fsi/fsi.h"
 +
 +#include "hw/qdev-properties.h"
 +
 +#define ENGINE_CONFIG_NEXT            BIT(31)
 +#define ENGINE_CONFIG_TYPE_PEEK       (0x02 << 4)
 +#define ENGINE_CONFIG_TYPE_FSI        (0x03 << 4)
 +#define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4)
 +
 +/* Valid, slots, version, type, crc */
 +#define CFAM_CONFIG_REG(__VER, __TYPE, __CRC)   \
 +    (ENGINE_CONFIG_NEXT       |   \
 +     0x00010000               |   \
 +     (__VER)                  |   \
 +     (__TYPE)                 |   \
 +     (__CRC))
 +
 +#define TO_REG(x)                          ((x) >> 2)
 +
 +#define CFAM_CONFIG_CHIP_ID                TO_REG(0x00)
 +#define CFAM_CONFIG_PEEK_STATUS            TO_REG(0x04)
 +#define CFAM_CONFIG_CHIP_ID_P9             0xc0022d15
 +#define CFAM_CONFIG_CHIP_ID_BREAK          0xc0de0000
 +
 +static uint64_t fsi_cfam_config_read(void *opaque, hwaddr addr, unsigned size)
 +{
 +    trace_fsi_cfam_config_read(addr, size);
 +
 +    switch (addr) {
 +    case 0x00:
 +        return CFAM_CONFIG_CHIP_ID_P9;
 +    case 0x04:
 +        return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_PEEK, 0xc);
 +    case 0x08:
 +        return CFAM_CONFIG_REG(0x5000, ENGINE_CONFIG_TYPE_FSI, 0xa);
 +    case 0xc:
 +        return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_SCRATCHPAD, 0x7);
 +    default:
 +        /*
 +         * The config table contains different engines from 0xc onwards.
 +         * The scratch pad is already added at address 0xc. We need to add
 +         * future engines from address 0x10 onwards. Returning 0 as engine
 +         * is not implemented.
 +         */
 +        return 0;
 +    }
 +}
 +
 +static void fsi_cfam_config_write(void *opaque, hwaddr addr, uint64_t data,
 +                                  unsigned size)
 +{
 +    FSICFAMState *cfam = FSI_CFAM(opaque);
 +
 +    trace_fsi_cfam_config_write(addr, size, data);
 +
 +    switch (TO_REG(addr)) {
 +    case CFAM_CONFIG_CHIP_ID:
 +    case CFAM_CONFIG_PEEK_STATUS:
 +        if (data == CFAM_CONFIG_CHIP_ID_BREAK) {
 +            bus_cold_reset(BUS(&cfam->lbus));
 +        }
 +        break;
 +    default:
 +        trace_fsi_cfam_config_write_noaddr(addr, size, data);
 +    }
 +}
 +
 +static const struct MemoryRegionOps cfam_config_ops = {
 +    .read = fsi_cfam_config_read,
 +    .write = fsi_cfam_config_write,
 +    .valid.max_access_size = 4,
 +    .valid.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +    .impl.min_access_size = 4,
 +    .endianness = DEVICE_BIG_ENDIAN,
 +};
 +
 +static uint64_t fsi_cfam_unimplemented_read(void *opaque, hwaddr addr,
 +                                            unsigned size)
 +{
 +    trace_fsi_cfam_unimplemented_read(addr, size);
 +
 +    return 0;
 +}
 +
 +static void fsi_cfam_unimplemented_write(void *opaque, hwaddr addr,
 +                                         uint64_t data, unsigned size)
 +{
 +    trace_fsi_cfam_unimplemented_write(addr, size, data);
 +}
 +
 +static const struct MemoryRegionOps fsi_cfam_unimplemented_ops = {
 +    .read = fsi_cfam_unimplemented_read,
 +    .write = fsi_cfam_unimplemented_write,
 +    .endianness = DEVICE_BIG_ENDIAN,
 +};
 +
 +static void fsi_cfam_instance_init(Object *obj)
 +{
 +    FSICFAMState *s = FSI_CFAM(obj);
 +
 +    object_initialize_child(obj, "scratchpad", &s->scratchpad,
 +                            TYPE_FSI_SCRATCHPAD);
 +}
 +
 +static void fsi_cfam_realize(DeviceState *dev, Error **errp)
 +{
 +    FSICFAMState *cfam = FSI_CFAM(dev);
 +    FSISlaveState *slave = FSI_SLAVE(dev);
 +
 +    /* Each slave has a 2MiB address space */
 +    memory_region_init_io(&cfam->mr, OBJECT(cfam), &fsi_cfam_unimplemented_ops,
 +                          cfam, TYPE_FSI_CFAM, 2 * MiB);
 +
 +    qbus_init(&cfam->lbus, sizeof(cfam->lbus), TYPE_FSI_LBUS, DEVICE(cfam),
 +              NULL);
 +
 +    memory_region_init_io(&cfam->config_iomem, OBJECT(cfam), &cfam_config_ops,
 +                          cfam, TYPE_FSI_CFAM ".config", 0x400);
 +
 +    memory_region_add_subregion(&cfam->mr, 0, &cfam->config_iomem);
 +    memory_region_add_subregion(&cfam->mr, 0x800, &slave->iomem);
 +    memory_region_add_subregion(&cfam->mr, 0xc00, &cfam->lbus.mr);
 +
 +    /* Add scratchpad engine */
 +    if (!qdev_realize(DEVICE(&cfam->scratchpad), BUS(&cfam->lbus), errp)) {
 +        return;
 +    }
 +
 +    FSILBusDevice *fsi_dev = FSI_LBUS_DEVICE(&cfam->scratchpad);
 +    memory_region_add_subregion(&cfam->lbus.mr, 0, &fsi_dev->iomem);
 +}
 +
 +static void fsi_cfam_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    dc->bus_type = TYPE_FSI_BUS;
 +    dc->realize = fsi_cfam_realize;
 +}
 +
 +static const TypeInfo fsi_cfam_info = {
 +    .name = TYPE_FSI_CFAM,
 +    .parent = TYPE_FSI_SLAVE,
 +    .instance_init = fsi_cfam_instance_init,
 +    .instance_size = sizeof(FSICFAMState),
 +    .class_init = fsi_cfam_class_init,
 +};
 +
 +static void fsi_cfam_register_types(void)
 +{
 +    type_register_static(&fsi_cfam_info);
 +}
 +
 +type_init(fsi_cfam_register_types);
 diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/meson.build
 +++ b/hw/fsi/meson.build
@@ -1 +1 @@
 -system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c'))
 +system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'))
 diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/trace-events
 +++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@ fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
  fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
  fsi_slave_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
  fsi_slave_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 +fsi_cfam_config_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 +fsi_cfam_config_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 +fsi_cfam_unimplemented_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 +fsi_cfam_unimplemented_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 +fsi_cfam_config_write_noaddr(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 --
 .43.0

-New patch
+[PULL 12/17] hw/fsi: Introduce IBM's FSI master
+From: Ninad Palsule <ninad@linux.ibm.com>
 This is a part of patchset where IBM's Flexible Service Interface is
 introduced.
 This commit models the FSI master. CFAM is hanging out of FSI master which is a bus controller.
 The FSI master: A controller in the platform service processor (e.g.
 BMC) driving CFAM engine accesses into the POWER chip. At the
 hardware level FSI is a bit-based protocol supporting synchronous and
 DMA-driven accesses of engines in a CFAM.
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 [ clg: - move FSICFAMState object under FSIMasterState
        - introduced fsi_master_init()
        - reworked fsi_master_realize()
        - dropped FSIBus definition ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  include/hw/fsi/fsi-master.h |  32 +++++++
  hw/fsi/fsi-master.c         | 170 ++++++++++++++++++++++++++++++++++++
  hw/fsi/meson.build          |   2 +-
  hw/fsi/trace-events         |   2 +
 files changed, 205 insertions(+), 1 deletion(-)
  create mode 100644 include/hw/fsi/fsi-master.h
  create mode 100644 hw/fsi/fsi-master.c
 diff --git a/include/hw/fsi/fsi-master.h b/include/hw/fsi/fsi-master.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/fsi/fsi-master.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
 + * IBM Flexible Service Interface Master
 + */
 +#ifndef FSI_FSI_MASTER_H
 +#define FSI_FSI_MASTER_H
 +
 +#include "exec/memory.h"
 +#include "hw/qdev-core.h"
 +#include "hw/fsi/fsi.h"
 +#include "hw/fsi/cfam.h"
 +
 +#define TYPE_FSI_MASTER "fsi.master"
 +OBJECT_DECLARE_SIMPLE_TYPE(FSIMasterState, FSI_MASTER)
 +
 +#define FSI_MASTER_NR_REGS ((0x2e0 >> 2) + 1)
 +
 +typedef struct FSIMasterState {
 +    DeviceState parent;
 +    MemoryRegion iomem;
 +    MemoryRegion opb2fsi;
 +
 +    FSIBus bus;
 +
 +    uint32_t regs[FSI_MASTER_NR_REGS];
 +    FSICFAMState cfam;
 +} FSIMasterState;
 +
 +
 +#endif /* FSI_FSI_H */
 diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/fsi/fsi-master.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
 + * IBM Flexible Service Interface master
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "qemu/log.h"
 +#include "trace.h"
 +
 +#include "hw/fsi/fsi-master.h"
 +
 +#define TYPE_OP_BUS "opb"
 +
 +#define TO_REG(x)                               ((x) >> 2)
 +
 +#define FSI_MENP0                               TO_REG(0x010)
 +#define FSI_MENP32                              TO_REG(0x014)
 +#define FSI_MSENP0                              TO_REG(0x018)
 +#define FSI_MLEVP0                              TO_REG(0x018)
 +#define FSI_MSENP32                             TO_REG(0x01c)
 +#define FSI_MLEVP32                             TO_REG(0x01c)
 +#define FSI_MCENP0                              TO_REG(0x020)
 +#define FSI_MREFP0                              TO_REG(0x020)
 +#define FSI_MCENP32                             TO_REG(0x024)
 +#define FSI_MREFP32                             TO_REG(0x024)
 +
 +#define FSI_MVER                                TO_REG(0x074)
 +#define FSI_MRESP0                              TO_REG(0x0d0)
 +
 +#define FSI_MRESB0                              TO_REG(0x1d0)
 +#define   FSI_MRESB0_RESET_GENERAL              BIT(31)
 +#define   FSI_MRESB0_RESET_ERROR                BIT(30)
 +
 +static uint64_t fsi_master_read(void *opaque, hwaddr addr, unsigned size)
 +{
 +    FSIMasterState *s = FSI_MASTER(opaque);
 +    int reg = TO_REG(addr);
 +
 +    trace_fsi_master_read(addr, size);
 +
 +    if (reg >= FSI_MASTER_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
 +                      __func__, addr, size);
 +        return 0;
 +    }
 +
 +    return s->regs[reg];
 +}
 +
 +static void fsi_master_write(void *opaque, hwaddr addr, uint64_t data,
 +                             unsigned size)
 +{
 +    FSIMasterState *s = FSI_MASTER(opaque);
 +    int reg = TO_REG(addr);
 +
 +    trace_fsi_master_write(addr, size, data);
 +
 +    if (reg >= FSI_MASTER_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n",
 +                      __func__, addr, size);
 +        return;
 +    }
 +
 +    switch (reg) {
 +    case FSI_MENP0:
 +        s->regs[FSI_MENP0] = data;
 +        break;
 +    case FSI_MENP32:
 +        s->regs[FSI_MENP32] = data;
 +        break;
 +    case FSI_MSENP0:
 +        s->regs[FSI_MENP0] |= data;
 +        break;
 +    case FSI_MSENP32:
 +        s->regs[FSI_MENP32] |= data;
 +        break;
 +    case FSI_MCENP0:
 +        s->regs[FSI_MENP0] &= ~data;
 +        break;
 +    case FSI_MCENP32:
 +        s->regs[FSI_MENP32] &= ~data;
 +        break;
 +    case FSI_MRESP0:
 +        /* Perform necessary resets leave register 0 to indicate no errors */
 +        break;
 +    case FSI_MRESB0:
 +        if (data & FSI_MRESB0_RESET_GENERAL) {
 +            device_cold_reset(DEVICE(opaque));
 +        }
 +        if (data & FSI_MRESB0_RESET_ERROR) {
 +            /* FIXME: this seems dubious */
 +            device_cold_reset(DEVICE(opaque));
 +        }
 +        break;
 +    default:
 +        s->regs[reg] = data;
 +    }
 +}
 +
 +static const struct MemoryRegionOps fsi_master_ops = {
 +    .read = fsi_master_read,
 +    .write = fsi_master_write,
 +    .endianness = DEVICE_BIG_ENDIAN,
 +};
 +
 +static void fsi_master_init(Object *o)
 +{
 +    FSIMasterState *s = FSI_MASTER(o);
 +
 +    object_initialize_child(o, "cfam", &s->cfam, TYPE_FSI_CFAM);
 +
 +    qbus_init(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &fsi_master_ops, s,
 +                          TYPE_FSI_MASTER, 0x10000000);
 +    memory_region_init(&s->opb2fsi, OBJECT(s), "fsi.opb2fsi", 0x10000000);
 +}
 +
 +static void fsi_master_realize(DeviceState *dev, Error **errp)
 +{
 +    FSIMasterState *s = FSI_MASTER(dev);
 +
 +    if (!qdev_realize(DEVICE(&s->cfam), BUS(&s->bus), errp)) {
 +        return;
 +    }
 +
 +    /* address ? */
 +    memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.mr);
 +}
 +
 +static void fsi_master_reset(DeviceState *dev)
 +{
 +    FSIMasterState *s = FSI_MASTER(dev);
 +
 +    /* Initialize registers */
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    /* ASPEED default */
 +    s->regs[FSI_MVER] = 0xe0050101;
 +}
 +
 +static void fsi_master_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->bus_type = TYPE_OP_BUS;
 +    dc->desc = "FSI Master";
 +    dc->realize = fsi_master_realize;
 +    dc->reset = fsi_master_reset;
 +}
 +
 +static const TypeInfo fsi_master_info = {
 +    .name = TYPE_FSI_MASTER,
 +    .parent = TYPE_DEVICE,
 +    .instance_init = fsi_master_init,
 +    .instance_size = sizeof(FSIMasterState),
 +    .class_init = fsi_master_class_init,
 +};
 +
 +static void fsi_register_types(void)
 +{
 +    type_register_static(&fsi_master_info);
 +}
 +
 +type_init(fsi_register_types);
 diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/meson.build
 +++ b/hw/fsi/meson.build
@@ -1 +1 @@
 -system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'))
 +system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c','fsi-master.c'))
 diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/trace-events
 +++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@ fsi_cfam_config_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64
  fsi_cfam_unimplemented_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
  fsi_cfam_unimplemented_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
  fsi_cfam_config_write_noaddr(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 +fsi_master_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 +fsi_master_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 --
 .43.0

-New patch
+[PULL 13/17] hw/fsi: Aspeed APB2OPB & On-chip peripheral bus
+From: Ninad Palsule <ninad@linux.ibm.com>
 This is a part of patchset where IBM's Flexible Service Interface is
 introduced.
 An APB-to-OPB bridge enabling access to the OPB from the ARM core in
 the AST2600. Hardware limitations prevent the OPB from being directly
 mapped into APB, so all accesses are indirect through the bridge.
 The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
 POWER processors. This now makes an appearance in the ASPEED SoC due
 to tight integration of the FSI master IP with the OPB, mainly the
 existence of an MMIO-mapping of the CFAM address straight onto a
 sub-region of the OPB address space.
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 [ clg: - moved FSIMasterState under AspeedAPB2OPBState
        - modified fsi_opb_fsi_master_address() and
          fsi_opb_opb2fsi_address()
        - instroduced fsi_aspeed_apb2opb_init()
        - reworked fsi_aspeed_apb2opb_realize()
        - removed FSIMasterState object and fsi_opb_realize()
        - simplified OPBus
        - introduced fsi_aspeed_apb2opb_rw to fix endianness issue ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  include/hw/fsi/aspeed_apb2opb.h |  46 ++++
  hw/fsi/aspeed_apb2opb.c         | 367 ++++++++++++++++++++++++++++++++
  hw/arm/Kconfig                  |   1 +
  hw/fsi/Kconfig                  |   5 +
  hw/fsi/meson.build              |   1 +
  hw/fsi/trace-events             |   2 +
 files changed, 422 insertions(+)
  create mode 100644 include/hw/fsi/aspeed_apb2opb.h
  create mode 100644 hw/fsi/aspeed_apb2opb.c
 diff --git a/include/hw/fsi/aspeed_apb2opb.h b/include/hw/fsi/aspeed_apb2opb.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/fsi/aspeed_apb2opb.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
 + * ASPEED APB2OPB Bridge
 + * IBM On-Chip Peripheral Bus
 + */
 +#ifndef FSI_ASPEED_APB2OPB_H
 +#define FSI_ASPEED_APB2OPB_H
 +
 +#include "exec/memory.h"
 +#include "hw/fsi/fsi-master.h"
 +#include "hw/sysbus.h"
 +
 +#define TYPE_FSI_OPB "fsi.opb"
 +
 +#define TYPE_OP_BUS "opb"
 +OBJECT_DECLARE_SIMPLE_TYPE(OPBus, OP_BUS)
 +
 +typedef struct OPBus {
 +    BusState bus;
 +
 +    MemoryRegion mr;
 +    AddressSpace as;
 +} OPBus;
 +
 +#define TYPE_ASPEED_APB2OPB "aspeed.apb2opb"
 +OBJECT_DECLARE_SIMPLE_TYPE(AspeedAPB2OPBState, ASPEED_APB2OPB)
 +
 +#define ASPEED_APB2OPB_NR_REGS ((0xe8 >> 2) + 1)
 +
 +#define ASPEED_FSI_NUM 2
 +
 +typedef struct AspeedAPB2OPBState {
 +    SysBusDevice parent_obj;
 +
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[ASPEED_APB2OPB_NR_REGS];
 +    qemu_irq irq;
 +
 +    OPBus opb[ASPEED_FSI_NUM];
 +    FSIMasterState fsi[ASPEED_FSI_NUM];
 +} AspeedAPB2OPBState;
 +
 +#endif /* FSI_ASPEED_APB2OPB_H */
 diff --git a/hw/fsi/aspeed_apb2opb.c b/hw/fsi/aspeed_apb2opb.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/fsi/aspeed_apb2opb.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + * Copyright (C) 2024 IBM Corp.
 + *
 + * ASPEED APB-OPB FSI interface
 + * IBM On-chip Peripheral Bus
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "qom/object.h"
 +#include "qapi/error.h"
 +#include "trace.h"
 +
 +#include "hw/fsi/aspeed_apb2opb.h"
 +#include "hw/qdev-core.h"
 +
 +#define TO_REG(x) (x >> 2)
 +
 +#define APB2OPB_VERSION                    TO_REG(0x00)
 +#define APB2OPB_TRIGGER                    TO_REG(0x04)
 +
 +#define APB2OPB_CONTROL                    TO_REG(0x08)
 +#define   APB2OPB_CONTROL_OFF              BE_GENMASK(31, 13)
 +
 +#define APB2OPB_OPB2FSI                    TO_REG(0x0c)
 +#define   APB2OPB_OPB2FSI_OFF              BE_GENMASK(31, 22)
 +
 +#define APB2OPB_OPB0_SEL                   TO_REG(0x10)
 +#define APB2OPB_OPB1_SEL                   TO_REG(0x28)
 +#define   APB2OPB_OPB_SEL_EN               BIT(0)
 +
 +#define APB2OPB_OPB0_MODE                  TO_REG(0x14)
 +#define APB2OPB_OPB1_MODE                  TO_REG(0x2c)
 +#define   APB2OPB_OPB_MODE_RD              BIT(0)
 +
 +#define APB2OPB_OPB0_XFER                  TO_REG(0x18)
 +#define APB2OPB_OPB1_XFER                  TO_REG(0x30)
 +#define   APB2OPB_OPB_XFER_FULL            BIT(1)
 +#define   APB2OPB_OPB_XFER_HALF            BIT(0)
 +
 +#define APB2OPB_OPB0_ADDR                  TO_REG(0x1c)
 +#define APB2OPB_OPB0_WRITE_DATA            TO_REG(0x20)
 +
 +#define APB2OPB_OPB1_ADDR                  TO_REG(0x34)
 +#define APB2OPB_OPB1_WRITE_DATA                  TO_REG(0x38)
 +
 +#define APB2OPB_IRQ_STS                    TO_REG(0x48)
 +#define   APB2OPB_IRQ_STS_OPB1_TX_ACK      BIT(17)
 +#define   APB2OPB_IRQ_STS_OPB0_TX_ACK      BIT(16)
 +
 +#define APB2OPB_OPB0_WRITE_WORD_ENDIAN     TO_REG(0x4c)
 +#define   APB2OPB_OPB0_WRITE_WORD_ENDIAN_BE 0x0011101b
 +#define APB2OPB_OPB0_WRITE_BYTE_ENDIAN     TO_REG(0x50)
 +#define   APB2OPB_OPB0_WRITE_BYTE_ENDIAN_BE 0x0c330f3f
 +#define APB2OPB_OPB1_WRITE_WORD_ENDIAN     TO_REG(0x54)
 +#define APB2OPB_OPB1_WRITE_BYTE_ENDIAN     TO_REG(0x58)
 +#define APB2OPB_OPB0_READ_BYTE_ENDIAN      TO_REG(0x5c)
 +#define APB2OPB_OPB1_READ_BYTE_ENDIAN      TO_REG(0x60)
 +#define   APB2OPB_OPB0_READ_WORD_ENDIAN_BE  0x00030b1b
 +
 +#define APB2OPB_OPB0_READ_DATA         TO_REG(0x84)
 +#define APB2OPB_OPB1_READ_DATA         TO_REG(0x90)
 +
 +/*
 + * The following magic values came from AST2600 data sheet
 + * The register values are defined under section "FSI controller"
 + * as initial values.
 + */
 +static const uint32_t aspeed_apb2opb_reset[ASPEED_APB2OPB_NR_REGS] = {
 +     [APB2OPB_VERSION]                = 0x000000a1,
 +     [APB2OPB_OPB0_WRITE_WORD_ENDIAN] = 0x0044eee4,
 +     [APB2OPB_OPB0_WRITE_BYTE_ENDIAN] = 0x0055aaff,
 +     [APB2OPB_OPB1_WRITE_WORD_ENDIAN] = 0x00117717,
 +     [APB2OPB_OPB1_WRITE_BYTE_ENDIAN] = 0xffaa5500,
 +     [APB2OPB_OPB0_READ_BYTE_ENDIAN]  = 0x0044eee4,
 +     [APB2OPB_OPB1_READ_BYTE_ENDIAN]  = 0x00117717
 +};
 +
 +static void fsi_opb_fsi_master_address(FSIMasterState *fsi, hwaddr addr)
 +{
 +    memory_region_transaction_begin();
 +    memory_region_set_address(&fsi->iomem, addr);
 +    memory_region_transaction_commit();
 +}
 +
 +static void fsi_opb_opb2fsi_address(FSIMasterState *fsi, hwaddr addr)
 +{
 +    memory_region_transaction_begin();
 +    memory_region_set_address(&fsi->opb2fsi, addr);
 +    memory_region_transaction_commit();
 +}
 +
 +static uint64_t fsi_aspeed_apb2opb_read(void *opaque, hwaddr addr,
 +                                        unsigned size)
 +{
 +    AspeedAPB2OPBState *s = ASPEED_APB2OPB(opaque);
 +    unsigned int reg = TO_REG(addr);
 +
 +    trace_fsi_aspeed_apb2opb_read(addr, size);
 +
 +    if (reg >= ASPEED_APB2OPB_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
 +                      __func__, addr, size);
 +        return 0;
 +    }
 +
 +    return s->regs[reg];
 +}
 +
 +static MemTxResult fsi_aspeed_apb2opb_rw(AddressSpace *as, hwaddr addr,
 +                                         MemTxAttrs attrs, uint32_t *data,
 +                                         uint32_t size, bool is_write)
 +{
 +    MemTxResult res;
 +
 +    if (is_write) {
 +        switch (size) {
 +        case 4:
 +            address_space_stl_le(as, addr, *data, attrs, &res);
 +            break;
 +        case 2:
 +            address_space_stw_le(as, addr, *data, attrs, &res);
 +            break;
 +        case 1:
 +            address_space_stb(as, addr, *data, attrs, &res);
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    } else {
 +        switch (size) {
 +        case 4:
 +            *data = address_space_ldl_le(as, addr, attrs, &res);
 +            break;
 +        case 2:
 +            *data = address_space_lduw_le(as, addr, attrs, &res);
 +            break;
 +        case 1:
 +            *data = address_space_ldub(as, addr, attrs, &res);
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    }
 +    return res;
 +}
 +
 +static void fsi_aspeed_apb2opb_write(void *opaque, hwaddr addr, uint64_t data,
 +                                     unsigned size)
 +{
 +    AspeedAPB2OPBState *s = ASPEED_APB2OPB(opaque);
 +    unsigned int reg = TO_REG(addr);
 +
 +    trace_fsi_aspeed_apb2opb_write(addr, size, data);
 +
 +    if (reg >= ASPEED_APB2OPB_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n",
 +                      __func__, addr, size);
 +        return;
 +    }
 +
 +    switch (reg) {
 +    case APB2OPB_CONTROL:
 +        fsi_opb_fsi_master_address(&s->fsi[0],
 +                data & APB2OPB_CONTROL_OFF);
 +        break;
 +    case APB2OPB_OPB2FSI:
 +        fsi_opb_opb2fsi_address(&s->fsi[0],
 +                data & APB2OPB_OPB2FSI_OFF);
 +        break;
 +    case APB2OPB_OPB0_WRITE_WORD_ENDIAN:
 +        if (data != APB2OPB_OPB0_WRITE_WORD_ENDIAN_BE) {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "%s: Bridge needs to be driven as BE (0x%x)\n",
 +                          __func__, APB2OPB_OPB0_WRITE_WORD_ENDIAN_BE);
 +        }
 +        break;
 +    case APB2OPB_OPB0_WRITE_BYTE_ENDIAN:
 +        if (data != APB2OPB_OPB0_WRITE_BYTE_ENDIAN_BE) {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "%s: Bridge needs to be driven as BE (0x%x)\n",
 +                          __func__, APB2OPB_OPB0_WRITE_BYTE_ENDIAN_BE);
 +        }
 +        break;
 +    case APB2OPB_OPB0_READ_BYTE_ENDIAN:
 +        if (data != APB2OPB_OPB0_READ_WORD_ENDIAN_BE) {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "%s: Bridge needs to be driven as BE (0x%x)\n",
 +                          __func__, APB2OPB_OPB0_READ_WORD_ENDIAN_BE);
 +        }
 +        break;
 +    case APB2OPB_TRIGGER:
 +    {
 +        uint32_t opb, op_mode, op_size, op_addr, op_data;
 +        MemTxResult result;
 +        bool is_write;
 +        int index;
 +        AddressSpace *as;
 +
 +        assert((s->regs[APB2OPB_OPB0_SEL] & APB2OPB_OPB_SEL_EN) ^
 +               (s->regs[APB2OPB_OPB1_SEL] & APB2OPB_OPB_SEL_EN));
 +
 +        if (s->regs[APB2OPB_OPB0_SEL] & APB2OPB_OPB_SEL_EN) {
 +            opb = 0;
 +            op_mode = s->regs[APB2OPB_OPB0_MODE];
 +            op_size = s->regs[APB2OPB_OPB0_XFER];
 +            op_addr = s->regs[APB2OPB_OPB0_ADDR];
 +            op_data = s->regs[APB2OPB_OPB0_WRITE_DATA];
 +        } else if (s->regs[APB2OPB_OPB1_SEL] & APB2OPB_OPB_SEL_EN) {
 +            opb = 1;
 +            op_mode = s->regs[APB2OPB_OPB1_MODE];
 +            op_size = s->regs[APB2OPB_OPB1_XFER];
 +            op_addr = s->regs[APB2OPB_OPB1_ADDR];
 +            op_data = s->regs[APB2OPB_OPB1_WRITE_DATA];
 +        } else {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "%s: Invalid operation: 0x%"HWADDR_PRIx" for %u\n",
 +                          __func__, addr, size);
 +            return;
 +        }
 +
 +        if (op_size & ~(APB2OPB_OPB_XFER_HALF | APB2OPB_OPB_XFER_FULL)) {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "OPB transaction failed: Unrecognized access width: %d\n",
 +                          op_size);
 +            return;
 +        }
 +
 +        op_size += 1;
 +        is_write = !(op_mode & APB2OPB_OPB_MODE_RD);
 +        index = opb ? APB2OPB_OPB1_READ_DATA : APB2OPB_OPB0_READ_DATA;
 +        as = &s->opb[opb].as;
 +
 +        result = fsi_aspeed_apb2opb_rw(as, op_addr, MEMTXATTRS_UNSPECIFIED,
 +                                       &op_data, op_size, is_write);
 +        if (result != MEMTX_OK) {
 +            qemu_log_mask(LOG_GUEST_ERROR, "%s: OPB %s failed @%08x\n",
 +                          __func__, is_write ? "write" : "read", op_addr);
 +            return;
 +        }
 +
 +        if (!is_write) {
 +            s->regs[index] = op_data;
 +        }
 +
 +        s->regs[APB2OPB_IRQ_STS] |= opb ? APB2OPB_IRQ_STS_OPB1_TX_ACK
 +            : APB2OPB_IRQ_STS_OPB0_TX_ACK;
 +        break;
 +    }
 +    }
 +
 +    s->regs[reg] = data;
 +}
 +
 +static const struct MemoryRegionOps aspeed_apb2opb_ops = {
 +    .read = fsi_aspeed_apb2opb_read,
 +    .write = fsi_aspeed_apb2opb_write,
 +    .valid.max_access_size = 4,
 +    .valid.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +    .impl.min_access_size = 4,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void fsi_aspeed_apb2opb_init(Object *o)
 +{
 +    AspeedAPB2OPBState *s = ASPEED_APB2OPB(o);
 +    int i;
 +
 +    for (i = 0; i < ASPEED_FSI_NUM; i++) {
 +        object_initialize_child(o, "fsi-master[*]", &s->fsi[i],
 +                                TYPE_FSI_MASTER);
 +    }
 +}
 +
 +static void fsi_aspeed_apb2opb_realize(DeviceState *dev, Error **errp)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    AspeedAPB2OPBState *s = ASPEED_APB2OPB(dev);
 +    int i;
 +
 +    /*
 +     * TODO: The OPBus model initializes the OPB address space in
 +     * the .instance_init handler and this is problematic for test
 +     * device-introspect-test. To avoid a memory corruption and a QEMU
 +     * crash, qbus_init() should be called from realize(). Something to
 +     * improve. Possibly, OPBus could also be removed.
 +     */
 +    for (i = 0; i < ASPEED_FSI_NUM; i++) {
 +        qbus_init(&s->opb[i], sizeof(s->opb[i]), TYPE_OP_BUS, DEVICE(s),
 +                  NULL);
 +    }
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_apb2opb_ops, s,
 +                          TYPE_ASPEED_APB2OPB, 0x1000);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +
 +    for (i = 0; i < ASPEED_FSI_NUM; i++) {
 +        if (!qdev_realize(DEVICE(&s->fsi[i]), BUS(&s->opb[i]), errp)) {
 +            return;
 +        }
 +
 +        memory_region_add_subregion(&s->opb[i].mr, 0x80000000,
 +                &s->fsi[i].iomem);
 +
 +        memory_region_add_subregion(&s->opb[i].mr, 0xa0000000,
 +                &s->fsi[i].opb2fsi);
 +    }
 +}
 +
 +static void fsi_aspeed_apb2opb_reset(DeviceState *dev)
 +{
 +    AspeedAPB2OPBState *s = ASPEED_APB2OPB(dev);
 +
 +    memcpy(s->regs, aspeed_apb2opb_reset, ASPEED_APB2OPB_NR_REGS);
 +}
 +
 +static void fsi_aspeed_apb2opb_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "ASPEED APB2OPB Bridge";
 +    dc->realize = fsi_aspeed_apb2opb_realize;
 +    dc->reset = fsi_aspeed_apb2opb_reset;
 +}
 +
 +static const TypeInfo aspeed_apb2opb_info = {
 +    .name = TYPE_ASPEED_APB2OPB,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_init = fsi_aspeed_apb2opb_init,
 +    .instance_size = sizeof(AspeedAPB2OPBState),
 +    .class_init = fsi_aspeed_apb2opb_class_init,
 +};
 +
 +static void aspeed_apb2opb_register_types(void)
 +{
 +    type_register_static(&aspeed_apb2opb_info);
 +}
 +
 +type_init(aspeed_apb2opb_register_types);
 +
 +static void fsi_opb_init(Object *o)
 +{
 +    OPBus *opb = OP_BUS(o);
 +
 +    memory_region_init(&opb->mr, 0, TYPE_FSI_OPB, UINT32_MAX);
 +    address_space_init(&opb->as, &opb->mr, TYPE_FSI_OPB);
 +}
 +
 +static const TypeInfo opb_info = {
 +    .name = TYPE_OP_BUS,
 +    .parent = TYPE_BUS,
 +    .instance_init = fsi_opb_init,
 +    .instance_size = sizeof(OPBus),
 +};
 +
 +static void fsi_opb_register_types(void)
 +{
 +    type_register_static(&opb_info);
 +}
 +
 +type_init(fsi_opb_register_types);
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ASPEED_SOC
      select LED
      select PMBUS
      select MAX31785
 +    select FSI_APB2OPB_ASPEED
  config MPS2
      bool
 diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/Kconfig
 +++ b/hw/fsi/Kconfig
@@ -XXX,XX +XXX,XX @@
 +config FSI_APB2OPB_ASPEED
 +    bool
 +    depends on ASPEED_SOC
 +    select FSI
 +
  config FSI
      bool
 diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/meson.build
 +++ b/hw/fsi/meson.build
@@ -1 +1,2 @@
  system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c','fsi-master.c'))
 +system_ss.add(when: 'CONFIG_FSI_APB2OPB_ASPEED', if_true: files('aspeed_apb2opb.c'))
 diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/fsi/trace-events
 +++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@ fsi_cfam_unimplemented_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%"
  fsi_cfam_config_write_noaddr(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
  fsi_master_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
  fsi_master_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 +fsi_aspeed_apb2opb_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 +fsi_aspeed_apb2opb_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 --
 .43.0

-[PULL 07/12] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
+[PULL 14/17] hw/arm: Hook up FSI module in AST2600
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Ninad Palsule <ninad@linux.ibm.com>
-TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
+This patchset introduces IBM's Flexible Service Interface(FSI).
 In few commits we'll add more fields, but to keep
 review process simple, don't add any yet.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Time for some fun with inter-processor buses. FSI allows a service
 processor access to the internal buses of a host POWER processor to
 perform configuration or debugging.
 FSI has long existed in POWER processes and so comes with some baggage,
 including how it has been integrated into the ASPEED SoC.
 Working backwards from the POWER processor, the fundamental pieces of
 interest for the implementation are:
 . The Common FRU Access Macro (CFAM), an address space containing
    various "engines" that drive accesses on buses internal and external
    to the POWER chip. Examples include the SBEFIFO and I2C masters. The
    engines hang off of an internal Local Bus (LBUS) which is described
    by the CFAM configuration block.
 . The FSI slave: The slave is the terminal point of the FSI bus for
    FSI symbols addressed to it. Slaves can be cascaded off of one
    another. The slave's configuration registers appear in address space
    of the CFAM to which it is attached.
 . The FSI master: A controller in the platform service processor (e.g.
    BMC) driving CFAM engine accesses into the POWER chip. At the
    hardware level FSI is a bit-based protocol supporting synchronous and
    DMA-driven accesses of engines in a CFAM.
 . The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
    POWER processors. This now makes an appearance in the ASPEED SoC due
    to tight integration of the FSI master IP with the OPB, mainly the
    existence of an MMIO-mapping of the CFAM address straight onto a
    sub-region of the OPB address space.
 . An APB-to-OPB bridge enabling access to the OPB from the ARM core in
    the AST2600. Hardware limitations prevent the OPB from being directly
    mapped into APB, so all accesses are indirect through the bridge.
 The implementation appears as following in the qemu device tree:
     (qemu) info qtree
     bus: main-system-bus
       type System
       ...
       dev: aspeed.apb2opb, id ""
         gpio-out "sysbus-irq" 1
         mmio 000000001e79b000/0000000000001000
         bus: opb.1
           type opb
           dev: fsi.master, id ""
             bus: fsi.bus.1
               type fsi.bus
               dev: cfam.config, id ""
               dev: cfam, id ""
                 bus: fsi.lbus.1
                   type lbus
                   dev: scratchpad, id ""
                     address = 0 (0x0)
         bus: opb.0
           type opb
           dev: fsi.master, id ""
             bus: fsi.bus.0
               type fsi.bus
               dev: cfam.config, id ""
               dev: cfam, id ""
                 bus: fsi.lbus.0
                   type lbus
                   dev: scratchpad, id ""
                     address = 0 (0x0)
 The LBUS is modelled to maintain the qdev bus hierarchy and to take
 advantage of the object model to automatically generate the CFAM
 configuration block. The configuration block presents engines in the
 order they are attached to the CFAM's LBUS. Engine implementations
 should subclass the LBusDevice and set the 'config' member of
 LBusDeviceClass to match the engine's type.
 CFAM designs offer a lot of flexibility, for instance it is possible for
 a CFAM to be simultaneously driven from multiple FSI links. The modeling
 is not so complete; it's assumed that each CFAM is attached to a single
 FSI slave (as a consequence the CFAM subclasses the FSI slave).
 As for FSI, its symbols and wire-protocol are not modelled at all. This
 is not necessary to get FSI off the ground thanks to the mapping of the
 CFAM address space onto the OPB address space - the models follow this
 directly and map the CFAM memory region into the OPB's memory region.
 Future work includes supporting more advanced accesses that drive the
 FSI master directly rather than indirectly via the CFAM mapping, which
 will require implementing the FSI state machine and methods for each of
 the FSI symbols on the slave. Further down the track we can also look at
 supporting the bitbanged SoftFSI drivers in Linux by extending the FSI
 slave model to resolve sequences of GPIO IRQs into FSI symbols, and
 calling the associated symbol method on the slave to map the access onto
 the CFAM.
 Testing:
     Tested by reading cfam config address 0 on rainier machine type.
     root@p10bmc:~# pdbg -a getcfam 0x0
     p0: 0x0 = 0xc0022d15
 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h |  7 +++++++
+ include/hw/arm/aspeed_soc.h |  4 ++++
- hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
+ hw/arm/aspeed_ast2600.c     | 19 +++++++++++++++++++
-files changed, 20 insertions(+), 13 deletions(-)
+files changed, 23 insertions(+)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/aspeed_lpc.h"
+ #include "hw/misc/unimp.h"
+ #include "hw/misc/aspeed_peci.h"
++#include "hw/fsi/aspeed_apb2opb.h"
+ #include "hw/char/serial.h"
+ #define ASPEED_SPIS_NUM  2
 @@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
+     UnimplementedDeviceState udc;
+     UnimplementedDeviceState sgpiom;
+     UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
++    AspeedAPB2OPBState fsi[2];
+ };
  #define TYPE_ASPEED_SOC "aspeed-soc"
- OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
+@@ -XXX,XX +XXX,XX @@ enum {
+     ASPEED_DEV_SGPIOM,
-+struct Aspeed2600SoCState {
+     ASPEED_DEV_JTAG0,
-+    AspeedSoCState parent;
+     ASPEED_DEV_JTAG1,
-+};
++    ASPEED_DEV_FSI1,
-+
++    ASPEED_DEV_FSI2,
 +#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
 +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 +
  struct Aspeed10x0SoCState {
      AspeedSoCState parent;
  };
+ #define ASPEED_SOC_SPI_BOOT_ADDR 0x0
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
-     sc->get_irq      = aspeed_soc_ast2600_get_irq;
+     [ASPEED_DEV_UART12]    = 0x1E790600,
      [ASPEED_DEV_UART13]    = 0x1E790700,
      [ASPEED_DEV_VUART]     = 0x1E787000,
 +    [ASPEED_DEV_FSI1]      = 0x1E79B000,
 +    [ASPEED_DEV_FSI2]      = 0x1E79B100,
      [ASPEED_DEV_I3C]       = 0x1E7A0000,
      [ASPEED_DEV_SDRAM]     = 0x80000000,
  };
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
      [ASPEED_DEV_ETH4]      = 33,
      [ASPEED_DEV_KCS]       = 138,   /* 138 -> 142 */
      [ASPEED_DEV_DP]        = 62,
 +    [ASPEED_DEV_FSI1]      = 100,
 +    [ASPEED_DEV_FSI2]      = 101,
      [ASPEED_DEV_I3C]       = 102,   /* 102 -> 107 */
  };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      object_initialize_child(obj, "emmc-boot-controller",
                              &s->emmc_boot_controller,
                              TYPE_UNIMPLEMENTED_DEVICE);
 +
 +    for (i = 0; i < ASPEED_FSI_NUM; i++) {
 +        object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB);
 +    }
  }
--static const TypeInfo aspeed_soc_ast2600_type_info = {
+ /*
--    .name           = "ast2600-a3",
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
--    .parent         = TYPE_ASPEED_SOC,
+         return;
--    .instance_size  = sizeof(AspeedSoCState),
+     }
--    .instance_init  = aspeed_soc_ast2600_init,
+     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
--    .class_init     = aspeed_soc_ast2600_class_init,
++
--    .class_size     = sizeof(AspeedSoCClass),
++    /* FSI */
-+static const TypeInfo aspeed_soc_ast2600_types[] = {
++    for (i = 0; i < ASPEED_FSI_NUM; i++) {
-+    {
++        if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) {
-+        .name           = TYPE_ASPEED2600_SOC,
++            return;
-+        .parent         = TYPE_ASPEED_SOC,
++        }
-+        .instance_size  = sizeof(Aspeed2600SoCState),
++        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0,
-+        .abstract       = true,
++                        sc->memmap[ASPEED_DEV_FSI1 + i]);
-+    }, {
++        sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0,
-+        .name           = "ast2600-a3",
++                           aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i));
-+        .parent         = TYPE_ASPEED2600_SOC,
++    }
-+        .instance_init  = aspeed_soc_ast2600_init,
+ }
-+        .class_init     = aspeed_soc_ast2600_class_init,
-+    },
+ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
  };
 -static void aspeed_soc_register_types(void)
 -{
 -    type_register_static(&aspeed_soc_ast2600_type_info);
 -};
 -
 -type_init(aspeed_soc_register_types)
 +DEFINE_TYPES(aspeed_soc_ast2600_types)
 --
-.41.0
+.43.0

-New patch
+[PULL 15/17] hw/fsi: Added qtest
+From: Ninad Palsule <ninad@linux.ibm.com>
 Added basic qtests for FSI model.
 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Acked-by: Thomas Huth <thuth@redhat.com>
 [ clg: aspeed-fsi-test.c -> aspeed_fsi-test.c to match other filenames ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  tests/qtest/aspeed_fsi-test.c | 205 ++++++++++++++++++++++++++++++++++
  tests/qtest/meson.build       |   1 +
 files changed, 206 insertions(+)
  create mode 100644 tests/qtest/aspeed_fsi-test.c
 diff --git a/tests/qtest/aspeed_fsi-test.c b/tests/qtest/aspeed_fsi-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/aspeed_fsi-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTest testcases for IBM's Flexible Service Interface (FSI)
 + *
 + * Copyright (c) 2023 IBM Corporation
 + *
 + * Authors:
 + *   Ninad Palsule <ninad@linux.ibm.com>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
 +#include <glib/gstdio.h>
 +
 +#include "qemu/module.h"
 +#include "libqtest-single.h"
 +
 +/* Registers from ast2600 specifications */
 +#define ASPEED_FSI_ENGINER_TRIGGER   0x04
 +#define ASPEED_FSI_OPB0_BUS_SELECT   0x10
 +#define ASPEED_FSI_OPB1_BUS_SELECT   0x28
 +#define ASPEED_FSI_OPB0_RW_DIRECTION 0x14
 +#define ASPEED_FSI_OPB1_RW_DIRECTION 0x2c
 +#define ASPEED_FSI_OPB0_XFER_SIZE    0x18
 +#define ASPEED_FSI_OPB1_XFER_SIZE    0x30
 +#define ASPEED_FSI_OPB0_BUS_ADDR     0x1c
 +#define ASPEED_FSI_OPB1_BUS_ADDR     0x34
 +#define ASPEED_FSI_INTRRUPT_CLEAR    0x40
 +#define ASPEED_FSI_INTRRUPT_STATUS   0x48
 +#define ASPEED_FSI_OPB0_BUS_STATUS   0x80
 +#define ASPEED_FSI_OPB1_BUS_STATUS   0x8c
 +#define ASPEED_FSI_OPB0_READ_DATA    0x84
 +#define ASPEED_FSI_OPB1_READ_DATA    0x90
 +
 +/*
 + * FSI Base addresses from the ast2600 specifications.
 + */
 +#define AST2600_OPB_FSI0_BASE_ADDR 0x1e79b000
 +#define AST2600_OPB_FSI1_BASE_ADDR 0x1e79b100
 +
 +static uint32_t aspeed_fsi_base_addr;
 +
 +static uint32_t aspeed_fsi_readl(QTestState *s, uint32_t reg)
 +{
 +    return qtest_readl(s, aspeed_fsi_base_addr + reg);
 +}
 +
 +static void aspeed_fsi_writel(QTestState *s, uint32_t reg, uint32_t val)
 +{
 +    qtest_writel(s, aspeed_fsi_base_addr + reg, val);
 +}
 +
 +/* Setup base address and select register */
 +static void test_fsi_setup(QTestState *s, uint32_t base_addr)
 +{
 +    uint32_t curval;
 +
 +    aspeed_fsi_base_addr = base_addr;
 +
 +    /* Set the base select register */
 +    if (base_addr == AST2600_OPB_FSI0_BASE_ADDR) {
 +        /* Unselect FSI1 */
 +        aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x0);
 +        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
 +        g_assert_cmpuint(curval, ==, 0x0);
 +
 +        /* Select FSI0 */
 +        aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x1);
 +        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
 +        g_assert_cmpuint(curval, ==, 0x1);
 +    } else if (base_addr == AST2600_OPB_FSI1_BASE_ADDR) {
 +        /* Unselect FSI0 */
 +        aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x0);
 +        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
 +        g_assert_cmpuint(curval, ==, 0x0);
 +
 +        /* Select FSI1 */
 +        aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x1);
 +        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
 +        g_assert_cmpuint(curval, ==, 0x1);
 +    } else {
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void test_fsi_reg_change(QTestState *s, uint32_t reg, uint32_t newval)
 +{
 +    uint32_t base;
 +    uint32_t curval;
 +
 +    base = aspeed_fsi_readl(s, reg);
 +    aspeed_fsi_writel(s, reg, newval);
 +    curval = aspeed_fsi_readl(s, reg);
 +    g_assert_cmpuint(curval, ==, newval);
 +    aspeed_fsi_writel(s, reg, base);
 +    curval = aspeed_fsi_readl(s, reg);
 +    g_assert_cmpuint(curval, ==, base);
 +}
 +
 +static void test_fsi0_master_regs(const void *data)
 +{
 +    QTestState *s = (QTestState *)data;
 +
 +    test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
 +
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0xF3F4F514);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB0_XFER_SIZE, 0xF3F4F518);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xF3F4F51c);
 +    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
 +    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_STATUS, 0xF3F4F580);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB0_READ_DATA, 0xF3F4F584);
 +}
 +
 +static void test_fsi1_master_regs(const void *data)
 +{
 +    QTestState *s = (QTestState *)data;
 +
 +    test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
 +
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0xF3F4F514);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB1_XFER_SIZE, 0xF3F4F518);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xF3F4F51c);
 +    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
 +    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_STATUS, 0xF3F4F580);
 +    test_fsi_reg_change(s, ASPEED_FSI_OPB1_READ_DATA, 0xF3F4F584);
 +}
 +
 +static void test_fsi0_getcfam_addr0(const void *data)
 +{
 +    QTestState *s = (QTestState *)data;
 +    uint32_t curval;
 +
 +    test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
 +
 +    /* Master access direction read */
 +    aspeed_fsi_writel(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0x1);
 +    /* word */
 +    aspeed_fsi_writel(s, ASPEED_FSI_OPB0_XFER_SIZE, 0x3);
 +    /* Address */
 +    aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xa0000000);
 +    aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
 +    aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
 +
 +    curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
 +    g_assert_cmpuint(curval, ==, 0x10000);
 +    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_STATUS);
 +    g_assert_cmpuint(curval, ==, 0x0);
 +    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_READ_DATA);
 +    g_assert_cmpuint(curval, ==, 0x152d02c0);
 +}
 +
 +static void test_fsi1_getcfam_addr0(const void *data)
 +{
 +    QTestState *s = (QTestState *)data;
 +    uint32_t curval;
 +
 +    test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
 +
 +    /* Master access direction read */
 +    aspeed_fsi_writel(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0x1);
 +
 +    aspeed_fsi_writel(s, ASPEED_FSI_OPB1_XFER_SIZE, 0x3);
 +    aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xa0000000);
 +    aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
 +    aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
 +
 +    curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
 +    g_assert_cmpuint(curval, ==, 0x20000);
 +    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_STATUS);
 +    g_assert_cmpuint(curval, ==, 0x0);
 +    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_READ_DATA);
 +    g_assert_cmpuint(curval, ==, 0x152d02c0);
 +}
 +
 +int main(int argc, char **argv)
 +{
 +    int ret = -1;
 +    QTestState *s;
 +
 +    g_test_init(&argc, &argv, NULL);
 +
 +    s = qtest_init("-machine ast2600-evb ");
 +
 +    /* Tests for OPB/FSI0 */
 +    qtest_add_data_func("/aspeed-fsi-test/test_fsi0_master_regs", s,
 +                        test_fsi0_master_regs);
 +
 +    qtest_add_data_func("/aspeed-fsi-test/test_fsi0_getcfam_addr0", s,
 +                        test_fsi0_getcfam_addr0);
 +
 +    /* Tests for OPB/FSI1 */
 +    qtest_add_data_func("/aspeed-fsi-test/test_fsi1_master_regs", s,
 +                        test_fsi1_master_regs);
 +
 +    qtest_add_data_func("/aspeed-fsi-test/test_fsi1_getcfam_addr0", s,
 +                        test_fsi1_getcfam_addr0);
 +
 +    ret = g_test_run();
 +    qtest_quit(s);
 +
 +    return ret;
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
    (config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
    (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
    (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
 +  (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
    ['arm-cpu-features',
     'boot-serial-test']
 --
 .43.0

-New patch
+[PULL 16/17] hw/fsi: Added FSI documentation
+From: Ninad Palsule <ninad@linux.ibm.com>
+Documentation for IBM FSI model.
+Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
+[ clg : - Removed source file list
+        - Fixed aspeed machine reference ]
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+---
+ docs/specs/fsi.rst   | 122 +++++++++++++++++++++++++++++++++++++++++++
+ docs/specs/index.rst |   1 +
+files changed, 123 insertions(+)
+ create mode 100644 docs/specs/fsi.rst
+diff --git a/docs/specs/fsi.rst b/docs/specs/fsi.rst
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/docs/specs/fsi.rst
+@@ -XXX,XX +XXX,XX @@
++======================================
++IBM's Flexible Service Interface (FSI)
++======================================
++
++The QEMU FSI emulation implements hardware interfaces between ASPEED SOC, FSI
++master/slave and the end engine.
++
++FSI is a point-to-point two wire interface which is capable of supporting
++distances of up to 4 meters. FSI interfaces have been used successfully for
++many years in IBM servers to attach IBM Flexible Support Processors(FSP) to
++CPUs and IBM ASICs.
++
++FSI allows a service processor access to the internal buses of a host POWER
++processor to perform configuration or debugging. FSI has long existed in POWER
++processes and so comes with some baggage, including how it has been integrated
++into the ASPEED SoC.
++
++Working backwards from the POWER processor, the fundamental pieces of interest
++for the implementation are: (see the `FSI specification`_ for more details)
++
++1. The Common FRU Access Macro (CFAM), an address space containing various
++   "engines" that drive accesses on buses internal and external to the POWER
++   chip. Examples include the SBEFIFO and I2C masters. The engines hang off of
++   an internal Local Bus (LBUS) which is described by the CFAM configuration
++   block.
++
++2. The FSI slave: The slave is the terminal point of the FSI bus for FSI
++   symbols addressed to it. Slaves can be cascaded off of one another. The
++   slave's configuration registers appear in address space of the CFAM to
++   which it is attached.
++
++3. The FSI master: A controller in the platform service processor (e.g. BMC)
++   driving CFAM engine accesses into the POWER chip. At the hardware level
++   FSI is a bit-based protocol supporting synchronous and DMA-driven accesses
++   of engines in a CFAM.
++
++4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER
++   processors. This now makes an appearance in the ASPEED SoC due to tight
++   integration of the FSI master IP with the OPB, mainly the existence of an
++   MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
++   address space.
++
++5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
++   AST2600. Hardware limitations prevent the OPB from being directly mapped
++   into APB, so all accesses are indirect through the bridge.
++
++The LBUS is modelled to maintain the qdev bus hierarchy and to take advantages
++of the object model to automatically generate the CFAM configuration block.
++The configuration block presents engines in the order they are attached to the
++CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the
++'config' member of LBusDeviceClass to match the engine's type.
++
++CFAM designs offer a lot of flexibility, for instance it is possible for a
++CFAM to be simultaneously driven from multiple FSI links. The modeling is not
++so complete; it's assumed that each CFAM is attached to a single FSI slave (as
++a consequence the CFAM subclasses the FSI slave).
++
++As for FSI, its symbols and wire-protocol are not modelled at all. This is not
++necessary to get FSI off the ground thanks to the mapping of the CFAM address
++space onto the OPB address space - the models follow this directly and map the
++CFAM memory region into the OPB's memory region.
++
++The following commands start the ``rainier-bmc`` machine with built-in FSI
++model. There are no model specific arguments. Please check this document to
++learn more about Aspeed ``rainier-bmc`` machine: (:doc:`../../system/arm/aspeed`)
++
++.. code-block:: console
++
++  qemu-system-arm -M rainier-bmc -nographic \
++  -kernel fitImage-linux.bin \
++  -dtb aspeed-bmc-ibm-rainier.dtb \
++  -initrd obmc-phosphor-initramfs.rootfs.cpio.xz \
++  -drive file=obmc-phosphor-image.rootfs.wic.qcow2,if=sd,index=2 \
++  -append "rootwait console=ttyS4,115200n8 root=PARTLABEL=rofs-a"
++
++The implementation appears as following in the qemu device tree:
++
++.. code-block:: console
++
++  (qemu) info qtree
++  bus: main-system-bus
++    type System
++    ...
++    dev: aspeed.apb2opb, id ""
++      gpio-out "sysbus-irq" 1
++      mmio 000000001e79b000/0000000000001000
++      bus: opb.1
++        type opb
++        dev: fsi.master, id ""
++          bus: fsi.bus.1
++            type fsi.bus
++            dev: cfam.config, id ""
++            dev: cfam, id ""
++              bus: lbus.1
++                type lbus
++                dev: scratchpad, id ""
++                  address = 0 (0x0)
++      bus: opb.0
++        type opb
++        dev: fsi.master, id ""
++          bus: fsi.bus.0
++            type fsi.bus
++            dev: cfam.config, id ""
++            dev: cfam, id ""
++              bus: lbus.0
++                type lbus
++                dev: scratchpad, id ""
++                  address = 0 (0x0)
++
++pdbg is a simple application to allow debugging of the host POWER processors
++from the BMC. (see the `pdbg source repository`_ for more details)
++
++.. code-block:: console
++
++  root@p10bmc:~# pdbg -a getcfam 0x0
++  p0: 0x0 = 0xc0022d15
++
++.. _FSI specification:
++   https://openpowerfoundation.org/specifications/fsi/
++
++.. _pdbg source repository:
++   https://github.com/open-power/pdbg
+diff --git a/docs/specs/index.rst b/docs/specs/index.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/specs/index.rst
++++ b/docs/specs/index.rst
+@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
+    acpi_erst
+    sev-guest-firmware
+    fw_cfg
++   fsi
+    vmw_pvscsi-spec
+    edu
+    ivshmem-spec
+--
+.43.0

-[PULL 01/12] MAINTAINERS: aspeed: Update Andrew's email address
+[PULL 17/17] hw/fsi: Update MAINTAINER list
-From: Andrew Jeffery <andrew@codeconstruct.com.au>
+From: Ninad Palsule <ninad@linux.ibm.com>
-I've changed employers, have company email that deals with patch-based
+Add maintainer for IBM FSI model
 workflows without too much of a headache, and am trying to steer some
 content out of my personal mail.
-Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
+Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 [ clg: - slight change in commit log
        - fixed file list ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- MAINTAINERS | 2 +-
+ MAINTAINERS | 9 +++++++++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 9 insertions(+)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: docs/system/arm/emcraft-sf2.rst
+@@ -XXX,XX +XXX,XX @@ F: tests/qtest/adm1272-test.c
- ASPEED BMCs
+ F: tests/qtest/max34451-test.c
- M: Cédric Le Goater <clg@kaod.org>
+ F: tests/qtest/isl_pmbus_vr-test.c
- M: Peter Maydell <peter.maydell@linaro.org>
--R: Andrew Jeffery <andrew@aj.id.au>
++FSI
-+R: Andrew Jeffery <andrew@codeconstruct.com.au>
++M: Ninad Palsule <ninad@linux.ibm.com>
- R: Joel Stanley <joel@jms.id.au>
++R: Cédric Le Goater <clg@kaod.org>
- L: qemu-arm@nongnu.org
++S: Maintained
- S: Maintained
++F: hw/fsi/*
 +F: include/hw/fsi/*
 +F: docs/specs/fsi.rst
 +F: tests/qtest/aspeed_fsi-test.c
 +
  Firmware schema specifications
  M: Philippe Mathieu-Daudé <philmd@linaro.org>
  R: Daniel P. Berrange <berrange@redhat.com>
 --
-.41.0
+.43.0

The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:

Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20231025

for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:

hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)

----------------------------------------------------------------
aspeed queue:

* Update of Andrew's email
* Split of AspeedSoCState per 2400/2600/10x0

----------------------------------------------------------------
Andrew Jeffery (1):
      MAINTAINERS: aspeed: Update Andrew's email address

Philippe Mathieu-Daudé (11):
      hw/arm/aspeed: Extract code common to all boards to a common file
      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
      hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
      hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
      hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
      hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
      hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
      hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
      hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState

MAINTAINERS                               |   2 +-
 include/hw/arm/aspeed_soc.h               |  35 +++++-
 hw/arm/aspeed.c                           | 101 +++++++--------
 hw/arm/aspeed_ast10x0.c                   |  53 ++++----
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
 hw/arm/aspeed_ast2600.c                   |  75 ++++++------
 hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
 hw/arm/fby35.c                            |  27 ++--
 hw/arm/meson.build                        |   3 +-
 9 files changed, 363 insertions(+), 284 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
 create mode 100644 hw/arm/aspeed_soc_common.c

From: Philippe Mathieu-Daudé <philmd@linaro.org>

aspeed_soc.c contains definitions specific to the AST2400
and AST2500 SoCs, but also some definitions for other AST
SoCs: move them to a common file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_soc.c        |  96 -------------------------------
 hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
 hw/arm/meson.build         |   1 +
 3 files changed, 115 insertions(+), 96 deletions(-)
 create mode 100644 hw/arm/aspeed_soc_common.c

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
 };
 
 type_init(aspeed_soc_register_types);
-
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-{
-    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-}
-
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    SerialMM *smm;
-
-    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
-        smm = &s->uart[i];
-
-        /* Chardev property is set by the machine. */
-        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
-        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
-        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
-        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
-        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
-            return false;
-        }
-
-        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
-        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
-    }
-
-    return true;
-}
-
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    int i = dev - ASPEED_DEV_UART1;
-
-    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
-    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
-}
-
-/*
- * SDMC should be realized first to get correct RAM size and max size
- * values
- */
-bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    ram_addr_t ram_size, max_ram_size;
-
-    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
-                                        &error_abort);
-    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
-                                            &error_abort);
-
-    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
-                       max_ram_size);
-    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-
-    /*
-     * Add a memory region beyond the RAM region to let firmwares scan
-     * the address space with load/store and guess how much RAM the
-     * SoC has.
-     */
-    if (ram_size < max_ram_size) {
-        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-
-        qdev_prop_set_string(dev, "name", "ram-empty");
-        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
-        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
-            return false;
-        }
-
-        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
-                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
-    }
-
-    memory_region_add_subregion(s->memory,
-                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
-    return true;
-}
-
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
-{
-    memory_region_add_subregion(s->memory, addr,
-                                sysbus_mmio_get_region(dev, n));
-}
-
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
-                                   const char *name, hwaddr addr, uint64_t size)
-{
-    qdev_prop_set_string(DEVICE(dev), "name", name);
-    qdev_prop_set_uint64(DEVICE(dev), "size", size);
-    sysbus_realize(dev, &error_abort);
-
-    memory_region_add_subregion_overlap(s->memory, addr,
-                                        sysbus_mmio_get_region(dev, 0), -1000);
-}
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED SoC family
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ * Jeremy Kerr <jk@ozlabs.org>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/char/serial.h"
+
+
+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+{
+    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+}
+
+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    SerialMM *smm;
+
+    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+        smm = &s->uart[i];
+
+        /* Chardev property is set by the machine. */
+        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
+        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
+        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
+        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
+        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
+            return false;
+        }
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+    }
+
+    return true;
+}
+
+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    int i = dev - ASPEED_DEV_UART1;
+
+    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
+    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+}
+
+/*
+ * SDMC should be realized first to get correct RAM size and max size
+ * values
+ */
+bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    ram_addr_t ram_size, max_ram_size;
+
+    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+                                        &error_abort);
+    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
+                                            &error_abort);
+
+    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
+                       max_ram_size);
+    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
+
+    /*
+     * Add a memory region beyond the RAM region to let firmwares scan
+     * the address space with load/store and guess how much RAM the
+     * SoC has.
+     */
+    if (ram_size < max_ram_size) {
+        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
+
+        qdev_prop_set_string(dev, "name", "ram-empty");
+        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
+        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
+            return false;
+        }
+
+        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
+                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
+    }
+
+    memory_region_add_subregion(s->memory,
+                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
+    return true;
+}
+
+void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
+{
+    memory_region_add_subregion(s->memory, addr,
+                                sysbus_mmio_get_region(dev, n));
+}
+
+void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+                                   const char *name, hwaddr addr, uint64_t size)
+{
+    qdev_prop_set_string(DEVICE(dev), "name", name);
+    qdev_prop_set_uint64(DEVICE(dev), "size", size);
+    sysbus_realize(dev, &error_abort);
+
+    memory_region_add_subregion_overlap(s->memory, addr,
+                                        sysbus_mmio_get_region(dev, 0), -1000);
+}
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
 arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_soc.c',
   'aspeed.c',
+  'aspeed_soc_common.c',
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
   'aspeed_eeprom.c',
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
 }
 
-static void aspeed_soc_init(Object *obj)
+static void aspeed_ast2400_soc_init(Object *obj)
 {
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2400_type_info = {
     .name           = "ast2400-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2400_class_init,
 };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2500_type_info = {
     .name           = "ast2500-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2500_class_init,
 };
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Keep aspeed_soc_class_init() generic, set the realize handler
to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
 }
 
-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
 {
     int i;
     AspeedSoCState *s = ASPEED_SOC(dev);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    dc->realize = aspeed_soc_realize;
-    /* Reason: Uses serial_hds and nd_table in realize() directly */
-    dc->user_creatable = false;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2400-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2500-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

We want to derivate the big AspeedSoCState object in some more
SoC-specific ones. Since the object size will vary, allocate it
dynamically.

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
     MachineState parent_obj;
     /* Public */
 
-    AspeedSoCState soc;
+    AspeedSoCState *soc;
     MemoryRegion boot_rom;
     bool mmio_exec;
     uint32_t uart_chosen;
@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
                                     uint64_t rom_size)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
                            &error_abort);
@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 {
     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
-    AspeedSoCState *s = &bmc->soc;
+    AspeedSoCState *s = bmc->soc;
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
     int i;
     NICInfo *nd = &nd_table[0];
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-
-    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
 
     /*
      * This will error out if the RAM size is not supported by the
      * memory controller of the SoC.
      */
-    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
+    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
                              &error_fatal);
 
     for (i = 0; i < sc->macs_num; i++) {
         if ((amc->macs_mask & (1 << i)) && nd->used) {
             qemu_check_nic_model(nd, TYPE_FTGMAC100);
-            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
+            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
             nd++;
         }
     }
 
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
                             &error_abort);
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
                             &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "dram",
+    object_property_set_link(OBJECT(bmc->soc), "dram",
                              OBJECT(machine->ram), &error_abort);
     if (machine->kernel_filename) {
         /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          * that runs to unlock the SCU. In this case set the default to
          * be unlocked as the kernel expects
          */
-        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
+        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
                                 ASPEED_SCU_PROT_KEY, &error_abort);
     }
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
     if (defaults_enabled()) {
-        aspeed_board_init_flashes(&bmc->soc.fmc,
+        aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs, 0);
-        aspeed_board_init_flashes(&bmc->soc.spi[0],
+        aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               1, amc->num_cs);
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
         amc->i2c_init(bmc);
     }
 
-    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
-        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
+    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
                            drive_get(IF_SD, 0, i));
     }
 
-    if (bmc->soc.emmc.num_slots) {
-        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
-                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
+    if (bmc->soc->emmc.num_slots) {
+        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
+                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
     }
 
     if (!bmc->mmio_exec) {
-        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
+        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
         BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
 
         if (fmc0) {
-            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
             aspeed_install_boot_rom(bmc, fmc0, rom_size);
         }
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
 
 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /*
      * The quanta-q71l platform expects tmp75s which are compatible with
@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 
 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 
 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
      * good enough */
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 
 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* bus 2 : */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
     };
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
     DeviceState *dev;
     LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
 
     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 
 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[144] = {};
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[13] = {};
     for (int i = 0; i < 13; i++) {
         if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fby35_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[16];
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
 
 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 }
 
 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *therm_mux, *cpuvr_mux;
 
     /* Create the generic DC-SCM hardware */
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
 static void fby35_reset(MachineState *state, ShutdownCause reason)
 {
     AspeedMachineState *bmc = ASPEED_MACHINE(state);
-    AspeedGPIOState *gpio = &bmc->soc.gpio;
+    AspeedGPIOState *gpio = &bmc->soc->gpio;
 
     qemu_devices_reset(reason);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
     clock_set_hz(sysclk, SYSCLK_FRQ);
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
 
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&bmc->soc.fmc,
+    aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs,
                               0);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[0],
+    aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, amc->num_cs);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[1],
+    aspeed_board_init_flashes(&bmc->soc->spi[1],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, (amc->num_cs * 2));
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
 
 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* U10 24C08 connects to SDA/SCL Group 1 by default */
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed10x0SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
+
 struct AspeedSoCClass {
     DeviceClass parent_class;
 
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
     sc->get_irq = aspeed_soc_ast1030_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast1030_type_info = {
-    .name          = "ast1030-a1",
-    .parent        = TYPE_ASPEED_SOC,
-    .instance_size = sizeof(AspeedSoCState),
-    .instance_init = aspeed_soc_ast1030_init,
-    .class_init    = aspeed_soc_ast1030_class_init,
-    .class_size    = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast10x0_types[] = {
+    {
+        .name           = TYPE_ASPEED10X0_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed10x0SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast1030-a1",
+        .parent         = TYPE_ASPEED10X0_SOC,
+        .instance_init  = aspeed_soc_ast1030_init,
+        .class_init     = aspeed_soc_ast1030_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast1030_type_info);
-}
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast10x0_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2600SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2600_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2600_type_info = {
-    .name           = "ast2600-a3",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_size  = sizeof(AspeedSoCState),
-    .instance_init  = aspeed_soc_ast2600_init,
-    .class_init     = aspeed_soc_ast2600_class_init,
-    .class_size     = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast2600_types[] = {
+    {
+        .name           = TYPE_ASPEED2600_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed2600SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2600-a3",
+        .parent         = TYPE_ASPEED2600_SOC,
+        .instance_init  = aspeed_soc_ast2600_init,
+        .class_init     = aspeed_soc_ast2600_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast2600_type_info);
-};
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast2600_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

TYPE_ASPEED_SOC is common to various Aspeed SoCs,
define it in aspeed_soc_common.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++
 hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
 hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
 3 files changed, 53 insertions(+), 44 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2400SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
+
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
 }
-static Property aspeed_soc_properties[] = {
-    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(oc);
-
-    device_class_set_props(dc, aspeed_soc_properties);
-}
-
-static const TypeInfo aspeed_soc_type_info = {
-    .name           = TYPE_ASPEED_SOC,
-    .parent         = TYPE_DEVICE,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_size     = sizeof(AspeedSoCClass),
-    .class_init     = aspeed_soc_class_init,
-    .abstract       = true,
-};
 
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2400_type_info = {
-    .name           = "ast2400-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2400_class_init,
-};
-
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2500_type_info = {
-    .name           = "ast2500-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2500_class_init,
-};
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_type_info);
-    type_register_static(&aspeed_soc_ast2400_type_info);
-    type_register_static(&aspeed_soc_ast2500_type_info);
+static const TypeInfo aspeed_soc_ast2400_types[] = {
+    {
+        .name           = TYPE_ASPEED2400_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_init  = aspeed_ast2400_soc_init,
+        .instance_size  = sizeof(Aspeed2400SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2400-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2400_class_init,
+    }, {
+        .name           = "ast2500-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2500_class_init,
+    },
 };
 
-type_init(aspeed_soc_register_types);
+DEFINE_TYPES(aspeed_soc_ast2400_types)
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "hw/qdev-properties.h"
 #include "hw/misc/unimp.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/char/serial.h"
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
     memory_region_add_subregion_overlap(s->memory, addr,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
+
+static Property aspeed_soc_properties[] = {
+    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    device_class_set_props(dc, aspeed_soc_properties);
+}
+
+static const TypeInfo aspeed_soc_types[] = {
+    {
+        .name           = TYPE_ASPEED_SOC,
+        .parent         = TYPE_DEVICE,
+        .instance_size  = sizeof(AspeedSoCState),
+        .class_size     = sizeof(AspeedSoCClass),
+        .class_init     = aspeed_soc_class_init,
+        .abstract       = true,
+    },
+};
+
+DEFINE_TYPES(aspeed_soc_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
 
+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+{
+    AspeedSoCState *s = ASPEED_SOC(dev);
+
+    if (!s->memory) {
+        error_setg(errp, "'memory' link is not set");
+        return;
+    }
+}
+
 static Property aspeed_soc_properties[] = {
     DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
                      MemoryRegion *),
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
+    dc->realize = aspeed_soc_realize;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-M core is specific to the Aspeed 10x0 series,
remove it from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  5 ++---
 hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
 hw/arm/fby35.c              | 13 ++++++++-----
 3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #define ASPEED_JTAG_NUM  2
 
 struct AspeedSoCState {
-    /*< private >*/
     DeviceState parent;
 
-    /*< public >*/
     ARMCPU cpu[ASPEED_CPUS_NUM];
     A15MPPrivState     a7mpcore;
-    ARMv7MState        armv7m;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
+
+    ARMv7MState armv7m;
 };
 
 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast1030_init(Object *obj)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
         g_assert_not_reached();
     }
 
-    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
 
     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
 
 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
     AspeedSoCState *s = ASPEED_SOC(dev_soc);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
                                   0x40000);
 
     /* AST1030 CPU Core */
-    armv7m = DEVICE(&s->armv7m);
+    armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
     qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
-    object_property_set_link(OBJECT(&s->armv7m), "memory",
+    object_property_set_link(OBJECT(&a->armv7m), "memory",
                              OBJECT(s->memory), &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
 
     /* Internal SRAM */
     sram_name = g_strdup_printf("aspeed.sram.%d",
-                                CPU(s->armv7m.cpu)->cpu_index);
+                                CPU(a->armv7m.cpu)->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err != NULL) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST1030 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST1030 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* UART */
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     Clock *bic_sysclk;
 
     AspeedSoCState bmc;
-    AspeedSoCState bic;
+    Aspeed10x0SoCState bic;
 
     bool mmio_exec;
 };
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
 
 static void fby35_bic_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
     clock_set_hz(s->bic_sysclk, 200000000ULL);
 
     object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
+    soc = ASPEED_SOC(&s->bic);
 
     memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
     qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
     object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                              &error_abort);
-    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
     qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
-    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
-    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
+    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
+    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
+    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
 }
 
 static void fby35_init(MachineState *machine)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-A cluster is specific to the Aspeed 2600 series,
remove it from the common AspeedSoCState.

The ARM cores belong to the MP cluster, but the array
is currently used by TYPE_ASPEED2600_SOC. We'll clean
that soon, but for now keep it in Aspeed2600SoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  4 ++-
 hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
 hw/arm/fby35.c              | 14 ++++++-----
 3 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     DeviceState parent;
 
     ARMCPU cpu[ASPEED_CPUS_NUM];
-    A15MPPrivState     a7mpcore;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
+
+    A15MPPrivState a7mpcore;
+    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
 };
 
 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast2600_init(Object *obj)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     }
 
     for (i = 0; i < sc->num_cpus; i++) {
-        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
     }
 
     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                               "hw-prot-key");
 
-    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                             TYPE_A15MPCORE_PRIV);
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 {
     int i;
+    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
     AspeedSoCState *s = ASPEED_SOC(dev);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     /* CPU */
     for (i = 0; i < sc->num_cpus; i++) {
         if (sc->num_cpus > 1) {
-            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                     ASPEED_A7MPCORE_ADDR, &error_abort);
         }
-        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                 aspeed_calc_affinity(i), &error_abort);
 
-        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                 &error_abort);
-        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                  OBJECT(s->memory), &error_abort);
 
-        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
             return;
         }
     }
 
     /* A7MPCORE */
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
                             ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
                             &error_abort);
 
-    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
 
     for (i = 0; i < sc->num_cpus; i++) {
-        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
-        DeviceState  *d   = DEVICE(&s->cpu[i]);
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
+        DeviceState  *d   = DEVICE(&a->cpu[i]);
 
         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
         sysbus_connect_irq(sbd, i, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
 
     /* SRAM */
-    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST2600 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      * offset 0.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* HACE */
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST2600 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     MemoryRegion bic_memory;
     Clock *bic_sysclk;
 
-    AspeedSoCState bmc;
+    Aspeed2600SoCState bmc;
     Aspeed10x0SoCState bic;
 
     bool mmio_exec;
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
 
 static void fby35_bmc_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
+    soc = ASPEED_SOC(&s->bmc);
 
     memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
                             &error_abort);
     object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
                             &error_abort);
-    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
     qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
+    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
 
     /* Install first FMC flash content as a boot rom. */
     if (!s->mmio_exec) {
         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
 
         if (mtd0) {
-            AspeedSoCState *bmc = &s->bmc;
-            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
+            uint64_t rom_size = memory_region_size(&soc->spi_boot);
 
             memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
                                    rom_size, &error_abort);
-            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
+            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
                                                 &s->bmc_boot_rom, 1);
 
             fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The ARM array and VIC peripheral are only used by the
2400 series, remove them from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h               |  5 +++--
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
 hw/arm/meson.build                        |  2 +-
 3 files changed, 19 insertions(+), 15 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)

The following changes since commit bd2e12310b18b51aefbf834e6d54989fd175976f:

Merge tag 'qga-pull-2024-01-30' of https://github.com/kostyanf14/qemu into staging (2024-01-30 15:53:46 +0000)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20240201

for you to fetch changes up to 649b8ed20543f1b7f7e3dd8fd409092639bb345e:

hw/fsi: Update MAINTAINER list (2024-02-01 08:33:18 +0100)

----------------------------------------------------------------
aspeed queue:

* Update of buildroot images to 2023.11 (6.6.3 kernel)
* Check of the valid CPU type supported by aspeed machines
* Simplified models for the IBM's FSI bus and the Aspeed
  controller bridge

Changes since v1:

- Endianness fix
- Renamed test file to match other filenames
- Fixed file list in MAINTAINER
 
----------------------------------------------------------------
Cédric Le Goater (1):
      tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11

Ninad Palsule (11):
      hw/fsi: Introduce IBM's Local bus
      hw/fsi: Introduce IBM's scratchpad device
      hw/fsi: Introduce IBM's FSI Bus
      hw/fsi: Introduce IBM's fsi-slave model
      hw/fsi: Introduce IBM's cfam
      hw/fsi: Introduce IBM's FSI master
      hw/fsi: Aspeed APB2OPB & On-chip peripheral bus
      hw/arm: Hook up FSI module in AST2600
      hw/fsi: Added qtest
      hw/fsi: Added FSI documentation
      hw/fsi: Update MAINTAINER list

Philippe Mathieu-Daudé (5):
      hw/arm/aspeed: Remove dead code
      hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
      hw/arm/aspeed: Init CPU defaults in a common helper
      hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
      hw/arm/aspeed: Check for CPU types in machine_run_board_init()

MAINTAINERS                     |   9 +
 docs/specs/fsi.rst              | 122 +++++++++++++
 docs/specs/index.rst            |   1 +
 meson.build                     |   1 +
 hw/fsi/trace.h                  |   1 +
 include/hw/arm/aspeed_soc.h     |   8 +-
 include/hw/fsi/aspeed_apb2opb.h |  46 +++++
 include/hw/fsi/cfam.h           |  34 ++++
 include/hw/fsi/fsi-master.h     |  32 ++++
 include/hw/fsi/fsi.h            |  37 ++++
 include/hw/fsi/lbus.h           |  43 +++++
 hw/arm/aspeed.c                 |  70 ++++----
 hw/arm/aspeed_ast10x0.c         |   8 +-
 hw/arm/aspeed_ast2400.c         |  15 +-
 hw/arm/aspeed_ast2600.c         |  28 ++-
 hw/arm/aspeed_soc_common.c      |   8 +
 hw/fsi/aspeed_apb2opb.c         | 367 ++++++++++++++++++++++++++++++++++++++++
 hw/fsi/cfam.c                   | 168 ++++++++++++++++++
 hw/fsi/fsi-master.c             | 170 +++++++++++++++++++
 hw/fsi/fsi.c                    | 102 +++++++++++
 hw/fsi/lbus.c                   | 117 +++++++++++++
 tests/qtest/aspeed_fsi-test.c   | 205 ++++++++++++++++++++++
 hw/Kconfig                      |   1 +
 hw/arm/Kconfig                  |   1 +
 hw/fsi/Kconfig                  |   7 +
 hw/fsi/meson.build              |   2 +
 hw/fsi/trace-events             |  13 ++
 hw/meson.build                  |   1 +
 tests/avocado/machine_aspeed.py |  18 +-
 tests/qtest/meson.build         |   1 +
 30 files changed, 1578 insertions(+), 58 deletions(-)
 create mode 100644 docs/specs/fsi.rst
 create mode 100644 hw/fsi/trace.h
 create mode 100644 include/hw/fsi/aspeed_apb2opb.h
 create mode 100644 include/hw/fsi/cfam.h
 create mode 100644 include/hw/fsi/fsi-master.h
 create mode 100644 include/hw/fsi/fsi.h
 create mode 100644 include/hw/fsi/lbus.h
 create mode 100644 hw/fsi/aspeed_apb2opb.c
 create mode 100644 hw/fsi/cfam.c
 create mode 100644 hw/fsi/fsi-master.c
 create mode 100644 hw/fsi/fsi.c
 create mode 100644 hw/fsi/lbus.c
 create mode 100644 tests/qtest/aspeed_fsi-test.c
 create mode 100644 hw/fsi/Kconfig
 create mode 100644 hw/fsi/meson.build
 create mode 100644 hw/fsi/trace-events

Compared to mainline buildroot, these images have some customization :

- Linux version is bumped to 6.6.3 and built with a custom config
- U-Boot is switched to the one provided by OpenBMC for more support
- defconfigs extra tools for dev

See branch [1] for more details.

There are a few changes since last update, commit ed1f5ff84209. Images
all have a password now and I2C devices have been updated in the Linux
ast2600-evb device tree [2]. Do the necessary adjustements.

[1] https://github.com/legoater/buildroot/commits/aspeed-2023.11
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9deb10cf160e

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/avocado/machine_aspeed.py | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'
         time.sleep(0.1)
         exec_command(self, 'root')
         time.sleep(0.1)
+        exec_command(self, "passw0rd")
 
     def do_test_arm_aspeed_buildroot_poweroff(self):
         exec_command_and_wait_for_pattern(self, 'poweroff',
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_buildroot(self):
         """
 
         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-                     'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
-        image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
+                     'images/ast2500-evb/buildroot-2023.11/flash.img')
+        image_hash = ('c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
                                       algorithm='sha256')
 
         self.vm.add_args('-device',
                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
-        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0')
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0', 'Aspeed AST2500 EVB')
 
         exec_command_and_wait_for_pattern(self,
              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
         """
 
         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-                     'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
-        image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
+                     'images/ast2600-evb/buildroot-2023.11/flash.img')
+        image_hash = ('b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
                                       algorithm='sha256')
 
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
                          'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
         self.vm.add_args('-device',
                          'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
-        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
 
         exec_command_and_wait_for_pattern(self,
              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
              'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
         exec_command_and_wait_for_pattern(self,
-                             'cat /sys/class/hwmon/hwmon0/temp1_input', '0')
+                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
         self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
                     property='temperature', value=18000);
         exec_command_and_wait_for_pattern(self,
-                             'cat /sys/class/hwmon/hwmon0/temp1_input', '18000')
+                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
 
         exec_command_and_wait_for_pattern(self,
              'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot_tpm(self):
         self.vm.add_args('-device',
                          'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
         self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
-        exec_command(self, "passw0rd")
 
         exec_command_and_wait_for_pattern(self,
             'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
of CPUs from the SoC definition") Aspeed machines use the
aspeed_soc_num_cpus() helper to set the number of CPUs.

Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e
"hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
     amc->i2c_init  = palmetto_bmc_i2c_init;
     mc->default_ram_size = 256 * MiB;
+    mc->default_cpus = mc->min_cpus = mc->max_cpus =
+        aspeed_soc_num_cpus(amc->soc_name);
 }
 
 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
     mc->init = aspeed_minibmc_machine_init;
     amc->i2c_init = ast1030_evb_i2c_init;
     mc->default_ram_size = 0;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
     amc->fmc_model = "sst25vf032b";
     amc->spi_model = "sst25vf032b";
     amc->num_cs = 2;
     amc->macs_mask = 0;
+    mc->default_cpus = mc->min_cpus = mc->max_cpus =
+        aspeed_soc_num_cpus(amc->soc_name);
 }
 
 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
helper to reduce code duplication.

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
                                           "Change the SPI Flash model");
 }
 
-static int aspeed_soc_num_cpus(const char *soc_name)
+static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
 {
-   AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
-   return sc->num_cpus;
+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
+    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
+
+    mc->default_cpus = sc->num_cpus;
+    mc->min_cpus = sc->num_cpus;
+    mc->max_cpus = sc->num_cpus;
 }
 
 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 1;
     amc->i2c_init  = palmetto_bmc_i2c_init;
     mc->default_ram_size       = 256 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 1;
     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
     mc->default_ram_size       = 128 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 }
 
 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
     amc->i2c_init  = palmetto_bmc_i2c_init;
     mc->default_ram_size = 256 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 }
 
 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
     amc->i2c_init  = palmetto_bmc_i2c_init;
     mc->default_ram_size = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 }
 
 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 1;
     amc->i2c_init  = ast2500_evb_i2c_init;
     mc->default_ram_size       = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 2;
     amc->i2c_init  = yosemitev2_bmc_i2c_init;
     mc->default_ram_size       = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 2;
     amc->i2c_init  = romulus_bmc_i2c_init;
     mc->default_ram_size       = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 2;
     amc->i2c_init  = tiogapass_bmc_i2c_init;
     mc->default_ram_size       = 1 * GiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 2;
     amc->i2c_init  = sonorapass_bmc_i2c_init;
     mc->default_ram_size       = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 2;
     amc->i2c_init  = witherspoon_bmc_i2c_init;
     mc->default_ram_size = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
                      ASPEED_MAC3_ON;
     amc->i2c_init  = ast2600_evb_i2c_init;
     mc->default_ram_size = 1 * GiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
     amc->macs_mask  = ASPEED_MAC2_ON;
     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
     mc->default_ram_size = 1 * GiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
     amc->i2c_init  = g220a_bmc_i2c_init;
     mc->default_ram_size = 1024 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
     amc->i2c_init  = fp5280g2_bmc_i2c_init;
     mc->default_ram_size = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
     amc->i2c_init  = rainier_bmc_i2c_init;
     mc->default_ram_size = 1 * GiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
     amc->i2c_init = fuji_bmc_i2c_init;
     amc->uart_default = ASPEED_DEV_UART1;
     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
     amc->macs_mask = ASPEED_MAC2_ON;
     amc->i2c_init  = bletchley_bmc_i2c_init;
     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 }
 
 static void fby35_reset(MachineState *state, ShutdownCause reason)
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
     amc->i2c_init  = fby35_i2c_init;
     /* FIXME: Replace this macro with something more general */
     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
+    aspeed_machine_class_init_cpus_defaults(mc);
 }
 
 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
     amc->spi_model = "sst25vf032b";
     amc->num_cs = 2;
     amc->macs_mask = 0;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 }
 
 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
     mc->default_ram_size = 1 * GiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
     mc->default_ram_size = 1 * GiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
+    aspeed_machine_class_init_cpus_defaults(mc);
 };
 
 static const TypeInfo aspeed_machine_types[] = {
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

In order to alter AspeedSoCClass::cpu_type in the next
commit, introduce the aspeed_soc_cpu_type() helper to
retrieve the per-SoC CPU type from AspeedSoCClass.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h | 1 +
 hw/arm/aspeed_ast10x0.c     | 2 +-
 hw/arm/aspeed_ast2400.c     | 3 ++-
 hw/arm/aspeed_ast2600.c     | 3 ++-
 hw/arm/aspeed_soc_common.c  | 5 +++++
 5 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass {
     qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
 };
 
+const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
 
 enum {
     ASPEED_DEV_SPI_BOOT,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     /* AST1030 CPU Core */
     armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
-    qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
+    qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
     object_property_set_link(OBJECT(&a->armv7m), "memory",
                              OBJECT(s->memory), &error_abort);
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
     }
 
     for (i = 0; i < sc->num_cpus; i++) {
-        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
+        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
+                                aspeed_soc_cpu_type(sc));
     }
 
     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     }
 
     for (i = 0; i < sc->num_cpus; i++) {
-        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
+        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
+                                aspeed_soc_cpu_type(sc));
     }
 
     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 
 
+const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
+{
+    return sc->cpu_type;
+}
+
 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
 {
     return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
Convert it to a NULL-terminated array (of a single non-NULL element).

Set MachineClass::valid_cpu_types[] to use the common machine code
to provide hints when the requested CPU is invalid (see commit
e702cbc19e ("machine: Improve is_cpu_type_supported()").

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  3 ++-
 hw/arm/aspeed.c             |  1 +
 hw/arm/aspeed_ast10x0.c     |  6 +++++-
 hw/arm/aspeed_ast2400.c     | 12 ++++++++++--
 hw/arm/aspeed_ast2600.c     |  6 +++++-
 hw/arm/aspeed_soc_common.c  |  5 ++++-
 6 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass {
     DeviceClass parent_class;
 
     const char *name;
-    const char *cpu_type;
+    /** valid_cpu_types: NULL terminated array of a single CPU type. */
+    const char * const *valid_cpu_types;
     uint32_t silicon_rev;
     uint64_t sram_size;
     uint64_t secsram_size;
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
     mc->default_cpus = sc->num_cpus;
     mc->min_cpus = sc->num_cpus;
     mc->max_cpus = sc->num_cpus;
+    mc->valid_cpu_types = sc->valid_cpu_types;
 }
 
 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 
 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
 {
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+        NULL
+    };
     DeviceClass *dc = DEVICE_CLASS(klass);
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
 
     dc->realize = aspeed_soc_ast1030_realize;
 
     sc->name = "ast1030-a1";
-    sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
+    sc->valid_cpu_types = valid_cpu_types;
     sc->silicon_rev = AST1030_A1_SILICON_REV;
     sc->sram_size = 0xc0000;
     sc->secsram_size = 0x40000; /* 256 * KiB */
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
 
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("arm926"),
+        NULL
+    };
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
     DeviceClass *dc = DEVICE_CLASS(oc);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
     dc->user_creatable = false;
 
     sc->name         = "ast2400-a1";
-    sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
+    sc->valid_cpu_types = valid_cpu_types;
     sc->silicon_rev  = AST2400_A1_SILICON_REV;
     sc->sram_size    = 0x8000;
     sc->spis_num     = 1;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("arm1176"),
+        NULL
+    };
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
     DeviceClass *dc = DEVICE_CLASS(oc);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
     dc->user_creatable = false;
 
     sc->name         = "ast2500-a1";
-    sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
+    sc->valid_cpu_types = valid_cpu_types;
     sc->silicon_rev  = AST2500_A1_SILICON_REV;
     sc->sram_size    = 0x9000;
     sc->spis_num     = 2;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 
 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
 {
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("cortex-a7"),
+        NULL
+    };
     DeviceClass *dc = DEVICE_CLASS(oc);
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 
     dc->realize      = aspeed_soc_ast2600_realize;
 
     sc->name         = "ast2600-a3";
-    sc->cpu_type     = ARM_CPU_TYPE_NAME("cortex-a7");
+    sc->valid_cpu_types = valid_cpu_types;
     sc->silicon_rev  = AST2600_A3_SILICON_REV;
     sc->sram_size    = 0x16400;
     sc->spis_num     = 2;
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
 
 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
 {
-    return sc->cpu_type;
+    assert(sc->valid_cpu_types);
+    assert(sc->valid_cpu_types[0]);
+    assert(!sc->valid_cpu_types[1]);
+    return sc->valid_cpu_types[0];
 }
 
 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This is a part of patchset where IBM's Flexible Service Interface is
introduced.

The LBUS is modelled to maintain mapped memory for the devices. The
memory is mapped after CFAM config, peek table and FSI slave registers.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - removed lbus_add_device() bc unused
       - removed lbus_create_device() bc used only once
       - removed "address" property
       - updated meson.build to build fsi dir
       - included an empty hw/fsi/trace-events ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 meson.build           |  1 +
 hw/fsi/trace.h        |  1 +
 include/hw/fsi/lbus.h | 32 ++++++++++++++++++++++++++++++++
 hw/fsi/lbus.c         | 43 +++++++++++++++++++++++++++++++++++++++++++
 hw/Kconfig            |  1 +
 hw/fsi/Kconfig        |  2 ++
 hw/fsi/meson.build    |  1 +
 hw/fsi/trace-events   |  0
 hw/meson.build        |  1 +
 9 files changed, 82 insertions(+)
 create mode 100644 hw/fsi/trace.h
 create mode 100644 include/hw/fsi/lbus.h
 create mode 100644 hw/fsi/lbus.c
 create mode 100644 hw/fsi/Kconfig
 create mode 100644 hw/fsi/meson.build
 create mode 100644 hw/fsi/trace-events

diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'hw/char',
     'hw/display',
     'hw/dma',
+    'hw/fsi',
     'hw/hyperv',
     'hw/i2c',
     'hw/i386',
diff --git a/hw/fsi/trace.h b/hw/fsi/trace.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_fsi.h"
diff --git a/include/hw/fsi/lbus.h b/include/hw/fsi/lbus.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/fsi/lbus.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Local bus and connected device structures.
+ */
+#ifndef FSI_LBUS_H
+#define FSI_LBUS_H
+
+#include "hw/qdev-core.h"
+#include "qemu/units.h"
+#include "exec/memory.h"
+
+#define TYPE_FSI_LBUS_DEVICE "fsi.lbus.device"
+OBJECT_DECLARE_SIMPLE_TYPE(FSILBusDevice, FSI_LBUS_DEVICE)
+
+typedef struct FSILBusDevice {
+    DeviceState parent;
+
+    MemoryRegion iomem;
+} FSILBusDevice;
+
+#define TYPE_FSI_LBUS "fsi.lbus"
+OBJECT_DECLARE_SIMPLE_TYPE(FSILBus, FSI_LBUS)
+
+typedef struct FSILBus {
+    BusState bus;
+
+    MemoryRegion mr;
+} FSILBus;
+
+#endif /* FSI_LBUS_H */
diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/lbus.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Local bus where FSI slaves are connected
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/fsi/lbus.h"
+
+#include "hw/qdev-properties.h"
+
+#include "trace.h"
+
+static void fsi_lbus_init(Object *o)
+{
+    FSILBus *lbus = FSI_LBUS(o);
+
+    memory_region_init(&lbus->mr, OBJECT(lbus), TYPE_FSI_LBUS, 1 * MiB);
+}
+
+static const TypeInfo fsi_lbus_info = {
+    .name = TYPE_FSI_LBUS,
+    .parent = TYPE_BUS,
+    .instance_init = fsi_lbus_init,
+    .instance_size = sizeof(FSILBus),
+};
+
+static const TypeInfo fsi_lbus_device_type_info = {
+    .name = TYPE_FSI_LBUS_DEVICE,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(FSILBusDevice),
+    .abstract = true,
+};
+
+static void fsi_lbus_register_types(void)
+{
+    type_register_static(&fsi_lbus_info);
+    type_register_static(&fsi_lbus_device_type_info);
+}
+
+type_init(fsi_lbus_register_types);
diff --git a/hw/Kconfig b/hw/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -XXX,XX +XXX,XX @@ source core/Kconfig
 source cxl/Kconfig
 source display/Kconfig
 source dma/Kconfig
+source fsi/Kconfig
 source gpio/Kconfig
 source hyperv/Kconfig
 source i2c/Kconfig
diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/Kconfig
@@ -XXX,XX +XXX,XX @@
+config FSI
+    bool
diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/meson.build
@@ -0,0 +1 @@
+system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c'))
diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
new file mode 100644
index XXXXXXX..XXXXXXX
diff --git a/hw/meson.build b/hw/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -XXX,XX +XXX,XX @@ subdir('virtio')
 subdir('watchdog')
 subdir('xen')
 subdir('xenpv')
+subdir('fsi')
 
 subdir('alpha')
 subdir('arm')
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This is a part of patchset where IBM's Flexible Service Interface is
introduced.

The scratchpad provides a set of non-functional registers. The firmware
is free to use them, hardware does not support any special management
support. The scratchpad registers can be read or written from LBUS
slave. The scratch pad is managed under FSI CFAM state.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - moved object FSIScratchPad under FSICFAMState
       - moved FSIScratchPad code under cfam.c ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/fsi/lbus.h | 11 ++++++
 hw/fsi/lbus.c         | 78 +++++++++++++++++++++++++++++++++++++++++--
 hw/fsi/trace-events   |  2 ++
 3 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/include/hw/fsi/lbus.h b/include/hw/fsi/lbus.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/fsi/lbus.h
+++ b/include/hw/fsi/lbus.h
@@ -XXX,XX +XXX,XX @@ typedef struct FSILBus {
     MemoryRegion mr;
 } FSILBus;
 
+#define TYPE_FSI_SCRATCHPAD "fsi.scratchpad"
+#define SCRATCHPAD(obj) OBJECT_CHECK(FSIScratchPad, (obj), TYPE_FSI_SCRATCHPAD)
+
+#define FSI_SCRATCHPAD_NR_REGS 4
+
+typedef struct FSIScratchPad {
+        FSILBusDevice parent;
+
+        uint32_t regs[FSI_SCRATCHPAD_NR_REGS];
+} FSIScratchPad;
+
 #endif /* FSI_LBUS_H */
diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/lbus.c
+++ b/hw/fsi/lbus.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/fsi/lbus.h"
-
 #include "hw/qdev-properties.h"
-
+#include "qemu/log.h"
 #include "trace.h"
 
+#define TO_REG(offset) ((offset) >> 2)
+
 static void fsi_lbus_init(Object *o)
 {
     FSILBus *lbus = FSI_LBUS(o);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo fsi_lbus_device_type_info = {
     .abstract = true,
 };
 
+static uint64_t fsi_scratchpad_read(void *opaque, hwaddr addr, unsigned size)
+{
+    FSIScratchPad *s = SCRATCHPAD(opaque);
+    int reg = TO_REG(addr);
+
+    trace_fsi_scratchpad_read(addr, size);
+
+    if (reg >= FSI_SCRATCHPAD_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        return 0;
+    }
+
+    return s->regs[reg];
+}
+
+static void fsi_scratchpad_write(void *opaque, hwaddr addr, uint64_t data,
+                                 unsigned size)
+{
+    FSIScratchPad *s = SCRATCHPAD(opaque);
+
+    trace_fsi_scratchpad_write(addr, size, data);
+    int reg = TO_REG(addr);
+
+    if (reg >= FSI_SCRATCHPAD_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        return;
+    }
+
+    s->regs[reg] = data;
+}
+
+static const struct MemoryRegionOps scratchpad_ops = {
+    .read = fsi_scratchpad_read,
+    .write = fsi_scratchpad_write,
+    .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void fsi_scratchpad_realize(DeviceState *dev, Error **errp)
+{
+    FSILBusDevice *ldev = FSI_LBUS_DEVICE(dev);
+
+    memory_region_init_io(&ldev->iomem, OBJECT(ldev), &scratchpad_ops,
+                          ldev, TYPE_FSI_SCRATCHPAD, 0x400);
+}
+
+static void fsi_scratchpad_reset(DeviceState *dev)
+{
+    FSIScratchPad *s = SCRATCHPAD(dev);
+
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void fsi_scratchpad_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->bus_type = TYPE_FSI_LBUS;
+    dc->realize = fsi_scratchpad_realize;
+    dc->reset = fsi_scratchpad_reset;
+}
+
+static const TypeInfo fsi_scratchpad_info = {
+    .name = TYPE_FSI_SCRATCHPAD,
+    .parent = TYPE_FSI_LBUS_DEVICE,
+    .instance_size = sizeof(FSIScratchPad),
+    .class_init = fsi_scratchpad_class_init,
+};
+
 static void fsi_lbus_register_types(void)
 {
     type_register_static(&fsi_lbus_info);
     type_register_static(&fsi_lbus_device_type_info);
+    type_register_static(&fsi_scratchpad_info);
 }
 
 type_init(fsi_lbus_register_types);
diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/trace-events
+++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@
+fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
+fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This is a part of patchset where FSI bus is introduced.

The FSI bus is a simple bus where FSI master is attached.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - removed include/hw/fsi/engine-scratchpad.h and
       	 hw/fsi/engine-scratchpad.c
       - dropped FSI_SCRATCHPAD
       - included FSIBus definition
       - dropped hw/fsi/trace-events changes ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/fsi/fsi.h | 19 +++++++++++++++++++
 hw/fsi/fsi.c         | 22 ++++++++++++++++++++++
 hw/fsi/meson.build   |  2 +-
 3 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/fsi/fsi.h
 create mode 100644 hw/fsi/fsi.c

diff --git a/include/hw/fsi/fsi.h b/include/hw/fsi/fsi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/fsi/fsi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Flexible Service Interface
+ */
+#ifndef FSI_FSI_H
+#define FSI_FSI_H
+
+#include "hw/qdev-core.h"
+
+#define TYPE_FSI_BUS "fsi.bus"
+OBJECT_DECLARE_SIMPLE_TYPE(FSIBus, FSI_BUS)
+
+typedef struct FSIBus {
+    BusState bus;
+} FSIBus;
+
+#endif /* FSI_FSI_H */
diff --git a/hw/fsi/fsi.c b/hw/fsi/fsi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/fsi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Flexible Service Interface
+ */
+#include "qemu/osdep.h"
+
+#include "hw/fsi/fsi.h"
+
+static const TypeInfo fsi_bus_info = {
+    .name = TYPE_FSI_BUS,
+    .parent = TYPE_BUS,
+    .instance_size = sizeof(FSIBus),
+};
+
+static void fsi_bus_register_types(void)
+{
+    type_register_static(&fsi_bus_info);
+}
+
+type_init(fsi_bus_register_types);
diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/meson.build
+++ b/hw/fsi/meson.build
@@ -1 +1 @@
-system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c'))
+system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c'))
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This is a part of patchset where IBM's Flexible Service Interface is
introduced.

The FSI slave: The slave is the terminal point of the FSI bus for
FSI symbols addressed to it. Slaves can be cascaded off of one
another. The slave's configuration registers appear in address space
of the CFAM to which it is attached.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/fsi/fsi.h | 18 ++++++++++
 hw/fsi/fsi.c         | 84 ++++++++++++++++++++++++++++++++++++++++++--
 hw/fsi/trace-events  |  2 ++
 3 files changed, 102 insertions(+), 2 deletions(-)

diff --git a/include/hw/fsi/fsi.h b/include/hw/fsi/fsi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/fsi/fsi.h
+++ b/include/hw/fsi/fsi.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSI_FSI_H
 #define FSI_FSI_H
 
+#include "exec/memory.h"
 #include "hw/qdev-core.h"
+#include "hw/fsi/lbus.h"
+#include "qemu/bitops.h"
+
+/* Bitwise operations at the word level. */
+#define BE_GENMASK(hb, lb)  MAKE_64BIT_MASK((lb), ((hb) - (lb) + 1))
 
 #define TYPE_FSI_BUS "fsi.bus"
 OBJECT_DECLARE_SIMPLE_TYPE(FSIBus, FSI_BUS)
@@ -XXX,XX +XXX,XX @@ typedef struct FSIBus {
     BusState bus;
 } FSIBus;
 
+#define TYPE_FSI_SLAVE "fsi.slave"
+OBJECT_DECLARE_SIMPLE_TYPE(FSISlaveState, FSI_SLAVE)
+
+#define FSI_SLAVE_CONTROL_NR_REGS ((0x40 >> 2) + 1)
+
+typedef struct FSISlaveState {
+    DeviceState parent;
+
+    MemoryRegion iomem;
+    uint32_t regs[FSI_SLAVE_CONTROL_NR_REGS];
+} FSISlaveState;
+
 #endif /* FSI_FSI_H */
diff --git a/hw/fsi/fsi.c b/hw/fsi/fsi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/fsi.c
+++ b/hw/fsi/fsi.c
@@ -XXX,XX +XXX,XX @@
  * IBM Flexible Service Interface
  */
 #include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "trace.h"
 
 #include "hw/fsi/fsi.h"
 
+#define TO_REG(x)                               ((x) >> 2)
+
 static const TypeInfo fsi_bus_info = {
     .name = TYPE_FSI_BUS,
     .parent = TYPE_BUS,
     .instance_size = sizeof(FSIBus),
 };
 
-static void fsi_bus_register_types(void)
+static uint64_t fsi_slave_read(void *opaque, hwaddr addr, unsigned size)
+{
+    FSISlaveState *s = FSI_SLAVE(opaque);
+    int reg = TO_REG(addr);
+
+    trace_fsi_slave_read(addr, size);
+
+    if (reg >= FSI_SLAVE_CONTROL_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
+                      __func__, addr, size);
+        return 0;
+    }
+
+    return s->regs[reg];
+}
+
+static void fsi_slave_write(void *opaque, hwaddr addr, uint64_t data,
+                                 unsigned size)
+{
+    FSISlaveState *s = FSI_SLAVE(opaque);
+    int reg = TO_REG(addr);
+
+    trace_fsi_slave_write(addr, size, data);
+
+    if (reg >= FSI_SLAVE_CONTROL_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out of bounds write: 0x%"HWADDR_PRIx" for %u\n",
+                      __func__, addr, size);
+        return;
+    }
+
+    s->regs[reg] = data;
+}
+
+static const struct MemoryRegionOps fsi_slave_ops = {
+    .read = fsi_slave_read,
+    .write = fsi_slave_write,
+    .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void fsi_slave_reset(DeviceState *dev)
+{
+    FSISlaveState *s = FSI_SLAVE(dev);
+
+    /* Initialize registers */
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void fsi_slave_init(Object *o)
+{
+    FSISlaveState *s = FSI_SLAVE(o);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &fsi_slave_ops,
+                          s, TYPE_FSI_SLAVE, 0x400);
+}
+
+static void fsi_slave_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->bus_type = TYPE_FSI_BUS;
+    dc->desc = "FSI Slave";
+    dc->reset = fsi_slave_reset;
+}
+
+static const TypeInfo fsi_slave_info = {
+    .name = TYPE_FSI_SLAVE,
+    .parent = TYPE_DEVICE,
+    .instance_init = fsi_slave_init,
+    .instance_size = sizeof(FSISlaveState),
+    .class_init = fsi_slave_class_init,
+};
+
+static void fsi_register_types(void)
 {
     type_register_static(&fsi_bus_info);
+    type_register_static(&fsi_slave_info);
 }
 
-type_init(fsi_bus_register_types);
+type_init(fsi_register_types);
diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/trace-events
+++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@
 fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
+fsi_slave_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
+fsi_slave_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This is a part of patchset where IBM's Flexible Service Interface is
introduced.

The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang off of an internal Local Bus (LBUS) which is described
by the CFAM configuration block.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - moved object FSIScratchPad under FSICFAMState
       - moved FSIScratchPad code under cfam.c
       - introduced fsi_cfam_instance_init()
       - reworked fsi_cfam_realize() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/fsi/cfam.h |  34 +++++++++
 hw/fsi/cfam.c         | 168 ++++++++++++++++++++++++++++++++++++++++++
 hw/fsi/meson.build    |   2 +-
 hw/fsi/trace-events   |   5 ++
 4 files changed, 208 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/fsi/cfam.h
 create mode 100644 hw/fsi/cfam.c

diff --git a/include/hw/fsi/cfam.h b/include/hw/fsi/cfam.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/fsi/cfam.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Common FRU Access Macro
+ */
+#ifndef FSI_CFAM_H
+#define FSI_CFAM_H
+
+#include "exec/memory.h"
+
+#include "hw/fsi/fsi.h"
+#include "hw/fsi/lbus.h"
+
+#define TYPE_FSI_CFAM "cfam"
+#define FSI_CFAM(obj) OBJECT_CHECK(FSICFAMState, (obj), TYPE_FSI_CFAM)
+
+/* P9-ism */
+#define CFAM_CONFIG_NR_REGS 0x28
+
+typedef struct FSICFAMState {
+    /* < private > */
+    FSISlaveState parent;
+
+    /* CFAM config address space */
+    MemoryRegion config_iomem;
+
+    MemoryRegion mr;
+
+    FSILBus lbus;
+    FSIScratchPad scratchpad;
+} FSICFAMState;
+
+#endif /* FSI_CFAM_H */
diff --git a/hw/fsi/cfam.c b/hw/fsi/cfam.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/cfam.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Common FRU Access Macro
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+
+#include "qapi/error.h"
+#include "trace.h"
+
+#include "hw/fsi/cfam.h"
+#include "hw/fsi/fsi.h"
+
+#include "hw/qdev-properties.h"
+
+#define ENGINE_CONFIG_NEXT            BIT(31)
+#define ENGINE_CONFIG_TYPE_PEEK       (0x02 << 4)
+#define ENGINE_CONFIG_TYPE_FSI        (0x03 << 4)
+#define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4)
+
+/* Valid, slots, version, type, crc */
+#define CFAM_CONFIG_REG(__VER, __TYPE, __CRC)   \
+    (ENGINE_CONFIG_NEXT       |   \
+     0x00010000               |   \
+     (__VER)                  |   \
+     (__TYPE)                 |   \
+     (__CRC))
+
+#define TO_REG(x)                          ((x) >> 2)
+
+#define CFAM_CONFIG_CHIP_ID                TO_REG(0x00)
+#define CFAM_CONFIG_PEEK_STATUS            TO_REG(0x04)
+#define CFAM_CONFIG_CHIP_ID_P9             0xc0022d15
+#define CFAM_CONFIG_CHIP_ID_BREAK          0xc0de0000
+
+static uint64_t fsi_cfam_config_read(void *opaque, hwaddr addr, unsigned size)
+{
+    trace_fsi_cfam_config_read(addr, size);
+
+    switch (addr) {
+    case 0x00:
+        return CFAM_CONFIG_CHIP_ID_P9;
+    case 0x04:
+        return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_PEEK, 0xc);
+    case 0x08:
+        return CFAM_CONFIG_REG(0x5000, ENGINE_CONFIG_TYPE_FSI, 0xa);
+    case 0xc:
+        return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_SCRATCHPAD, 0x7);
+    default:
+        /*
+         * The config table contains different engines from 0xc onwards.
+         * The scratch pad is already added at address 0xc. We need to add
+         * future engines from address 0x10 onwards. Returning 0 as engine
+         * is not implemented.
+         */
+        return 0;
+    }
+}
+
+static void fsi_cfam_config_write(void *opaque, hwaddr addr, uint64_t data,
+                                  unsigned size)
+{
+    FSICFAMState *cfam = FSI_CFAM(opaque);
+
+    trace_fsi_cfam_config_write(addr, size, data);
+
+    switch (TO_REG(addr)) {
+    case CFAM_CONFIG_CHIP_ID:
+    case CFAM_CONFIG_PEEK_STATUS:
+        if (data == CFAM_CONFIG_CHIP_ID_BREAK) {
+            bus_cold_reset(BUS(&cfam->lbus));
+        }
+        break;
+    default:
+        trace_fsi_cfam_config_write_noaddr(addr, size, data);
+    }
+}
+
+static const struct MemoryRegionOps cfam_config_ops = {
+    .read = fsi_cfam_config_read,
+    .write = fsi_cfam_config_write,
+    .valid.max_access_size = 4,
+    .valid.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .impl.min_access_size = 4,
+    .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static uint64_t fsi_cfam_unimplemented_read(void *opaque, hwaddr addr,
+                                            unsigned size)
+{
+    trace_fsi_cfam_unimplemented_read(addr, size);
+
+    return 0;
+}
+
+static void fsi_cfam_unimplemented_write(void *opaque, hwaddr addr,
+                                         uint64_t data, unsigned size)
+{
+    trace_fsi_cfam_unimplemented_write(addr, size, data);
+}
+
+static const struct MemoryRegionOps fsi_cfam_unimplemented_ops = {
+    .read = fsi_cfam_unimplemented_read,
+    .write = fsi_cfam_unimplemented_write,
+    .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void fsi_cfam_instance_init(Object *obj)
+{
+    FSICFAMState *s = FSI_CFAM(obj);
+
+    object_initialize_child(obj, "scratchpad", &s->scratchpad,
+                            TYPE_FSI_SCRATCHPAD);
+}
+
+static void fsi_cfam_realize(DeviceState *dev, Error **errp)
+{
+    FSICFAMState *cfam = FSI_CFAM(dev);
+    FSISlaveState *slave = FSI_SLAVE(dev);
+
+    /* Each slave has a 2MiB address space */
+    memory_region_init_io(&cfam->mr, OBJECT(cfam), &fsi_cfam_unimplemented_ops,
+                          cfam, TYPE_FSI_CFAM, 2 * MiB);
+
+    qbus_init(&cfam->lbus, sizeof(cfam->lbus), TYPE_FSI_LBUS, DEVICE(cfam),
+              NULL);
+
+    memory_region_init_io(&cfam->config_iomem, OBJECT(cfam), &cfam_config_ops,
+                          cfam, TYPE_FSI_CFAM ".config", 0x400);
+
+    memory_region_add_subregion(&cfam->mr, 0, &cfam->config_iomem);
+    memory_region_add_subregion(&cfam->mr, 0x800, &slave->iomem);
+    memory_region_add_subregion(&cfam->mr, 0xc00, &cfam->lbus.mr);
+
+    /* Add scratchpad engine */
+    if (!qdev_realize(DEVICE(&cfam->scratchpad), BUS(&cfam->lbus), errp)) {
+        return;
+    }
+
+    FSILBusDevice *fsi_dev = FSI_LBUS_DEVICE(&cfam->scratchpad);
+    memory_region_add_subregion(&cfam->lbus.mr, 0, &fsi_dev->iomem);
+}
+
+static void fsi_cfam_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    dc->bus_type = TYPE_FSI_BUS;
+    dc->realize = fsi_cfam_realize;
+}
+
+static const TypeInfo fsi_cfam_info = {
+    .name = TYPE_FSI_CFAM,
+    .parent = TYPE_FSI_SLAVE,
+    .instance_init = fsi_cfam_instance_init,
+    .instance_size = sizeof(FSICFAMState),
+    .class_init = fsi_cfam_class_init,
+};
+
+static void fsi_cfam_register_types(void)
+{
+    type_register_static(&fsi_cfam_info);
+}
+
+type_init(fsi_cfam_register_types);
diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/meson.build
+++ b/hw/fsi/meson.build
@@ -1 +1 @@
-system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c'))
+system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'))
diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/trace-events
+++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@ fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 fsi_slave_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 fsi_slave_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
+fsi_cfam_config_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
+fsi_cfam_config_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
+fsi_cfam_unimplemented_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
+fsi_cfam_unimplemented_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
+fsi_cfam_config_write_noaddr(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This is a part of patchset where IBM's Flexible Service Interface is
introduced.

This commit models the FSI master. CFAM is hanging out of FSI master which is a bus controller.

The FSI master: A controller in the platform service processor (e.g.
BMC) driving CFAM engine accesses into the POWER chip. At the
hardware level FSI is a bit-based protocol supporting synchronous and
DMA-driven accesses of engines in a CFAM.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - move FSICFAMState object under FSIMasterState
       - introduced fsi_master_init()
       - reworked fsi_master_realize()
       - dropped FSIBus definition ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/fsi/fsi-master.h |  32 +++++++
 hw/fsi/fsi-master.c         | 170 ++++++++++++++++++++++++++++++++++++
 hw/fsi/meson.build          |   2 +-
 hw/fsi/trace-events         |   2 +
 4 files changed, 205 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/fsi/fsi-master.h
 create mode 100644 hw/fsi/fsi-master.c

diff --git a/include/hw/fsi/fsi-master.h b/include/hw/fsi/fsi-master.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/fsi/fsi-master.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Flexible Service Interface Master
+ */
+#ifndef FSI_FSI_MASTER_H
+#define FSI_FSI_MASTER_H
+
+#include "exec/memory.h"
+#include "hw/qdev-core.h"
+#include "hw/fsi/fsi.h"
+#include "hw/fsi/cfam.h"
+
+#define TYPE_FSI_MASTER "fsi.master"
+OBJECT_DECLARE_SIMPLE_TYPE(FSIMasterState, FSI_MASTER)
+
+#define FSI_MASTER_NR_REGS ((0x2e0 >> 2) + 1)
+
+typedef struct FSIMasterState {
+    DeviceState parent;
+    MemoryRegion iomem;
+    MemoryRegion opb2fsi;
+
+    FSIBus bus;
+
+    uint32_t regs[FSI_MASTER_NR_REGS];
+    FSICFAMState cfam;
+} FSIMasterState;
+
+
+#endif /* FSI_FSI_H */
diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/fsi-master.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * IBM Flexible Service Interface master
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "trace.h"
+
+#include "hw/fsi/fsi-master.h"
+
+#define TYPE_OP_BUS "opb"
+
+#define TO_REG(x)                               ((x) >> 2)
+
+#define FSI_MENP0                               TO_REG(0x010)
+#define FSI_MENP32                              TO_REG(0x014)
+#define FSI_MSENP0                              TO_REG(0x018)
+#define FSI_MLEVP0                              TO_REG(0x018)
+#define FSI_MSENP32                             TO_REG(0x01c)
+#define FSI_MLEVP32                             TO_REG(0x01c)
+#define FSI_MCENP0                              TO_REG(0x020)
+#define FSI_MREFP0                              TO_REG(0x020)
+#define FSI_MCENP32                             TO_REG(0x024)
+#define FSI_MREFP32                             TO_REG(0x024)
+
+#define FSI_MVER                                TO_REG(0x074)
+#define FSI_MRESP0                              TO_REG(0x0d0)
+
+#define FSI_MRESB0                              TO_REG(0x1d0)
+#define   FSI_MRESB0_RESET_GENERAL              BIT(31)
+#define   FSI_MRESB0_RESET_ERROR                BIT(30)
+
+static uint64_t fsi_master_read(void *opaque, hwaddr addr, unsigned size)
+{
+    FSIMasterState *s = FSI_MASTER(opaque);
+    int reg = TO_REG(addr);
+
+    trace_fsi_master_read(addr, size);
+
+    if (reg >= FSI_MASTER_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
+                      __func__, addr, size);
+        return 0;
+    }
+
+    return s->regs[reg];
+}
+
+static void fsi_master_write(void *opaque, hwaddr addr, uint64_t data,
+                             unsigned size)
+{
+    FSIMasterState *s = FSI_MASTER(opaque);
+    int reg = TO_REG(addr);
+
+    trace_fsi_master_write(addr, size, data);
+
+    if (reg >= FSI_MASTER_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n",
+                      __func__, addr, size);
+        return;
+    }
+
+    switch (reg) {
+    case FSI_MENP0:
+        s->regs[FSI_MENP0] = data;
+        break;
+    case FSI_MENP32:
+        s->regs[FSI_MENP32] = data;
+        break;
+    case FSI_MSENP0:
+        s->regs[FSI_MENP0] |= data;
+        break;
+    case FSI_MSENP32:
+        s->regs[FSI_MENP32] |= data;
+        break;
+    case FSI_MCENP0:
+        s->regs[FSI_MENP0] &= ~data;
+        break;
+    case FSI_MCENP32:
+        s->regs[FSI_MENP32] &= ~data;
+        break;
+    case FSI_MRESP0:
+        /* Perform necessary resets leave register 0 to indicate no errors */
+        break;
+    case FSI_MRESB0:
+        if (data & FSI_MRESB0_RESET_GENERAL) {
+            device_cold_reset(DEVICE(opaque));
+        }
+        if (data & FSI_MRESB0_RESET_ERROR) {
+            /* FIXME: this seems dubious */
+            device_cold_reset(DEVICE(opaque));
+        }
+        break;
+    default:
+        s->regs[reg] = data;
+    }
+}
+
+static const struct MemoryRegionOps fsi_master_ops = {
+    .read = fsi_master_read,
+    .write = fsi_master_write,
+    .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void fsi_master_init(Object *o)
+{
+    FSIMasterState *s = FSI_MASTER(o);
+
+    object_initialize_child(o, "cfam", &s->cfam, TYPE_FSI_CFAM);
+
+    qbus_init(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &fsi_master_ops, s,
+                          TYPE_FSI_MASTER, 0x10000000);
+    memory_region_init(&s->opb2fsi, OBJECT(s), "fsi.opb2fsi", 0x10000000);
+}
+
+static void fsi_master_realize(DeviceState *dev, Error **errp)
+{
+    FSIMasterState *s = FSI_MASTER(dev);
+
+    if (!qdev_realize(DEVICE(&s->cfam), BUS(&s->bus), errp)) {
+        return;
+    }
+
+    /* address ? */
+    memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.mr);
+}
+
+static void fsi_master_reset(DeviceState *dev)
+{
+    FSIMasterState *s = FSI_MASTER(dev);
+
+    /* Initialize registers */
+    memset(s->regs, 0, sizeof(s->regs));
+
+    /* ASPEED default */
+    s->regs[FSI_MVER] = 0xe0050101;
+}
+
+static void fsi_master_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->bus_type = TYPE_OP_BUS;
+    dc->desc = "FSI Master";
+    dc->realize = fsi_master_realize;
+    dc->reset = fsi_master_reset;
+}
+
+static const TypeInfo fsi_master_info = {
+    .name = TYPE_FSI_MASTER,
+    .parent = TYPE_DEVICE,
+    .instance_init = fsi_master_init,
+    .instance_size = sizeof(FSIMasterState),
+    .class_init = fsi_master_class_init,
+};
+
+static void fsi_register_types(void)
+{
+    type_register_static(&fsi_master_info);
+}
+
+type_init(fsi_register_types);
diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/meson.build
+++ b/hw/fsi/meson.build
@@ -1 +1 @@
-system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'))
+system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c','fsi-master.c'))
diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/trace-events
+++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@ fsi_cfam_config_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64
 fsi_cfam_unimplemented_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 fsi_cfam_unimplemented_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 fsi_cfam_config_write_noaddr(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
+fsi_master_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
+fsi_master_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This is a part of patchset where IBM's Flexible Service Interface is
introduced.

An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.

The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence of an MMIO-mapping of the CFAM address straight onto a
sub-region of the OPB address space.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - moved FSIMasterState under AspeedAPB2OPBState
       - modified fsi_opb_fsi_master_address() and
         fsi_opb_opb2fsi_address()
       - instroduced fsi_aspeed_apb2opb_init()
       - reworked fsi_aspeed_apb2opb_realize()
       - removed FSIMasterState object and fsi_opb_realize()
       - simplified OPBus
       - introduced fsi_aspeed_apb2opb_rw to fix endianness issue ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/fsi/aspeed_apb2opb.h |  46 ++++
 hw/fsi/aspeed_apb2opb.c         | 367 ++++++++++++++++++++++++++++++++
 hw/arm/Kconfig                  |   1 +
 hw/fsi/Kconfig                  |   5 +
 hw/fsi/meson.build              |   1 +
 hw/fsi/trace-events             |   2 +
 6 files changed, 422 insertions(+)
 create mode 100644 include/hw/fsi/aspeed_apb2opb.h
 create mode 100644 hw/fsi/aspeed_apb2opb.c

diff --git a/include/hw/fsi/aspeed_apb2opb.h b/include/hw/fsi/aspeed_apb2opb.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/fsi/aspeed_apb2opb.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * ASPEED APB2OPB Bridge
+ * IBM On-Chip Peripheral Bus
+ */
+#ifndef FSI_ASPEED_APB2OPB_H
+#define FSI_ASPEED_APB2OPB_H
+
+#include "exec/memory.h"
+#include "hw/fsi/fsi-master.h"
+#include "hw/sysbus.h"
+
+#define TYPE_FSI_OPB "fsi.opb"
+
+#define TYPE_OP_BUS "opb"
+OBJECT_DECLARE_SIMPLE_TYPE(OPBus, OP_BUS)
+
+typedef struct OPBus {
+    BusState bus;
+
+    MemoryRegion mr;
+    AddressSpace as;
+} OPBus;
+
+#define TYPE_ASPEED_APB2OPB "aspeed.apb2opb"
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedAPB2OPBState, ASPEED_APB2OPB)
+
+#define ASPEED_APB2OPB_NR_REGS ((0xe8 >> 2) + 1)
+
+#define ASPEED_FSI_NUM 2
+
+typedef struct AspeedAPB2OPBState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+
+    uint32_t regs[ASPEED_APB2OPB_NR_REGS];
+    qemu_irq irq;
+
+    OPBus opb[ASPEED_FSI_NUM];
+    FSIMasterState fsi[ASPEED_FSI_NUM];
+} AspeedAPB2OPBState;
+
+#endif /* FSI_ASPEED_APB2OPB_H */
diff --git a/hw/fsi/aspeed_apb2opb.c b/hw/fsi/aspeed_apb2opb.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/fsi/aspeed_apb2opb.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 IBM Corp.
+ *
+ * ASPEED APB-OPB FSI interface
+ * IBM On-chip Peripheral Bus
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "qapi/error.h"
+#include "trace.h"
+
+#include "hw/fsi/aspeed_apb2opb.h"
+#include "hw/qdev-core.h"
+
+#define TO_REG(x) (x >> 2)
+
+#define APB2OPB_VERSION                    TO_REG(0x00)
+#define APB2OPB_TRIGGER                    TO_REG(0x04)
+
+#define APB2OPB_CONTROL                    TO_REG(0x08)
+#define   APB2OPB_CONTROL_OFF              BE_GENMASK(31, 13)
+
+#define APB2OPB_OPB2FSI                    TO_REG(0x0c)
+#define   APB2OPB_OPB2FSI_OFF              BE_GENMASK(31, 22)
+
+#define APB2OPB_OPB0_SEL                   TO_REG(0x10)
+#define APB2OPB_OPB1_SEL                   TO_REG(0x28)
+#define   APB2OPB_OPB_SEL_EN               BIT(0)
+
+#define APB2OPB_OPB0_MODE                  TO_REG(0x14)
+#define APB2OPB_OPB1_MODE                  TO_REG(0x2c)
+#define   APB2OPB_OPB_MODE_RD              BIT(0)
+
+#define APB2OPB_OPB0_XFER                  TO_REG(0x18)
+#define APB2OPB_OPB1_XFER                  TO_REG(0x30)
+#define   APB2OPB_OPB_XFER_FULL            BIT(1)
+#define   APB2OPB_OPB_XFER_HALF            BIT(0)
+
+#define APB2OPB_OPB0_ADDR                  TO_REG(0x1c)
+#define APB2OPB_OPB0_WRITE_DATA            TO_REG(0x20)
+
+#define APB2OPB_OPB1_ADDR                  TO_REG(0x34)
+#define APB2OPB_OPB1_WRITE_DATA                  TO_REG(0x38)
+
+#define APB2OPB_IRQ_STS                    TO_REG(0x48)
+#define   APB2OPB_IRQ_STS_OPB1_TX_ACK      BIT(17)
+#define   APB2OPB_IRQ_STS_OPB0_TX_ACK      BIT(16)
+
+#define APB2OPB_OPB0_WRITE_WORD_ENDIAN     TO_REG(0x4c)
+#define   APB2OPB_OPB0_WRITE_WORD_ENDIAN_BE 0x0011101b
+#define APB2OPB_OPB0_WRITE_BYTE_ENDIAN     TO_REG(0x50)
+#define   APB2OPB_OPB0_WRITE_BYTE_ENDIAN_BE 0x0c330f3f
+#define APB2OPB_OPB1_WRITE_WORD_ENDIAN     TO_REG(0x54)
+#define APB2OPB_OPB1_WRITE_BYTE_ENDIAN     TO_REG(0x58)
+#define APB2OPB_OPB0_READ_BYTE_ENDIAN      TO_REG(0x5c)
+#define APB2OPB_OPB1_READ_BYTE_ENDIAN      TO_REG(0x60)
+#define   APB2OPB_OPB0_READ_WORD_ENDIAN_BE  0x00030b1b
+
+#define APB2OPB_OPB0_READ_DATA         TO_REG(0x84)
+#define APB2OPB_OPB1_READ_DATA         TO_REG(0x90)
+
+/*
+ * The following magic values came from AST2600 data sheet
+ * The register values are defined under section "FSI controller"
+ * as initial values.
+ */
+static const uint32_t aspeed_apb2opb_reset[ASPEED_APB2OPB_NR_REGS] = {
+     [APB2OPB_VERSION]                = 0x000000a1,
+     [APB2OPB_OPB0_WRITE_WORD_ENDIAN] = 0x0044eee4,
+     [APB2OPB_OPB0_WRITE_BYTE_ENDIAN] = 0x0055aaff,
+     [APB2OPB_OPB1_WRITE_WORD_ENDIAN] = 0x00117717,
+     [APB2OPB_OPB1_WRITE_BYTE_ENDIAN] = 0xffaa5500,
+     [APB2OPB_OPB0_READ_BYTE_ENDIAN]  = 0x0044eee4,
+     [APB2OPB_OPB1_READ_BYTE_ENDIAN]  = 0x00117717
+};
+
+static void fsi_opb_fsi_master_address(FSIMasterState *fsi, hwaddr addr)
+{
+    memory_region_transaction_begin();
+    memory_region_set_address(&fsi->iomem, addr);
+    memory_region_transaction_commit();
+}
+
+static void fsi_opb_opb2fsi_address(FSIMasterState *fsi, hwaddr addr)
+{
+    memory_region_transaction_begin();
+    memory_region_set_address(&fsi->opb2fsi, addr);
+    memory_region_transaction_commit();
+}
+
+static uint64_t fsi_aspeed_apb2opb_read(void *opaque, hwaddr addr,
+                                        unsigned size)
+{
+    AspeedAPB2OPBState *s = ASPEED_APB2OPB(opaque);
+    unsigned int reg = TO_REG(addr);
+
+    trace_fsi_aspeed_apb2opb_read(addr, size);
+
+    if (reg >= ASPEED_APB2OPB_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
+                      __func__, addr, size);
+        return 0;
+    }
+
+    return s->regs[reg];
+}
+
+static MemTxResult fsi_aspeed_apb2opb_rw(AddressSpace *as, hwaddr addr,
+                                         MemTxAttrs attrs, uint32_t *data,
+                                         uint32_t size, bool is_write)
+{
+    MemTxResult res;
+
+    if (is_write) {
+        switch (size) {
+        case 4:
+            address_space_stl_le(as, addr, *data, attrs, &res);
+            break;
+        case 2:
+            address_space_stw_le(as, addr, *data, attrs, &res);
+            break;
+        case 1:
+            address_space_stb(as, addr, *data, attrs, &res);
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    } else {
+        switch (size) {
+        case 4:
+            *data = address_space_ldl_le(as, addr, attrs, &res);
+            break;
+        case 2:
+            *data = address_space_lduw_le(as, addr, attrs, &res);
+            break;
+        case 1:
+            *data = address_space_ldub(as, addr, attrs, &res);
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    }
+    return res;
+}
+
+static void fsi_aspeed_apb2opb_write(void *opaque, hwaddr addr, uint64_t data,
+                                     unsigned size)
+{
+    AspeedAPB2OPBState *s = ASPEED_APB2OPB(opaque);
+    unsigned int reg = TO_REG(addr);
+
+    trace_fsi_aspeed_apb2opb_write(addr, size, data);
+
+    if (reg >= ASPEED_APB2OPB_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n",
+                      __func__, addr, size);
+        return;
+    }
+
+    switch (reg) {
+    case APB2OPB_CONTROL:
+        fsi_opb_fsi_master_address(&s->fsi[0],
+                data & APB2OPB_CONTROL_OFF);
+        break;
+    case APB2OPB_OPB2FSI:
+        fsi_opb_opb2fsi_address(&s->fsi[0],
+                data & APB2OPB_OPB2FSI_OFF);
+        break;
+    case APB2OPB_OPB0_WRITE_WORD_ENDIAN:
+        if (data != APB2OPB_OPB0_WRITE_WORD_ENDIAN_BE) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Bridge needs to be driven as BE (0x%x)\n",
+                          __func__, APB2OPB_OPB0_WRITE_WORD_ENDIAN_BE);
+        }
+        break;
+    case APB2OPB_OPB0_WRITE_BYTE_ENDIAN:
+        if (data != APB2OPB_OPB0_WRITE_BYTE_ENDIAN_BE) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Bridge needs to be driven as BE (0x%x)\n",
+                          __func__, APB2OPB_OPB0_WRITE_BYTE_ENDIAN_BE);
+        }
+        break;
+    case APB2OPB_OPB0_READ_BYTE_ENDIAN:
+        if (data != APB2OPB_OPB0_READ_WORD_ENDIAN_BE) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Bridge needs to be driven as BE (0x%x)\n",
+                          __func__, APB2OPB_OPB0_READ_WORD_ENDIAN_BE);
+        }
+        break;
+    case APB2OPB_TRIGGER:
+    {
+        uint32_t opb, op_mode, op_size, op_addr, op_data;
+        MemTxResult result;
+        bool is_write;
+        int index;
+        AddressSpace *as;
+
+        assert((s->regs[APB2OPB_OPB0_SEL] & APB2OPB_OPB_SEL_EN) ^
+               (s->regs[APB2OPB_OPB1_SEL] & APB2OPB_OPB_SEL_EN));
+
+        if (s->regs[APB2OPB_OPB0_SEL] & APB2OPB_OPB_SEL_EN) {
+            opb = 0;
+            op_mode = s->regs[APB2OPB_OPB0_MODE];
+            op_size = s->regs[APB2OPB_OPB0_XFER];
+            op_addr = s->regs[APB2OPB_OPB0_ADDR];
+            op_data = s->regs[APB2OPB_OPB0_WRITE_DATA];
+        } else if (s->regs[APB2OPB_OPB1_SEL] & APB2OPB_OPB_SEL_EN) {
+            opb = 1;
+            op_mode = s->regs[APB2OPB_OPB1_MODE];
+            op_size = s->regs[APB2OPB_OPB1_XFER];
+            op_addr = s->regs[APB2OPB_OPB1_ADDR];
+            op_data = s->regs[APB2OPB_OPB1_WRITE_DATA];
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Invalid operation: 0x%"HWADDR_PRIx" for %u\n",
+                          __func__, addr, size);
+            return;
+        }
+
+        if (op_size & ~(APB2OPB_OPB_XFER_HALF | APB2OPB_OPB_XFER_FULL)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "OPB transaction failed: Unrecognized access width: %d\n",
+                          op_size);
+            return;
+        }
+
+        op_size += 1;
+        is_write = !(op_mode & APB2OPB_OPB_MODE_RD);
+        index = opb ? APB2OPB_OPB1_READ_DATA : APB2OPB_OPB0_READ_DATA;
+        as = &s->opb[opb].as;
+
+        result = fsi_aspeed_apb2opb_rw(as, op_addr, MEMTXATTRS_UNSPECIFIED,
+                                       &op_data, op_size, is_write);
+        if (result != MEMTX_OK) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: OPB %s failed @%08x\n",
+                          __func__, is_write ? "write" : "read", op_addr);
+            return;
+        }
+
+        if (!is_write) {
+            s->regs[index] = op_data;
+        }
+
+        s->regs[APB2OPB_IRQ_STS] |= opb ? APB2OPB_IRQ_STS_OPB1_TX_ACK
+            : APB2OPB_IRQ_STS_OPB0_TX_ACK;
+        break;
+    }
+    }
+
+    s->regs[reg] = data;
+}
+
+static const struct MemoryRegionOps aspeed_apb2opb_ops = {
+    .read = fsi_aspeed_apb2opb_read,
+    .write = fsi_aspeed_apb2opb_write,
+    .valid.max_access_size = 4,
+    .valid.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .impl.min_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void fsi_aspeed_apb2opb_init(Object *o)
+{
+    AspeedAPB2OPBState *s = ASPEED_APB2OPB(o);
+    int i;
+
+    for (i = 0; i < ASPEED_FSI_NUM; i++) {
+        object_initialize_child(o, "fsi-master[*]", &s->fsi[i],
+                                TYPE_FSI_MASTER);
+    }
+}
+
+static void fsi_aspeed_apb2opb_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    AspeedAPB2OPBState *s = ASPEED_APB2OPB(dev);
+    int i;
+
+    /*
+     * TODO: The OPBus model initializes the OPB address space in
+     * the .instance_init handler and this is problematic for test
+     * device-introspect-test. To avoid a memory corruption and a QEMU
+     * crash, qbus_init() should be called from realize(). Something to
+     * improve. Possibly, OPBus could also be removed.
+     */
+    for (i = 0; i < ASPEED_FSI_NUM; i++) {
+        qbus_init(&s->opb[i], sizeof(s->opb[i]), TYPE_OP_BUS, DEVICE(s),
+                  NULL);
+    }
+
+    sysbus_init_irq(sbd, &s->irq);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_apb2opb_ops, s,
+                          TYPE_ASPEED_APB2OPB, 0x1000);
+    sysbus_init_mmio(sbd, &s->iomem);
+
+    for (i = 0; i < ASPEED_FSI_NUM; i++) {
+        if (!qdev_realize(DEVICE(&s->fsi[i]), BUS(&s->opb[i]), errp)) {
+            return;
+        }
+
+        memory_region_add_subregion(&s->opb[i].mr, 0x80000000,
+                &s->fsi[i].iomem);
+
+        memory_region_add_subregion(&s->opb[i].mr, 0xa0000000,
+                &s->fsi[i].opb2fsi);
+    }
+}
+
+static void fsi_aspeed_apb2opb_reset(DeviceState *dev)
+{
+    AspeedAPB2OPBState *s = ASPEED_APB2OPB(dev);
+
+    memcpy(s->regs, aspeed_apb2opb_reset, ASPEED_APB2OPB_NR_REGS);
+}
+
+static void fsi_aspeed_apb2opb_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "ASPEED APB2OPB Bridge";
+    dc->realize = fsi_aspeed_apb2opb_realize;
+    dc->reset = fsi_aspeed_apb2opb_reset;
+}
+
+static const TypeInfo aspeed_apb2opb_info = {
+    .name = TYPE_ASPEED_APB2OPB,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_init = fsi_aspeed_apb2opb_init,
+    .instance_size = sizeof(AspeedAPB2OPBState),
+    .class_init = fsi_aspeed_apb2opb_class_init,
+};
+
+static void aspeed_apb2opb_register_types(void)
+{
+    type_register_static(&aspeed_apb2opb_info);
+}
+
+type_init(aspeed_apb2opb_register_types);
+
+static void fsi_opb_init(Object *o)
+{
+    OPBus *opb = OP_BUS(o);
+
+    memory_region_init(&opb->mr, 0, TYPE_FSI_OPB, UINT32_MAX);
+    address_space_init(&opb->as, &opb->mr, TYPE_FSI_OPB);
+}
+
+static const TypeInfo opb_info = {
+    .name = TYPE_OP_BUS,
+    .parent = TYPE_BUS,
+    .instance_init = fsi_opb_init,
+    .instance_size = sizeof(OPBus),
+};
+
+static void fsi_opb_register_types(void)
+{
+    type_register_static(&opb_info);
+}
+
+type_init(fsi_opb_register_types);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ASPEED_SOC
     select LED
     select PMBUS
     select MAX31785
+    select FSI_APB2OPB_ASPEED
 
 config MPS2
     bool
diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/Kconfig
+++ b/hw/fsi/Kconfig
@@ -XXX,XX +XXX,XX @@
+config FSI_APB2OPB_ASPEED
+    bool
+    depends on ASPEED_SOC
+    select FSI
+
 config FSI
     bool
diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/meson.build
+++ b/hw/fsi/meson.build
@@ -1 +1,2 @@
 system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c','fsi-master.c'))
+system_ss.add(when: 'CONFIG_FSI_APB2OPB_ASPEED', if_true: files('aspeed_apb2opb.c'))
diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/fsi/trace-events
+++ b/hw/fsi/trace-events
@@ -XXX,XX +XXX,XX @@ fsi_cfam_unimplemented_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%"
 fsi_cfam_config_write_noaddr(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
 fsi_master_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
 fsi_master_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
+fsi_aspeed_apb2opb_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
+fsi_aspeed_apb2opb_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

This patchset introduces IBM's Flexible Service Interface(FSI).

Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.

FSI has long existed in POWER processes and so comes with some baggage,
including how it has been integrated into the ASPEED SoC.

Working backwards from the POWER processor, the fundamental pieces of
interest for the implementation are:

1. The Common FRU Access Macro (CFAM), an address space containing
   various "engines" that drive accesses on buses internal and external
   to the POWER chip. Examples include the SBEFIFO and I2C masters. The
   engines hang off of an internal Local Bus (LBUS) which is described
   by the CFAM configuration block.

2. The FSI slave: The slave is the terminal point of the FSI bus for
   FSI symbols addressed to it. Slaves can be cascaded off of one
   another. The slave's configuration registers appear in address space
   of the CFAM to which it is attached.

3. The FSI master: A controller in the platform service processor (e.g.
   BMC) driving CFAM engine accesses into the POWER chip. At the
   hardware level FSI is a bit-based protocol supporting synchronous and
   DMA-driven accesses of engines in a CFAM.

4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
   POWER processors. This now makes an appearance in the ASPEED SoC due
   to tight integration of the FSI master IP with the OPB, mainly the
   existence of an MMIO-mapping of the CFAM address straight onto a
   sub-region of the OPB address space.

5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in
   the AST2600. Hardware limitations prevent the OPB from being directly
   mapped into APB, so all accesses are indirect through the bridge.

The implementation appears as following in the qemu device tree:

(qemu) info qtree
    bus: main-system-bus
      type System
      ...
      dev: aspeed.apb2opb, id ""
        gpio-out "sysbus-irq" 1
        mmio 000000001e79b000/0000000000001000
        bus: opb.1
          type opb
          dev: fsi.master, id ""
            bus: fsi.bus.1
              type fsi.bus
              dev: cfam.config, id ""
              dev: cfam, id ""
                bus: fsi.lbus.1
                  type lbus
                  dev: scratchpad, id ""
                    address = 0 (0x0)
        bus: opb.0
          type opb
          dev: fsi.master, id ""
            bus: fsi.bus.0
              type fsi.bus
              dev: cfam.config, id ""
              dev: cfam, id ""
                bus: fsi.lbus.0
                  type lbus
                  dev: scratchpad, id ""
                    address = 0 (0x0)

The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration block presents engines in the
order they are attached to the CFAM's LBUS. Engine implementations
should subclass the LBusDevice and set the 'config' member of
LBusDeviceClass to match the engine's type.

CFAM designs offer a lot of flexibility, for instance it is possible for
a CFAM to be simultaneously driven from multiple FSI links. The modeling
is not so complete; it's assumed that each CFAM is attached to a single
FSI slave (as a consequence the CFAM subclasses the FSI slave).

As for FSI, its symbols and wire-protocol are not modelled at all. This
is not necessary to get FSI off the ground thanks to the mapping of the
CFAM address space onto the OPB address space - the models follow this
directly and map the CFAM memory region into the OPB's memory region.
Future work includes supporting more advanced accesses that drive the
FSI master directly rather than indirectly via the CFAM mapping, which
will require implementing the FSI state machine and methods for each of
the FSI symbols on the slave. Further down the track we can also look at
supporting the bitbanged SoftFSI drivers in Linux by extending the FSI
slave model to resolve sequences of GPIO IRQs into FSI symbols, and
calling the associated symbol method on the slave to map the access onto
the CFAM.

Testing:
    Tested by reading cfam config address 0 on rainier machine type.

root@p10bmc:~# pdbg -a getcfam 0x0
    p0: 0x0 = 0xc0022d15

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  4 ++++
 hw/arm/aspeed_ast2600.c     | 19 +++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/aspeed_lpc.h"
 #include "hw/misc/unimp.h"
 #include "hw/misc/aspeed_peci.h"
+#include "hw/fsi/aspeed_apb2opb.h"
 #include "hw/char/serial.h"
 
 #define ASPEED_SPIS_NUM  2
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     UnimplementedDeviceState udc;
     UnimplementedDeviceState sgpiom;
     UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
+    AspeedAPB2OPBState fsi[2];
 };
 
 #define TYPE_ASPEED_SOC "aspeed-soc"
@@ -XXX,XX +XXX,XX @@ enum {
     ASPEED_DEV_SGPIOM,
     ASPEED_DEV_JTAG0,
     ASPEED_DEV_JTAG1,
+    ASPEED_DEV_FSI1,
+    ASPEED_DEV_FSI2,
 };
 
 #define ASPEED_SOC_SPI_BOOT_ADDR 0x0
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
     [ASPEED_DEV_UART12]    = 0x1E790600,
     [ASPEED_DEV_UART13]    = 0x1E790700,
     [ASPEED_DEV_VUART]     = 0x1E787000,
+    [ASPEED_DEV_FSI1]      = 0x1E79B000,
+    [ASPEED_DEV_FSI2]      = 0x1E79B100,
     [ASPEED_DEV_I3C]       = 0x1E7A0000,
     [ASPEED_DEV_SDRAM]     = 0x80000000,
 };
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
     [ASPEED_DEV_ETH4]      = 33,
     [ASPEED_DEV_KCS]       = 138,   /* 138 -> 142 */
     [ASPEED_DEV_DP]        = 62,
+    [ASPEED_DEV_FSI1]      = 100,
+    [ASPEED_DEV_FSI2]      = 101,
     [ASPEED_DEV_I3C]       = 102,   /* 102 -> 107 */
 };
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     object_initialize_child(obj, "emmc-boot-controller",
                             &s->emmc_boot_controller,
                             TYPE_UNIMPLEMENTED_DEVICE);
+
+    for (i = 0; i < ASPEED_FSI_NUM; i++) {
+        object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB);
+    }
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
         return;
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
+
+    /* FSI */
+    for (i = 0; i < ASPEED_FSI_NUM; i++) {
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) {
+            return;
+        }
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0,
+                        sc->memmap[ASPEED_DEV_FSI1 + i]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0,
+                           aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i));
+    }
 }
 
 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

Added basic qtests for FSI model.

Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
[ clg: aspeed-fsi-test.c -> aspeed_fsi-test.c to match other filenames ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/qtest/aspeed_fsi-test.c | 205 ++++++++++++++++++++++++++++++++++
 tests/qtest/meson.build       |   1 +
 2 files changed, 206 insertions(+)
 create mode 100644 tests/qtest/aspeed_fsi-test.c

diff --git a/tests/qtest/aspeed_fsi-test.c b/tests/qtest/aspeed_fsi-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/aspeed_fsi-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTest testcases for IBM's Flexible Service Interface (FSI)
+ *
+ * Copyright (c) 2023 IBM Corporation
+ *
+ * Authors:
+ *   Ninad Palsule <ninad@linux.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include <glib/gstdio.h>
+
+#include "qemu/module.h"
+#include "libqtest-single.h"
+
+/* Registers from ast2600 specifications */
+#define ASPEED_FSI_ENGINER_TRIGGER   0x04
+#define ASPEED_FSI_OPB0_BUS_SELECT   0x10
+#define ASPEED_FSI_OPB1_BUS_SELECT   0x28
+#define ASPEED_FSI_OPB0_RW_DIRECTION 0x14
+#define ASPEED_FSI_OPB1_RW_DIRECTION 0x2c
+#define ASPEED_FSI_OPB0_XFER_SIZE    0x18
+#define ASPEED_FSI_OPB1_XFER_SIZE    0x30
+#define ASPEED_FSI_OPB0_BUS_ADDR     0x1c
+#define ASPEED_FSI_OPB1_BUS_ADDR     0x34
+#define ASPEED_FSI_INTRRUPT_CLEAR    0x40
+#define ASPEED_FSI_INTRRUPT_STATUS   0x48
+#define ASPEED_FSI_OPB0_BUS_STATUS   0x80
+#define ASPEED_FSI_OPB1_BUS_STATUS   0x8c
+#define ASPEED_FSI_OPB0_READ_DATA    0x84
+#define ASPEED_FSI_OPB1_READ_DATA    0x90
+
+/*
+ * FSI Base addresses from the ast2600 specifications.
+ */
+#define AST2600_OPB_FSI0_BASE_ADDR 0x1e79b000
+#define AST2600_OPB_FSI1_BASE_ADDR 0x1e79b100
+
+static uint32_t aspeed_fsi_base_addr;
+
+static uint32_t aspeed_fsi_readl(QTestState *s, uint32_t reg)
+{
+    return qtest_readl(s, aspeed_fsi_base_addr + reg);
+}
+
+static void aspeed_fsi_writel(QTestState *s, uint32_t reg, uint32_t val)
+{
+    qtest_writel(s, aspeed_fsi_base_addr + reg, val);
+}
+
+/* Setup base address and select register */
+static void test_fsi_setup(QTestState *s, uint32_t base_addr)
+{
+    uint32_t curval;
+
+    aspeed_fsi_base_addr = base_addr;
+
+    /* Set the base select register */
+    if (base_addr == AST2600_OPB_FSI0_BASE_ADDR) {
+        /* Unselect FSI1 */
+        aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x0);
+        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
+        g_assert_cmpuint(curval, ==, 0x0);
+
+        /* Select FSI0 */
+        aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x1);
+        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
+        g_assert_cmpuint(curval, ==, 0x1);
+    } else if (base_addr == AST2600_OPB_FSI1_BASE_ADDR) {
+        /* Unselect FSI0 */
+        aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x0);
+        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
+        g_assert_cmpuint(curval, ==, 0x0);
+
+        /* Select FSI1 */
+        aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x1);
+        curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
+        g_assert_cmpuint(curval, ==, 0x1);
+    } else {
+        g_assert_not_reached();
+    }
+}
+
+static void test_fsi_reg_change(QTestState *s, uint32_t reg, uint32_t newval)
+{
+    uint32_t base;
+    uint32_t curval;
+
+    base = aspeed_fsi_readl(s, reg);
+    aspeed_fsi_writel(s, reg, newval);
+    curval = aspeed_fsi_readl(s, reg);
+    g_assert_cmpuint(curval, ==, newval);
+    aspeed_fsi_writel(s, reg, base);
+    curval = aspeed_fsi_readl(s, reg);
+    g_assert_cmpuint(curval, ==, base);
+}
+
+static void test_fsi0_master_regs(const void *data)
+{
+    QTestState *s = (QTestState *)data;
+
+    test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
+
+    test_fsi_reg_change(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0xF3F4F514);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB0_XFER_SIZE, 0xF3F4F518);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xF3F4F51c);
+    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
+    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_STATUS, 0xF3F4F580);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB0_READ_DATA, 0xF3F4F584);
+}
+
+static void test_fsi1_master_regs(const void *data)
+{
+    QTestState *s = (QTestState *)data;
+
+    test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
+
+    test_fsi_reg_change(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0xF3F4F514);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB1_XFER_SIZE, 0xF3F4F518);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xF3F4F51c);
+    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
+    test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_STATUS, 0xF3F4F580);
+    test_fsi_reg_change(s, ASPEED_FSI_OPB1_READ_DATA, 0xF3F4F584);
+}
+
+static void test_fsi0_getcfam_addr0(const void *data)
+{
+    QTestState *s = (QTestState *)data;
+    uint32_t curval;
+
+    test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
+
+    /* Master access direction read */
+    aspeed_fsi_writel(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0x1);
+    /* word */
+    aspeed_fsi_writel(s, ASPEED_FSI_OPB0_XFER_SIZE, 0x3);
+    /* Address */
+    aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xa0000000);
+    aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
+    aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
+
+    curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
+    g_assert_cmpuint(curval, ==, 0x10000);
+    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_STATUS);
+    g_assert_cmpuint(curval, ==, 0x0);
+    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_READ_DATA);
+    g_assert_cmpuint(curval, ==, 0x152d02c0);
+}
+
+static void test_fsi1_getcfam_addr0(const void *data)
+{
+    QTestState *s = (QTestState *)data;
+    uint32_t curval;
+
+    test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
+
+    /* Master access direction read */
+    aspeed_fsi_writel(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0x1);
+
+    aspeed_fsi_writel(s, ASPEED_FSI_OPB1_XFER_SIZE, 0x3);
+    aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xa0000000);
+    aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
+    aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
+
+    curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
+    g_assert_cmpuint(curval, ==, 0x20000);
+    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_STATUS);
+    g_assert_cmpuint(curval, ==, 0x0);
+    curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_READ_DATA);
+    g_assert_cmpuint(curval, ==, 0x152d02c0);
+}
+
+int main(int argc, char **argv)
+{
+    int ret = -1;
+    QTestState *s;
+
+    g_test_init(&argc, &argv, NULL);
+
+    s = qtest_init("-machine ast2600-evb ");
+
+    /* Tests for OPB/FSI0 */
+    qtest_add_data_func("/aspeed-fsi-test/test_fsi0_master_regs", s,
+                        test_fsi0_master_regs);
+
+    qtest_add_data_func("/aspeed-fsi-test/test_fsi0_getcfam_addr0", s,
+                        test_fsi0_getcfam_addr0);
+
+    /* Tests for OPB/FSI1 */
+    qtest_add_data_func("/aspeed-fsi-test/test_fsi1_master_regs", s,
+                        test_fsi1_master_regs);
+
+    qtest_add_data_func("/aspeed-fsi-test/test_fsi1_getcfam_addr0", s,
+                        test_fsi1_getcfam_addr0);
+
+    ret = g_test_run();
+    qtest_quit(s);
+
+    return ret;
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
   (config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
   (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
   (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
+  (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
   ['arm-cpu-features',
    'boot-serial-test']
 
-- 
2.43.0

From: Ninad Palsule <ninad@linux.ibm.com>

Documentation for IBM FSI model.

Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : - Removed source file list
        - Fixed aspeed machine reference ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 docs/specs/fsi.rst   | 122 +++++++++++++++++++++++++++++++++++++++++++
 docs/specs/index.rst |   1 +
 2 files changed, 123 insertions(+)
 create mode 100644 docs/specs/fsi.rst

diff --git a/docs/specs/fsi.rst b/docs/specs/fsi.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/specs/fsi.rst
@@ -XXX,XX +XXX,XX @@
+======================================
+IBM's Flexible Service Interface (FSI)
+======================================
+
+The QEMU FSI emulation implements hardware interfaces between ASPEED SOC, FSI
+master/slave and the end engine.
+
+FSI is a point-to-point two wire interface which is capable of supporting
+distances of up to 4 meters. FSI interfaces have been used successfully for
+many years in IBM servers to attach IBM Flexible Support Processors(FSP) to
+CPUs and IBM ASICs.
+
+FSI allows a service processor access to the internal buses of a host POWER
+processor to perform configuration or debugging. FSI has long existed in POWER
+processes and so comes with some baggage, including how it has been integrated
+into the ASPEED SoC.
+
+Working backwards from the POWER processor, the fundamental pieces of interest
+for the implementation are: (see the `FSI specification`_ for more details)
+
+1. The Common FRU Access Macro (CFAM), an address space containing various
+   "engines" that drive accesses on buses internal and external to the POWER
+   chip. Examples include the SBEFIFO and I2C masters. The engines hang off of
+   an internal Local Bus (LBUS) which is described by the CFAM configuration
+   block.
+
+2. The FSI slave: The slave is the terminal point of the FSI bus for FSI
+   symbols addressed to it. Slaves can be cascaded off of one another. The
+   slave's configuration registers appear in address space of the CFAM to
+   which it is attached.
+
+3. The FSI master: A controller in the platform service processor (e.g. BMC)
+   driving CFAM engine accesses into the POWER chip. At the hardware level
+   FSI is a bit-based protocol supporting synchronous and DMA-driven accesses
+   of engines in a CFAM.
+
+4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER
+   processors. This now makes an appearance in the ASPEED SoC due to tight
+   integration of the FSI master IP with the OPB, mainly the existence of an
+   MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
+   address space.
+
+5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
+   AST2600. Hardware limitations prevent the OPB from being directly mapped
+   into APB, so all accesses are indirect through the bridge.
+
+The LBUS is modelled to maintain the qdev bus hierarchy and to take advantages
+of the object model to automatically generate the CFAM configuration block.
+The configuration block presents engines in the order they are attached to the
+CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the
+'config' member of LBusDeviceClass to match the engine's type.
+
+CFAM designs offer a lot of flexibility, for instance it is possible for a
+CFAM to be simultaneously driven from multiple FSI links. The modeling is not
+so complete; it's assumed that each CFAM is attached to a single FSI slave (as
+a consequence the CFAM subclasses the FSI slave).
+
+As for FSI, its symbols and wire-protocol are not modelled at all. This is not
+necessary to get FSI off the ground thanks to the mapping of the CFAM address
+space onto the OPB address space - the models follow this directly and map the
+CFAM memory region into the OPB's memory region.
+
+The following commands start the ``rainier-bmc`` machine with built-in FSI
+model. There are no model specific arguments. Please check this document to
+learn more about Aspeed ``rainier-bmc`` machine: (:doc:`../../system/arm/aspeed`)
+
+.. code-block:: console
+
+  qemu-system-arm -M rainier-bmc -nographic \
+  -kernel fitImage-linux.bin \
+  -dtb aspeed-bmc-ibm-rainier.dtb \
+  -initrd obmc-phosphor-initramfs.rootfs.cpio.xz \
+  -drive file=obmc-phosphor-image.rootfs.wic.qcow2,if=sd,index=2 \
+  -append "rootwait console=ttyS4,115200n8 root=PARTLABEL=rofs-a"
+
+The implementation appears as following in the qemu device tree:
+
+.. code-block:: console
+
+  (qemu) info qtree
+  bus: main-system-bus
+    type System
+    ...
+    dev: aspeed.apb2opb, id ""
+      gpio-out "sysbus-irq" 1
+      mmio 000000001e79b000/0000000000001000
+      bus: opb.1
+        type opb
+        dev: fsi.master, id ""
+          bus: fsi.bus.1
+            type fsi.bus
+            dev: cfam.config, id ""
+            dev: cfam, id ""
+              bus: lbus.1
+                type lbus
+                dev: scratchpad, id ""
+                  address = 0 (0x0)
+      bus: opb.0
+        type opb
+        dev: fsi.master, id ""
+          bus: fsi.bus.0
+            type fsi.bus
+            dev: cfam.config, id ""
+            dev: cfam, id ""
+              bus: lbus.0
+                type lbus
+                dev: scratchpad, id ""
+                  address = 0 (0x0)
+
+pdbg is a simple application to allow debugging of the host POWER processors
+from the BMC. (see the `pdbg source repository`_ for more details)
+
+.. code-block:: console
+
+  root@p10bmc:~# pdbg -a getcfam 0x0
+  p0: 0x0 = 0xc0022d15
+
+.. _FSI specification:
+   https://openpowerfoundation.org/specifications/fsi/
+
+.. _pdbg source repository:
+   https://github.com/open-power/pdbg
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/specs/index.rst
+++ b/docs/specs/index.rst
@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
    acpi_erst
    sev-guest-firmware
    fw_cfg
+   fsi
    vmw_pvscsi-spec
    edu
    ivshmem-spec
-- 
2.43.0