The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:

Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20231025

for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:

hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)

----------------------------------------------------------------

aspeed queue:

* Update of Andrew's email

* Split of AspeedSoCState per 2400/2600/10x0

----------------------------------------------------------------

Andrew Jeffery (1):

MAINTAINERS: aspeed: Update Andrew's email address

Philippe Mathieu-Daudé (11):

hw/arm/aspeed: Extract code common to all boards to a common file

hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific

hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific

hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field

hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC

hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC

hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC

hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize

hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState

hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState

hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState

MAINTAINERS | 2 +-

include/hw/arm/aspeed_soc.h | 35 +++++-

hw/arm/aspeed.c | 101 +++++++--------

hw/arm/aspeed_ast10x0.c | 53 ++++----

hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------

hw/arm/aspeed_ast2600.c | 75 ++++++------

hw/arm/aspeed_soc_common.c | 154 +++++++++++++++++++++++

hw/arm/fby35.c | 27 ++--

hw/arm/meson.build | 3 +-

9 files changed, 363 insertions(+), 284 deletions(-)

rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)

create mode 100644 hw/arm/aspeed_soc_common.c

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The ARM array and VIC peripheral are only used by the

2400 series, remove them from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

include/hw/arm/aspeed_soc.h | 5 +++--

hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------

hw/arm/meson.build | 2 +-

3 files changed, 19 insertions(+), 15 deletions(-)

rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h

--- a/include/hw/arm/aspeed_soc.h

+++ b/include/hw/arm/aspeed_soc.h

@@ -XXX,XX +XXX,XX @@

struct AspeedSoCState {

DeviceState parent;

- ARMCPU cpu[ASPEED_CPUS_NUM];

MemoryRegion *memory;

MemoryRegion *dram_mr;

MemoryRegion dram_container;

MemoryRegion sram;

MemoryRegion spi_boot_container;

MemoryRegion spi_boot;

- AspeedVICState vic;

AspeedRtcState rtc;

AspeedTimerCtrlState timerctrl;

AspeedI2CState i2c;

@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)

struct Aspeed2400SoCState {

AspeedSoCState parent;

+

+ ARMCPU cpu[ASPEED_CPUS_NUM];

+ AspeedVICState vic;

};

#define TYPE_ASPEED2400_SOC "aspeed2400-soc"

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c

similarity index 95%

rename from hw/arm/aspeed_soc.c

rename to hw/arm/aspeed_ast2400.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_soc.c

+++ b/hw/arm/aspeed_ast2400.c

@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {

static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)

{

+ Aspeed2400SoCState *a = ASPEED2400_SOC(s);

AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

- return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);

+ return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);

}

static void aspeed_ast2400_soc_init(Object *obj)

{

+ Aspeed2400SoCState *a = ASPEED2400_SOC(obj);

AspeedSoCState *s = ASPEED_SOC(obj);

AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

int i;

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)

}

for (i = 0; i < sc->num_cpus; i++) {

- object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);

+ object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);

}

snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)

object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),

"hw-prot-key");

- object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);

+ object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);

object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)

static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)

{

int i;

+ Aspeed2400SoCState *a = ASPEED2400_SOC(dev);

AspeedSoCState *s = ASPEED_SOC(dev);

AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

Error *err = NULL;

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)

/* CPU */

for (i = 0; i < sc->num_cpus; i++) {

- object_property_set_link(OBJECT(&s->cpu[i]), "memory",

+ object_property_set_link(OBJECT(&a->cpu[i]), "memory",

OBJECT(s->memory), &error_abort);

- if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {

+ if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {

return;

}

/* SRAM */

- sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);

+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);

memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);

if (err) {

error_propagate(errp, err);

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)

aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);

/* VIC */

- if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {

+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {

return;

}

- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);

- sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,

- qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));

- sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,

- qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,

+ qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));

+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,

+ qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));

/* RTC */

if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {

diff --git a/hw/arm/meson.build b/hw/arm/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/meson.build

+++ b/hw/arm/meson.build

@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'

arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))

arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))

arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(

- 'aspeed_soc.c',

'aspeed.c',

'aspeed_soc_common.c',

+ 'aspeed_ast2400.c',

'aspeed_ast2600.c',

'aspeed_ast10x0.c',

'aspeed_eeprom.c',

2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-M core is specific to the Aspeed 10x0 series,

remove it from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

include/hw/arm/aspeed_soc.h | 5 ++---

hw/arm/aspeed_ast10x0.c | 27 +++++++++++++++------------

hw/arm/fby35.c | 13 ++++++++-----

3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h

--- a/include/hw/arm/aspeed_soc.h

+++ b/include/hw/arm/aspeed_soc.h

@@ -XXX,XX +XXX,XX @@

#define ASPEED_JTAG_NUM 2

struct AspeedSoCState {

- /*< private >*/

DeviceState parent;

- /*< public >*/

ARMCPU cpu[ASPEED_CPUS_NUM];

A15MPPrivState a7mpcore;

- ARMv7MState armv7m;

MemoryRegion *memory;

MemoryRegion *dram_mr;

MemoryRegion dram_container;

@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)

struct Aspeed10x0SoCState {

AspeedSoCState parent;

+ ARMv7MState armv7m;

};

#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"

diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c

--- a/hw/arm/aspeed_ast10x0.c

+++ b/hw/arm/aspeed_ast10x0.c

@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {

static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)

+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);

AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

- return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);

+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);

static void aspeed_soc_ast1030_init(Object *obj)

+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);

AspeedSoCState *s = ASPEED_SOC(obj);

AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

char socname[8];

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)

g_assert_not_reached();

- object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);

+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);

s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)

static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)

{

+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);

AspeedSoCState *s = ASPEED_SOC(dev_soc);

AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

DeviceState *armv7m;

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)

0x40000);

/* AST1030 CPU Core */

- armv7m = DEVICE(&s->armv7m);

+ armv7m = DEVICE(&a->armv7m);

qdev_prop_set_uint32(armv7m, "num-irq", 256);

qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);

qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);

- object_property_set_link(OBJECT(&s->armv7m), "memory",

+ object_property_set_link(OBJECT(&a->armv7m), "memory",

OBJECT(s->memory), &error_abort);

- sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);

+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);

/* Internal SRAM */

sram_name = g_strdup_printf("aspeed.sram.%d",

- CPU(s->armv7m.cpu)->cpu_index);

+ CPU(a->armv7m.cpu)->cpu_index);

memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);

if (err != NULL) {

error_propagate(errp, err);

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)

}

aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);

for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {

- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),

+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),

sc->irqmap[ASPEED_DEV_I2C] + i);

/* The AST1030 I2C controller has one IRQ per bus. */

sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)

}

aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);

for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {

- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),

+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),

sc->irqmap[ASPEED_DEV_I3C] + i);

/* The AST1030 I3C controller has one IRQ per bus. */

sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)

* On the AST1030 LPC subdevice IRQs are connected straight to the GIC.

*/

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,

- qdev_get_gpio_in(DEVICE(&s->armv7m),

+ qdev_get_gpio_in(DEVICE(&a->armv7m),

sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,

- qdev_get_gpio_in(DEVICE(&s->armv7m),

+ qdev_get_gpio_in(DEVICE(&a->armv7m),

sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,

- qdev_get_gpio_in(DEVICE(&s->armv7m),

+ qdev_get_gpio_in(DEVICE(&a->armv7m),

sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,

- qdev_get_gpio_in(DEVICE(&s->armv7m),

+ qdev_get_gpio_in(DEVICE(&a->armv7m),

sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));

/* UART */

diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/fby35.c

+++ b/hw/arm/fby35.c

@@ -XXX,XX +XXX,XX @@ struct Fby35State {

Clock *bic_sysclk;

AspeedSoCState bmc;

- AspeedSoCState bic;

+ Aspeed10x0SoCState bic;

bool mmio_exec;

};

@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)

static void fby35_bic_init(Fby35State *s)

{

+ AspeedSoCState *soc;

+

s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");

clock_set_hz(s->bic_sysclk, 200000000ULL);

object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");

+ soc = ASPEED_SOC(&s->bic);

memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",

UINT64_MAX);

@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)

qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);

object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),

&error_abort);

- aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));

+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));

qdev_realize(DEVICE(&s->bic), NULL, &error_abort);

- aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);

- aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);

- aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);

+ aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);

+ aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);

+ aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);

static void fby35_init(MachineState *machine)

2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

aspeed_soc.c contains definitions specific to the AST2400

and AST2500 SoCs, but also some definitions for other AST

SoCs: move them to a common file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

hw/arm/aspeed_soc.c | 96 -------------------------------

hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++

hw/arm/meson.build | 1 +

3 files changed, 115 insertions(+), 96 deletions(-)

create mode 100644 hw/arm/aspeed_soc_common.c

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_soc.c

+++ b/hw/arm/aspeed_soc.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)

};

type_init(aspeed_soc_register_types);

-

-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)

-{

- return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);

-}

-

-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)

-{

- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

- SerialMM *smm;

-

- for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {

- smm = &s->uart[i];

-

- /* Chardev property is set by the machine. */

- qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);

- qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);

- qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);

- qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);

- if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {

- return false;

- }

-

- sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));

- aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);

- }

-

- return true;

-}

-

-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)

-{

- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

- int i = dev - ASPEED_DEV_UART1;

-

- g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);

- qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);

-}

-

-/*

- * SDMC should be realized first to get correct RAM size and max size

- * values

- */

-bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)

-{

- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

- ram_addr_t ram_size, max_ram_size;

-

- ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",

- &error_abort);

- max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",

- &error_abort);

-

- memory_region_init(&s->dram_container, OBJECT(s), "ram-container",

- max_ram_size);

- memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);

-

- /*

- * Add a memory region beyond the RAM region to let firmwares scan

- * the address space with load/store and guess how much RAM the

- * SoC has.

- */

- if (ram_size < max_ram_size) {

- DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);

-

- qdev_prop_set_string(dev, "name", "ram-empty");

- qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);

- if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {

- return false;

- }

-

- memory_region_add_subregion_overlap(&s->dram_container, ram_size,

- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);

- }

-

- memory_region_add_subregion(s->memory,

- sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);

- return true;

-}

-

-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)

-{

- memory_region_add_subregion(s->memory, addr,

- sysbus_mmio_get_region(dev, n));

-}

-

-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,

- const char *name, hwaddr addr, uint64_t size)

-{

- qdev_prop_set_string(DEVICE(dev), "name", name);

- qdev_prop_set_uint64(DEVICE(dev), "size", size);

- sysbus_realize(dev, &error_abort);

-

- memory_region_add_subregion_overlap(s->memory, addr,

- sysbus_mmio_get_region(dev, 0), -1000);

-}

diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c

+++ b/hw/arm/aspeed_soc_common.c

+/*

+ * ASPEED SoC family

+ *

+ * Andrew Jeffery <andrew@aj.id.au>

+ * Jeremy Kerr <jk@ozlabs.org>

+ *

+ * Copyright 2016 IBM Corp.

+ *

+ * This code is licensed under the GPL version 2 or later. See

+ * the COPYING file in the top-level directory.

+ */

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "hw/misc/unimp.h"

+#include "hw/arm/aspeed_soc.h"

+#include "hw/char/serial.h"

+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)

+{

+ return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);

+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)

+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

+ SerialMM *smm;

+ for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {

+ smm = &s->uart[i];

+ /* Chardev property is set by the machine. */

+ qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);

+ qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);

+ qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);

+ qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);

+ if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {

+ return false;

+ }

+ sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));

+ aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);

+ return true;

+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)

+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

+ int i = dev - ASPEED_DEV_UART1;

+ g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);

+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);

+/*

+ * SDMC should be realized first to get correct RAM size and max size

+ * values

+ */

+bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)

+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

+ ram_addr_t ram_size, max_ram_size;

+ ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",

+ &error_abort);

+ max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",

+ &error_abort);

+

+ memory_region_init(&s->dram_container, OBJECT(s), "ram-container",

+ max_ram_size);

+ memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);

+

+ /*

+ * Add a memory region beyond the RAM region to let firmwares scan

+ * the address space with load/store and guess how much RAM the

+ * SoC has.

+ */

+ if (ram_size < max_ram_size) {

+ DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);

+

+ qdev_prop_set_string(dev, "name", "ram-empty");

+ qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);

+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {

+ return false;

+ }

+

+ memory_region_add_subregion_overlap(&s->dram_container, ram_size,

+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);

+ memory_region_add_subregion(s->memory,

+ sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);

+ return true;

+void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)

+ memory_region_add_subregion(s->memory, addr,

+ sysbus_mmio_get_region(dev, n));

+void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,

+ const char *name, hwaddr addr, uint64_t size)

+ qdev_prop_set_string(DEVICE(dev), "name", name);

+ qdev_prop_set_uint64(DEVICE(dev), "size", size);

+ sysbus_realize(dev, &error_abort);

+ memory_region_add_subregion_overlap(s->memory, addr,

+ sysbus_mmio_get_region(dev, 0), -1000);

diff --git a/hw/arm/meson.build b/hw/arm/meson.build

--- a/hw/arm/meson.build

+++ b/hw/arm/meson.build

@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))

arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(

'aspeed_soc.c',

'aspeed.c',

+ 'aspeed_soc_common.c',

'aspeed_ast2600.c',

'aspeed_ast10x0.c',

'aspeed_eeprom.c',

2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.

In few commits we'll add more fields, but to keep

review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

include/hw/arm/aspeed_soc.h | 7 +++++++

hw/arm/aspeed_ast2600.c | 26 +++++++++++++-------------

2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h

--- a/include/hw/arm/aspeed_soc.h

+++ b/include/hw/arm/aspeed_soc.h

@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {

#define TYPE_ASPEED_SOC "aspeed-soc"

OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)

+struct Aspeed2600SoCState {

+ AspeedSoCState parent;

+};

+

+#define TYPE_ASPEED2600_SOC "aspeed2600-soc"

+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)

+

struct Aspeed10x0SoCState {

AspeedSoCState parent;

};

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast2600.c

+++ b/hw/arm/aspeed_ast2600.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)

sc->get_irq = aspeed_soc_ast2600_get_irq;

}

-static const TypeInfo aspeed_soc_ast2600_type_info = {

- .name = "ast2600-a3",

- .parent = TYPE_ASPEED_SOC,

- .instance_size = sizeof(AspeedSoCState),

- .instance_init = aspeed_soc_ast2600_init,

- .class_init = aspeed_soc_ast2600_class_init,

- .class_size = sizeof(AspeedSoCClass),

+static const TypeInfo aspeed_soc_ast2600_types[] = {

+ {

+ .name = TYPE_ASPEED2600_SOC,

+ .parent = TYPE_ASPEED_SOC,

+ .instance_size = sizeof(Aspeed2600SoCState),

+ .abstract = true,

+ }, {

+ .name = "ast2600-a3",

+ .parent = TYPE_ASPEED2600_SOC,

+ .instance_init = aspeed_soc_ast2600_init,

+ .class_init = aspeed_soc_ast2600_class_init,

+ },

};

-static void aspeed_soc_register_types(void)

-{

- type_register_static(&aspeed_soc_ast2600_type_info);

-};

-

-type_init(aspeed_soc_register_types)

+DEFINE_TYPES(aspeed_soc_ast2600_types)

2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

hw/arm/aspeed_soc_common.c | 11 +++++++++++

1 file changed, 11 insertions(+)

diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c

--- a/hw/arm/aspeed_soc_common.c

+++ b/hw/arm/aspeed_soc_common.c

@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,

sysbus_mmio_get_region(dev, 0), -1000);

+static void aspeed_soc_realize(DeviceState *dev, Error **errp)

+ AspeedSoCState *s = ASPEED_SOC(dev);

+ if (!s->memory) {

+ error_setg(errp, "'memory' link is not set");

+ return;

+ }

static Property aspeed_soc_properties[] = {

DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,

MemoryRegion *),

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)

DeviceClass *dc = DEVICE_CLASS(oc);

+ dc->realize = aspeed_soc_realize;

device_class_set_props(dc, aspeed_soc_properties);

}

2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.

In few commits we'll add more fields, but to keep

review process simple, don't add any yet.

TYPE_ASPEED_SOC is common to various Aspeed SoCs,

define it in aspeed_soc_common.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

include/hw/arm/aspeed_soc.h | 7 +++++

hw/arm/aspeed_soc.c | 61 +++++++++++--------------------------

hw/arm/aspeed_soc_common.c | 29 ++++++++++++++++++

3 files changed, 53 insertions(+), 44 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h

--- a/include/hw/arm/aspeed_soc.h

+++ b/include/hw/arm/aspeed_soc.h

@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {

#define TYPE_ASPEED_SOC "aspeed-soc"

OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)

+struct Aspeed2400SoCState {

+ AspeedSoCState parent;

+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"

+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)

+

struct Aspeed2600SoCState {

AspeedSoCState parent;

};

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c

--- a/hw/arm/aspeed_soc.c

+++ b/hw/arm/aspeed_soc.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)

sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,

aspeed_soc_get_irq(s, ASPEED_DEV_HACE));

}

-static Property aspeed_soc_properties[] = {

- DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,

- MemoryRegion *),

- DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,

- MemoryRegion *),

- DEFINE_PROP_END_OF_LIST(),

-};

-

-static void aspeed_soc_class_init(ObjectClass *oc, void *data)

-{

- DeviceClass *dc = DEVICE_CLASS(oc);

-

- device_class_set_props(dc, aspeed_soc_properties);

-}

-

-static const TypeInfo aspeed_soc_type_info = {

- .name = TYPE_ASPEED_SOC,

- .parent = TYPE_DEVICE,

- .instance_size = sizeof(AspeedSoCState),

- .class_size = sizeof(AspeedSoCClass),

- .class_init = aspeed_soc_class_init,

- .abstract = true,

-};

static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)

{

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)

sc->get_irq = aspeed_soc_ast2400_get_irq;

}

-static const TypeInfo aspeed_soc_ast2400_type_info = {

- .name = "ast2400-a1",

- .parent = TYPE_ASPEED_SOC,

- .instance_init = aspeed_ast2400_soc_init,

- .instance_size = sizeof(AspeedSoCState),

- .class_init = aspeed_soc_ast2400_class_init,

-};

-

static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)

{

AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)

sc->get_irq = aspeed_soc_ast2400_get_irq;

}

-static const TypeInfo aspeed_soc_ast2500_type_info = {

- .name = "ast2500-a1",

- .parent = TYPE_ASPEED_SOC,

- .instance_init = aspeed_ast2400_soc_init,

- .instance_size = sizeof(AspeedSoCState),

- .class_init = aspeed_soc_ast2500_class_init,

-};

-static void aspeed_soc_register_types(void)

-{

- type_register_static(&aspeed_soc_type_info);

- type_register_static(&aspeed_soc_ast2400_type_info);

- type_register_static(&aspeed_soc_ast2500_type_info);

+static const TypeInfo aspeed_soc_ast2400_types[] = {

+ {

+ .name = TYPE_ASPEED2400_SOC,

+ .parent = TYPE_ASPEED_SOC,

+ .instance_init = aspeed_ast2400_soc_init,

+ .instance_size = sizeof(Aspeed2400SoCState),

+ .abstract = true,

+ }, {

+ .name = "ast2400-a1",