[PULL 00/24] target-arm queue
[PULL 00/35] target-arm queue
1
Hi; here's a queue of arm patches (plus a few elf2dmp changes);
1
The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
2
mostly these are minor cleanups and bugfixes.
3
2
4
thanks
3
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
5
-- PMM
6
7
The following changes since commit deaca3fd30d3a8829160f8d3705d65ad83176800:
8
9
Merge tag 'pull-vfio-20231018' of https://github.com/legoater/qemu into staging (2023-10-18 06:21:15 -0400)
10
4
11
are available in the Git repository at:
5
are available in the Git repository at:
12
6
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231019
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
14
8
15
for you to fetch changes up to 2a052b4ee01b3c413cef2ef49cb780cde17d4ba1:
9
for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
16
10
17
contrib/elf2dmp: Use g_malloc(), g_new() and g_free() (2023-10-19 14:32:13 +0100)
11
docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
22
* hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot'
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
23
* xlnx devices: remove deprecated device reset
17
* Fix some errors in SVE/SME handling of MTE tags
24
* xlnx-bbram: hw/nvram: Use dot in device type name
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
25
* elf2dmp: fix coverity issues
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
26
* elf2dmp: convert to g_malloc, g_new and g_free
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
27
* target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
28
* hw/arm: refactor virt PPI logic
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
29
* arm/kvm: convert to kvm_set_one_reg, kvm_get_one_reg
23
* Don't assert on vmload/vmsave of M-profile CPUs
30
* target/arm: Permit T32 LDM with single register
24
* hw/arm/smmuv3: add support for stage 1 access fault
31
* smmuv3: Advertise SMMUv3.1-XNX
25
* hw/arm/stellaris: QOM cleanups
32
* target/arm: Implement FEAT_HPMN0
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
33
* Remove some unnecessary include lines
27
* Improve Cortex_R52 IMPDEF sysreg modelling
34
* target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
28
* Allow access to SPSR_hyp from hyp mode
35
* hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
29
* New board model mps3-an536 (Cortex-R52)
36
30
37
----------------------------------------------------------------
31
----------------------------------------------------------------
38
Chris Rauer (1):
32
Luc Michel (1):
39
hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
33
hw/arm/smmuv3: add support for stage 1 access fault
40
34
41
Cornelia Huck (2):
35
Nabih Estefan (1):
42
arm/kvm: convert to kvm_set_one_reg
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
43
arm/kvm: convert to kvm_get_one_reg
44
37
45
Leif Lindholm (3):
38
Peter Maydell (22):
46
{include/}hw/arm: refactor virt PPI logic
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
47
include/hw/arm: move BSA definitions to bsa.h
40
hw/block/tc58128: Don't emit deprecation warning under qtest
48
hw/arm/sbsa-ref: use bsa.h for PPI definitions
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
44
tests/qtest/bios-tables-tests: Update virt golden reference
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
49
61
50
Michal Orzel (1):
62
Philippe Mathieu-Daudé (5):
51
target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
66
hw/arm/stellaris: Add missing QOM 'machine' parent
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
52
68
53
Peter Maydell (8):
69
Richard Henderson (6):
54
target/arm: Permit T32 LDM with single register
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
55
hw/arm/smmuv3: Update ID register bit field definitions
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
56
hw/arm/smmuv3: Sort ID register setting into field order
72
target/arm: Adjust and validate mtedesc sizem1
57
hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
73
target/arm: Split out make_svemte_desc
58
target/arm: Implement FEAT_HPMN0
74
target/arm: Handle mte in do_ldrq, do_ldro
59
target/arm/kvm64.c: Remove unused include
75
target/arm: Fix SVE/SME gross MTE suppression checks
60
target/arm/common-semi-target.h: Remove unnecessary boot.h include
61
target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
62
76
63
Philippe Mathieu-Daudé (1):
77
MAINTAINERS | 3 +-
64
hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'
78
docs/system/arm/mps2.rst | 37 +-
79
configs/devices/arm-softmmu/default.mak | 1 +
80
hw/arm/smmuv3-internal.h | 1 +
81
include/hw/arm/smmu-common.h | 1 +
82
include/hw/arm/virt.h | 2 +
83
include/hw/misc/mps2-scc.h | 1 +
84
linux-user/aarch64/target_prctl.h | 29 +-
85
target/arm/internals.h | 2 +-
86
target/arm/tcg/translate-a64.h | 2 +
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
88
hw/arm/npcm7xx.c | 1 +
89
hw/arm/smmu-common.c | 11 +
90
hw/arm/smmuv3.c | 1 +
91
hw/arm/stellaris.c | 47 ++-
92
hw/arm/virt-acpi-build.c | 20 +-
93
hw/arm/virt.c | 60 ++-
94
hw/arm/xilinx_zynq.c | 2 +
95
hw/block/tc58128.c | 4 +-
96
hw/misc/mps2-scc.c | 138 ++++++-
97
hw/pci-host/raven.c | 1 +
98
target/arm/helper.c | 14 +-
99
target/arm/tcg/cpu32.c | 109 ++++++
100
target/arm/tcg/op_helper.c | 43 ++-
101
target/arm/tcg/sme_helper.c | 8 +-
102
target/arm/tcg/sve_helper.c | 12 +-
103
target/arm/tcg/translate-sme.c | 15 +-
104
target/arm/tcg/translate-sve.c | 83 +++--
105
target/arm/tcg/translate.c | 19 +-
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
107
tests/qtest/npcm_gmac-test.c | 84 +----
108
hw/arm/Kconfig | 5 +
109
hw/arm/meson.build | 1 +
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
112
tests/qtest/meson.build | 4 +-
113
36 files changed, 1184 insertions(+), 222 deletions(-)
114
create mode 100644 hw/arm/mps3r.c
65
115
66
Suraj Shirvankar (1):
67
contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
68
69
Thomas Huth (1):
70
hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
71
72
Tong Ho (4):
73
xlnx-bbram: hw/nvram: Remove deprecated device reset
74
xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
75
xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
76
xlnx-bbram: hw/nvram: Use dot in device type name
77
78
Viktor Prutyanov (2):
79
elf2dmp: limit print length for sign_rsds
80
elf2dmp: check array bounds in pdb_get_file_size
81
82
MAINTAINERS | 2 +-
83
docs/system/arm/emulation.rst | 1 +
84
hw/arm/smmuv3-internal.h | 38 ++++++++
85
include/hw/arm/bsa.h | 35 +++++++
86
include/hw/arm/exynos4210.h | 2 +-
87
include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0
88
include/hw/arm/virt.h | 12 +--
89
include/hw/nvram/xlnx-bbram.h | 2 +-
90
target/arm/common-semi-target.h | 4 +-
91
target/arm/cpu-qom.h | 2 -
92
target/arm/cpu.h | 22 +++++
93
contrib/elf2dmp/addrspace.c | 7 +-
94
contrib/elf2dmp/main.c | 11 +--
95
contrib/elf2dmp/pdb.c | 32 ++++---
96
contrib/elf2dmp/qemu_elf.c | 7 +-
97
hw/arm/boot.c | 95 +++++--------------
98
hw/arm/sbsa-ref.c | 21 ++---
99
hw/arm/smmuv3.c | 8 +-
100
hw/arm/virt-acpi-build.c | 12 +--
101
hw/arm/virt.c | 24 +++--
102
hw/misc/bcm2835_property.c | 2 +-
103
hw/nvram/xlnx-bbram.c | 8 +-
104
hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +-
105
hw/nvram/xlnx-zynqmp-efuse.c | 8 +-
106
hw/timer/npcm7xx_timer.c | 3 +
107
target/arm/arm-powerctl.c | 53 +----------
108
target/arm/cpu.c | 95 +++++++++++++++++++
109
target/arm/helper.c | 19 +---
110
target/arm/kvm.c | 28 ++----
111
target/arm/kvm64.c | 124 +++++++------------------
112
target/arm/tcg/cpu32.c | 4 +
113
target/arm/tcg/cpu64.c | 1 +
114
target/arm/tcg/translate.c | 37 +++++---
115
33 files changed, 368 insertions(+), 359 deletions(-)
116
create mode 100644 include/hw/arm/bsa.h
117
rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)
118
diff view generated by jsdifflib
[PULL 13/24] arm/kvm: convert to kvm_set_one_reg
[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
1
From: Cornelia Huck <cohuck@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
We can neaten the code by switching to the kvm_set_one_reg function.
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
connect FIQ output of the GIC CPU interfaces to the CPU.
4
5
5
Reviewed-by: Gavin Shan <gshan@redhat.com>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20231010142453.224369-2-cohuck@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/kvm.c | 13 +++------
11
hw/arm/xilinx_zynq.c | 2 ++
13
target/arm/kvm64.c | 66 +++++++++++++---------------------------------
12
1 file changed, 2 insertions(+)
14
2 files changed, 21 insertions(+), 58 deletions(-)
15
13
16
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm.c
16
--- a/hw/arm/xilinx_zynq.c
19
+++ b/target/arm/kvm.c
17
+++ b/hw/arm/xilinx_zynq.c
20
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
21
bool ok = true;
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
22
20
sysbus_connect_irq(busdev, 0,
23
for (i = 0; i < cpu->cpreg_array_len; i++) {
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
24
- struct kvm_one_reg r;
22
+ sysbus_connect_irq(busdev, 1,
25
uint64_t regidx = cpu->cpreg_indexes[i];
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
26
uint32_t v32;
24
27
int ret;
25
for (n = 0; n < 64; n++) {
28
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
26
pic[n] = qdev_get_gpio_in(dev, n);
29
continue;
30
}
31
32
- r.id = regidx;
33
switch (regidx & KVM_REG_SIZE_MASK) {
34
case KVM_REG_SIZE_U32:
35
v32 = cpu->cpreg_values[i];
36
- r.addr = (uintptr_t)&v32;
37
+ ret = kvm_set_one_reg(cs, regidx, &v32);
38
break;
39
case KVM_REG_SIZE_U64:
40
- r.addr = (uintptr_t)(cpu->cpreg_values + i);
41
+ ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i);
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
47
if (ret) {
48
/* We might fail for "unknown register" and also for
49
* "you tried to set a register which is constant with
50
@@ -XXX,XX +XXX,XX @@ void kvm_arm_get_virtual_time(CPUState *cs)
51
void kvm_arm_put_virtual_time(CPUState *cs)
52
{
53
ARMCPU *cpu = ARM_CPU(cs);
54
- struct kvm_one_reg reg = {
55
- .id = KVM_REG_ARM_TIMER_CNT,
56
- .addr = (uintptr_t)&cpu->kvm_vtime,
57
- };
58
int ret;
59
60
if (!cpu->kvm_vtime_dirty) {
61
return;
62
}
63
64
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
65
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
66
if (ret) {
67
error_report("Failed to set KVM_REG_ARM_TIMER_CNT");
68
abort();
69
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/kvm64.c
72
+++ b/target/arm/kvm64.c
73
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_sve_set_vls(CPUState *cs)
74
{
75
ARMCPU *cpu = ARM_CPU(cs);
76
uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };
77
- struct kvm_one_reg reg = {
78
- .id = KVM_REG_ARM64_SVE_VLS,
79
- .addr = (uint64_t)&vls[0],
80
- };
81
82
assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
83
84
- return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
85
+ return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]);
86
}
87
88
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
89
@@ -XXX,XX +XXX,XX @@ static void kvm_inject_arm_sea(CPUState *c)
90
static int kvm_arch_put_fpsimd(CPUState *cs)
91
{
92
CPUARMState *env = &ARM_CPU(cs)->env;
93
- struct kvm_one_reg reg;
94
int i, ret;
95
96
for (i = 0; i < 32; i++) {
97
uint64_t *q = aa64_vfp_qreg(env, i);
98
#if HOST_BIG_ENDIAN
99
uint64_t fp_val[2] = { q[1], q[0] };
100
- reg.addr = (uintptr_t)fp_val;
101
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]),
102
+ fp_val);
103
#else
104
- reg.addr = (uintptr_t)q;
105
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
106
#endif
107
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
108
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
109
if (ret) {
110
return ret;
111
}
112
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
113
CPUARMState *env = &cpu->env;
114
uint64_t tmp[ARM_MAX_VQ * 2];
115
uint64_t *r;
116
- struct kvm_one_reg reg;
117
int n, ret;
118
119
for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
120
r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
121
- reg.addr = (uintptr_t)r;
122
- reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
123
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
124
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
125
if (ret) {
126
return ret;
127
}
128
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
129
for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
130
r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
131
DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
132
- reg.addr = (uintptr_t)r;
133
- reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
134
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
135
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
136
if (ret) {
137
return ret;
138
}
139
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
140
141
r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
142
DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
143
- reg.addr = (uintptr_t)r;
144
- reg.id = KVM_REG_ARM64_SVE_FFR(0);
145
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
146
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
147
if (ret) {
148
return ret;
149
}
150
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
151
152
int kvm_arch_put_registers(CPUState *cs, int level)
153
{
154
- struct kvm_one_reg reg;
155
uint64_t val;
156
uint32_t fpr;
157
int i, ret;
158
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
159
}
160
161
for (i = 0; i < 31; i++) {
162
- reg.id = AARCH64_CORE_REG(regs.regs[i]);
163
- reg.addr = (uintptr_t) &env->xregs[i];
164
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
165
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
166
+ &env->xregs[i]);
167
if (ret) {
168
return ret;
169
}
170
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
171
*/
172
aarch64_save_sp(env, 1);
173
174
- reg.id = AARCH64_CORE_REG(regs.sp);
175
- reg.addr = (uintptr_t) &env->sp_el[0];
176
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
177
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
178
if (ret) {
179
return ret;
180
}
181
182
- reg.id = AARCH64_CORE_REG(sp_el1);
183
- reg.addr = (uintptr_t) &env->sp_el[1];
184
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
185
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
186
if (ret) {
187
return ret;
188
}
189
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
190
} else {
191
val = cpsr_read(env);
192
}
193
- reg.id = AARCH64_CORE_REG(regs.pstate);
194
- reg.addr = (uintptr_t) &val;
195
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
196
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
197
if (ret) {
198
return ret;
199
}
200
201
- reg.id = AARCH64_CORE_REG(regs.pc);
202
- reg.addr = (uintptr_t) &env->pc;
203
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
204
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
205
if (ret) {
206
return ret;
207
}
208
209
- reg.id = AARCH64_CORE_REG(elr_el1);
210
- reg.addr = (uintptr_t) &env->elr_el[1];
211
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
212
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
213
if (ret) {
214
return ret;
215
}
216
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
217
218
/* KVM 0-4 map to QEMU banks 1-5 */
219
for (i = 0; i < KVM_NR_SPSR; i++) {
220
- reg.id = AARCH64_CORE_REG(spsr[i]);
221
- reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
222
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
223
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
224
+ &env->banked_spsr[i + 1]);
225
if (ret) {
226
return ret;
227
}
228
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
229
return ret;
230
}
231
232
- reg.addr = (uintptr_t)(&fpr);
233
fpr = vfp_get_fpsr(env);
234
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
235
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
236
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
237
if (ret) {
238
return ret;
239
}
240
241
- reg.addr = (uintptr_t)(&fpr);
242
fpr = vfp_get_fpcr(env);
243
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
244
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
245
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
246
if (ret) {
247
return ret;
248
}
249
--
27
--
250
2.34.1
28
2.34.1
251
29
252
30
diff view generated by jsdifflib
[PULL 23/24] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
1
From: Chris Rauer <crauer@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The counter register is only 24-bits and counts down. If the timer is
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
running but the qtimer to reset it hasn't fired off yet, there is a chance
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
the regster read can return an invalid result.
5
choose SYNC as the default.
6
6
7
Signed-off-by: Chris Rauer <crauer@google.com>
7
Cc: qemu-stable@nongnu.org
8
Message-id: 20230922181411.2697135-1-crauer@google.com
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
hw/timer/npcm7xx_timer.c | 3 +++
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
13
1 file changed, 3 insertions(+)
15
1 file changed, 17 insertions(+), 12 deletions(-)
14
16
15
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/timer/npcm7xx_timer.c
19
--- a/linux-user/aarch64/target_prctl.h
18
+++ b/hw/timer/npcm7xx_timer.c
20
+++ b/linux-user/aarch64/target_prctl.h
19
@@ -XXX,XX +XXX,XX @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
20
/* Convert a time interval in nanoseconds to a timer cycle count. */
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
21
static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
23
22
{
24
if (cpu_isar_feature(aa64_mte, cpu)) {
23
+ if (ns < 0) {
25
- switch (arg2 & PR_MTE_TCF_MASK) {
24
+ return 0;
26
- case PR_MTE_TCF_NONE:
25
+ }
27
- case PR_MTE_TCF_SYNC:
26
return clock_ns_to_ticks(t->ctrl->clock, ns) /
28
- case PR_MTE_TCF_ASYNC:
27
npcm7xx_tcsr_prescaler(t->tcsr);
29
- break;
28
}
30
- default:
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
29
--
60
--
30
2.34.1
61
2.34.1
diff view generated by jsdifflib
[PULL 12/24] hw/arm/sbsa-ref: use bsa.h for PPI definitions
[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use the private peripheral interrupt definitions from bsa.h instead of
3
The field is encoded as [0-3], which is convenient for
4
defining them locally. Refactor to use the INTIDs defined there instead
4
indexing our array of function pointers, but the true
5
of the PPI# used previously.
5
value is [1-4]. Adjust before calling do_mem_zpa.
6
6
7
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
7
Add an assert, and move the comment re passing ZT to
8
Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com
8
the helper back next to the relevant code.
9
10
Cc: qemu-stable@nongnu.org
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
hw/arm/sbsa-ref.c | 21 +++++++++------------
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
13
1 file changed, 9 insertions(+), 12 deletions(-)
19
1 file changed, 8 insertions(+), 8 deletions(-)
14
20
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/sbsa-ref.c
23
--- a/target/arm/tcg/translate-sve.c
18
+++ b/hw/arm/sbsa-ref.c
24
+++ b/target/arm/tcg/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
20
* ARM SBSA Reference Platform emulation
26
TCGv_ptr t_pg;
21
*
27
int desc = 0;
22
* Copyright (c) 2018 Linaro Limited
28
23
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
29
- /*
24
* Written by Hongbo Zhang <hongbo.zhang@linaro.org>
30
- * For e.g. LD4, there are not enough arguments to pass all 4
25
*
31
- * registers as pointers, so encode the regno into the data field.
26
* This program is free software; you can redistribute it and/or modify it
32
- * For consistency, do this even for LD1.
27
@@ -XXX,XX +XXX,XX @@
33
- */
28
#include "exec/hwaddr.h"
34
+ assert(mte_n >= 1 && mte_n <= 4);
29
#include "kvm_arm.h"
35
if (s->mte_active[0]) {
30
#include "hw/arm/boot.h"
36
int msz = dtype_msz(dtype);
31
+#include "hw/arm/bsa.h"
37
32
#include "hw/arm/fdt.h"
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
33
#include "hw/arm/smmuv3.h"
39
addr = clean_data_tbi(s, addr);
34
#include "hw/block/flash.h"
40
}
35
@@ -XXX,XX +XXX,XX @@
41
36
#define NUM_SMMU_IRQS 4
42
+ /*
37
#define NUM_SATA_PORTS 6
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
38
44
+ * registers as pointers, so encode the regno into the data field.
39
-#define VIRTUAL_PMU_IRQ 7
45
+ * For consistency, do this even for LD1.
40
-#define ARCH_GIC_MAINT_IRQ 9
46
+ */
41
-#define ARCH_TIMER_VIRT_IRQ 11
47
desc = simd_desc(vsz, vsz, zt | desc);
42
-#define ARCH_TIMER_S_EL1_IRQ 13
48
t_pg = tcg_temp_new_ptr();
43
-#define ARCH_TIMER_NS_EL1_IRQ 14
49
44
-#define ARCH_TIMER_NS_EL2_IRQ 10
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
45
-#define ARCH_TIMER_NS_EL2_VIRT_IRQ 12
51
* accessible via the instruction encoding.
46
-
47
enum {
48
SBSA_FLASH,
49
SBSA_MEM,
50
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
51
*/
52
*/
52
for (i = 0; i < smp_cpus; i++) {
53
assert(fn != NULL);
53
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
54
- int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
55
+ int intidbase = NUM_IRQS + i * GIC_INTERNAL;
56
}
56
int irq;
57
57
/*
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
58
* Mapping from the output timer irq lines from the CPU to the
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
59
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
60
if (nreg == 0) {
60
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
61
/* ST1 */
61
qdev_connect_gpio_out(cpudev, irq,
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
62
qdev_get_gpio_in(sms->gic,
63
- nreg = 1;
63
- ppibase + timer_irq[irq]));
64
} else {
64
+ intidbase + timer_irq[irq]));
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
65
}
66
assert(msz == esz);
66
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
67
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
68
}
68
- qdev_get_gpio_in(sms->gic, ppibase
69
assert(fn != NULL);
69
+ qdev_get_gpio_in(sms->gic,
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
70
+ intidbase
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
71
+ ARCH_GIC_MAINT_IRQ));
72
}
72
+
73
73
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
74
- qdev_get_gpio_in(sms->gic, ppibase
75
+ qdev_get_gpio_in(sms->gic,
76
+ intidbase
77
+ VIRTUAL_PMU_IRQ));
78
79
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
80
--
75
--
81
2.34.1
76
2.34.1
diff view generated by jsdifflib
[PULL 06/24] xlnx-bbram: hw/nvram: Use dot in device type name
[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
1
From: Tong Ho <tong.ho@amd.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This replaces the comma (,) to dot (.) in the device type name
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
4
so the name can be used with the 'driver=' command line option.
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
5
7
6
Signed-off-by: Tong Ho <tong.ho@amd.com>
8
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20231003052139.199665-1-tong.ho@amd.com
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
include/hw/nvram/xlnx-bbram.h | 2 +-
15
target/arm/internals.h | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
16
target/arm/tcg/translate-sve.c | 7 ++++---
17
2 files changed, 5 insertions(+), 4 deletions(-)
13
18
14
diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/nvram/xlnx-bbram.h
21
--- a/target/arm/internals.h
17
+++ b/include/hw/nvram/xlnx-bbram.h
22
+++ b/target/arm/internals.h
18
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
19
24
FIELD(MTEDESC, TCMA, 6, 2)
20
#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
25
FIELD(MTEDESC, WRITE, 8, 1)
21
26
FIELD(MTEDESC, ALIGN, 9, 3)
22
-#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
23
+#define TYPE_XLNX_BBRAM "xlnx.bbram-ctrl"
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
24
OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
29
25
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
26
struct XlnxBBRam {
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/translate-sve.c
35
+++ b/target/arm/tcg/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
{
38
unsigned vsz = vec_full_reg_size(s);
39
TCGv_ptr t_pg;
40
+ uint32_t sizem1;
41
int desc = 0;
42
43
assert(mte_n >= 1 && mte_n <= 4);
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
46
if (s->mte_active[0]) {
47
- int msz = dtype_msz(dtype);
48
-
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
55
desc <<= SVE_MTEDESC_SHIFT;
56
} else {
57
addr = clean_data_tbi(s, addr);
27
--
58
--
28
2.34.1
59
2.34.1
diff view generated by jsdifflib
[PULL 11/24] include/hw/arm: move BSA definitions to bsa.h
[PULL 05/35] target/arm: Split out make_svemte_desc
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
virt.h defines a number of IRQs that are ultimately described by Arm's
3
Share code that creates mtedesc and embeds within simd_desc.
4
Base System Architecture specification. Move these to a dedicated header
5
so that they can be reused by other platforms that do the same.
6
Include that header from virt.h to minimise churn.
7
4
8
While we're moving the definitions, sort them into numerical order,
5
Cc: qemu-stable@nongnu.org
9
and add the ARCH_TIMER_NS_EL2_VIRT_IRQ definition used by sbsa-ref
10
and which will eventually be needed by virt also.
11
12
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
13
Message-id: 20230919090229.188092-3-quic_llindhol@quicinc.com
14
[PMM: Remove unused PPI_TO_INTID macro; sort numerically;
15
add ARCH_TIMER_NS_EL2_VIRT_IRQ]
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/arm/bsa.h | 35 +++++++++++++++++++++++++++++++++++
12
target/arm/tcg/translate-a64.h | 2 ++
20
include/hw/arm/virt.h | 12 +-----------
13
target/arm/tcg/translate-sme.c | 15 +++--------
21
2 files changed, 36 insertions(+), 11 deletions(-)
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
22
create mode 100644 include/hw/arm/bsa.h
15
3 files changed, 31 insertions(+), 33 deletions(-)
23
16
24
diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
25
new file mode 100644
18
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX
19
--- a/target/arm/tcg/translate-a64.h
27
--- /dev/null
20
+++ b/target/arm/tcg/translate-a64.h
28
+++ b/include/hw/arm/bsa.h
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
29
@@ -XXX,XX +XXX,XX @@
22
bool sve_access_check(DisasContext *s);
30
+/*
23
bool sme_enabled_check(DisasContext *s);
31
+ * Common definitions for Arm Base System Architecture (BSA) platforms.
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
32
+ *
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
33
+ * Copyright (c) 2015 Linaro Limited
26
+ uint32_t msz, bool is_write, uint32_t data);
34
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
27
35
+ *
28
/* This function corresponds to CheckStreamingSVEEnabled. */
36
+ * This program is free software; you can redistribute it and/or modify it
29
static inline bool sme_sm_enabled_check(DisasContext *s)
37
+ * under the terms and conditions of the GNU General Public License,
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
38
+ * version 2 or later, as published by the Free Software Foundation.
31
index XXXXXXX..XXXXXXX 100644
39
+ *
32
--- a/target/arm/tcg/translate-sme.c
40
+ * This program is distributed in the hope it will be useful, but WITHOUT
33
+++ b/target/arm/tcg/translate-sme.c
41
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
42
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
35
43
+ * more details.
36
TCGv_ptr t_za, t_pg;
44
+ *
37
TCGv_i64 addr;
45
+ * You should have received a copy of the GNU General Public License along with
38
- int svl, desc = 0;
46
+ * this program. If not, see <http://www.gnu.org/licenses/>.
39
+ uint32_t desc;
47
+ *
40
bool be = s->be_data == MO_BE;
48
+ */
41
bool mte = s->mte_active[0];
42
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
46
47
- if (mte) {
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
49
+
60
+
50
+#ifndef QEMU_ARM_BSA_H
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
51
+#define QEMU_ARM_BSA_H
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/tcg/translate-sve.c
68
+++ b/target/arm/tcg/translate-sve.c
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
70
3, 2, 1, 3
71
};
72
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
74
- int dtype, uint32_t mte_n, bool is_write,
75
- gen_helper_gvec_mem *fn)
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
77
+ uint32_t msz, bool is_write, uint32_t data)
78
{
79
- unsigned vsz = vec_full_reg_size(s);
80
- TCGv_ptr t_pg;
81
uint32_t sizem1;
82
- int desc = 0;
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
52
+
92
+
53
+/* These are architectural INTID values */
93
if (s->mte_active[0]) {
54
+#define VIRTUAL_PMU_IRQ 23
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
55
+#define ARCH_GIC_MAINT_IRQ 25
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
56
+#define ARCH_TIMER_NS_EL2_IRQ 26
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
57
+#define ARCH_TIMER_VIRT_IRQ 27
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
58
+#define ARCH_TIMER_NS_EL2_VIRT_IRQ 28
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
59
+#define ARCH_TIMER_S_EL1_IRQ 29
99
desc <<= SVE_MTEDESC_SHIFT;
60
+#define ARCH_TIMER_NS_EL1_IRQ 30
100
- } else {
101
+ }
102
+ return simd_desc(vsz, vsz, desc | data);
103
+}
61
+
104
+
62
+#define INTID_TO_PPI(irq) ((irq) - 16)
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
63
+
111
+
64
+#endif /* QEMU_ARM_BSA_H */
112
+ if (!s->mte_active[0]) {
65
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
113
addr = clean_data_tbi(s, addr);
66
index XXXXXXX..XXXXXXX 100644
114
}
67
--- a/include/hw/arm/virt.h
115
68
+++ b/include/hw/arm/virt.h
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
69
@@ -XXX,XX +XXX,XX @@
117
* registers as pointers, so encode the regno into the data field.
70
#include "qemu/notify.h"
118
* For consistency, do this even for LD1.
71
#include "hw/boards.h"
119
*/
72
#include "hw/arm/boot.h"
120
- desc = simd_desc(vsz, vsz, zt | desc);
73
+#include "hw/arm/bsa.h"
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
74
#include "hw/block/flash.h"
122
+ dtype_msz(dtype), is_write, zt);
75
#include "sysemu/kvm.h"
123
t_pg = tcg_temp_new_ptr();
76
#include "hw/intc/arm_gicv3_common.h"
124
77
@@ -XXX,XX +XXX,XX @@
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
78
#define NUM_VIRTIO_TRANSPORTS 32
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
79
#define NUM_SMMU_IRQS 4
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
80
128
gen_helper_gvec_mem_scatter *fn)
81
-#define ARCH_GIC_MAINT_IRQ 25
129
{
130
- unsigned vsz = vec_full_reg_size(s);
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
134
- int desc = 0;
82
-
135
-
83
-#define ARCH_TIMER_VIRT_IRQ 27
136
- if (s->mte_active[0]) {
84
-#define ARCH_TIMER_S_EL1_IRQ 29
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
85
-#define ARCH_TIMER_NS_EL1_IRQ 30
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
86
-#define ARCH_TIMER_NS_EL2_IRQ 26
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
87
-
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
88
-#define VIRTUAL_PMU_IRQ 23
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
89
-
142
- desc <<= SVE_MTEDESC_SHIFT;
90
-#define INTID_TO_PPI(irq) ((irq) - 16)
143
- }
91
-
144
- desc = simd_desc(vsz, vsz, desc | scale);
92
/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
145
+ uint32_t desc;
93
#define PVTIME_SIZE_PER_CPU 64
146
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
150
+
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
153
}
94
154
95
--
155
--
96
2.34.1
156
2.34.1
diff view generated by jsdifflib
[PULL 07/24] elf2dmp: limit print length for sign_rsds
[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
1
From: Viktor Prutyanov <viktor@daynix.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
String sign_rsds isn't terminated, so the print length must be limited.
3
These functions "use the standard load helpers", but
4
fail to clean_data_tbi or populate mtedesc.
4
5
5
Fixes: Coverity CID 1521598
6
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230930235317.11469-2-viktor@daynix.com
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
contrib/elf2dmp/main.c | 2 +-
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
12
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 13 insertions(+), 2 deletions(-)
13
15
14
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/contrib/elf2dmp/main.c
18
--- a/target/arm/tcg/translate-sve.c
17
+++ b/contrib/elf2dmp/main.c
19
+++ b/target/arm/tcg/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool pe_check_pdb_name(uint64_t base, void *start_addr,
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
21
unsigned vsz = vec_full_reg_size(s);
22
TCGv_ptr t_pg;
23
int poff;
24
+ uint32_t desc;
25
26
/* Load the first quadword using the normal predicated load helpers. */
27
+ if (!s->mte_active[0]) {
28
+ addr = clean_data_tbi(s, addr);
29
+ }
30
+
31
poff = pred_full_reg_offset(s, pg);
32
if (vsz > 16) {
33
/*
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
35
36
gen_helper_gvec_mem *fn
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
41
42
/* Replicate that first quadword. */
43
if (vsz > 16) {
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
45
unsigned vsz_r32;
46
TCGv_ptr t_pg;
47
int poff, doff;
48
+ uint32_t desc;
49
50
if (vsz < 32) {
51
/*
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
19
}
53
}
20
54
21
if (memcmp(&rsds->Signature, sign_rsds, sizeof(sign_rsds))) {
55
/* Load the first octaword using the normal predicated load helpers. */
22
- eprintf("CodeView signature is \'%.4s\', \'%s\' expected\n",
56
+ if (!s->mte_active[0]) {
23
+ eprintf("CodeView signature is \'%.4s\', \'%.4s\' expected\n",
57
+ addr = clean_data_tbi(s, addr);
24
rsds->Signature, sign_rsds);
58
+ }
25
return false;
59
26
}
60
poff = pred_full_reg_offset(s, pg);
61
if (vsz > 32) {
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
63
64
gen_helper_gvec_mem *fn
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
69
70
/*
71
* Replicate that first octaword.
27
--
72
--
28
2.34.1
73
2.34.1
diff view generated by jsdifflib
[PULL 24/24] contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
1
From: Suraj Shirvankar <surajshirvankar@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
QEMU coding style uses the glib memory allocation APIs, not
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
the raw libc malloc/free. Switch the allocation and free
5
calls in elf2dmp to use these functions (dropping the now-unneeded
6
checks for failure).
7
4
8
Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>
5
Cc: qemu-stable@nongnu.org
9
Message-id: 169753938460.23804.11418813007617535750-1@git.sr.ht
10
[PMM: also remove NULL checks from g_malloc() calls;
11
beef up commit message]
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
contrib/elf2dmp/addrspace.c | 7 ++-----
12
target/arm/tcg/sme_helper.c | 8 ++++----
16
contrib/elf2dmp/main.c | 9 +++------
13
target/arm/tcg/sve_helper.c | 12 ++++++------
17
contrib/elf2dmp/pdb.c | 19 ++++++++-----------
14
2 files changed, 10 insertions(+), 10 deletions(-)
18
contrib/elf2dmp/qemu_elf.c | 7 ++-----
19
4 files changed, 15 insertions(+), 27 deletions(-)
20
15
21
diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
22
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
23
--- a/contrib/elf2dmp/addrspace.c
18
--- a/target/arm/tcg/sme_helper.c
24
+++ b/contrib/elf2dmp/addrspace.c
19
+++ b/target/arm/tcg/sme_helper.c
25
@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
26
}
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
22
23
/* Perform gross MTE suppression early. */
24
- if (!tbi_check(desc, bit55) ||
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
26
+ if (!tbi_check(mtedesc, bit55) ||
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
28
mtedesc = 0;
27
}
29
}
28
30
29
- ps->block = malloc(sizeof(*ps->block) * ps->block_nr);
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
30
- if (!ps->block) {
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
31
- return 1;
33
32
- }
34
/* Perform gross MTE suppression early. */
33
+ ps->block = g_new(struct pa_block, ps->block_nr);
35
- if (!tbi_check(desc, bit55) ||
34
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
35
for (i = 0; i < phdr_nr; i++) {
37
+ if (!tbi_check(mtedesc, bit55) ||
36
if (phdr[i].p_type == PT_LOAD) {
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
37
@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
39
mtedesc = 0;
38
void pa_space_destroy(struct pa_space *ps)
40
}
39
{
41
40
ps->block_nr = 0;
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
41
- free(ps->block);
42
+ g_free(ps->block);
43
}
44
45
void va_space_set_dtb(struct va_space *vs, uint64_t dtb)
46
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
47
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
48
--- a/contrib/elf2dmp/main.c
44
--- a/target/arm/tcg/sve_helper.c
49
+++ b/contrib/elf2dmp/main.c
45
+++ b/target/arm/tcg/sve_helper.c
50
@@ -XXX,XX +XXX,XX @@ static KDDEBUGGER_DATA64 *get_kdbg(uint64_t KernBase, struct pdb_reader *pdb,
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
51
}
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
48
49
/* Perform gross MTE suppression early. */
50
- if (!tbi_check(desc, bit55) ||
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
52
+ if (!tbi_check(mtedesc, bit55) ||
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
54
mtedesc = 0;
52
}
55
}
53
56
54
- kdbg = malloc(kdbg_hdr.Size);
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
55
- if (!kdbg) {
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
56
- return NULL;
59
57
- }
60
/* Perform gross MTE suppression early. */
58
+ kdbg = g_malloc(kdbg_hdr.Size);
61
- if (!tbi_check(desc, bit55) ||
59
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
60
if (va_space_rw(vs, KdDebuggerDataBlock, kdbg, kdbg_hdr.Size, 0)) {
63
+ if (!tbi_check(mtedesc, bit55) ||
61
eprintf("Failed to extract entire KDBG\n");
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
62
- free(kdbg);
65
mtedesc = 0;
63
+ g_free(kdbg);
64
return NULL;
65
}
66
}
66
67
67
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
70
71
/* Perform gross MTE suppression early. */
72
- if (!tbi_check(desc, bit55) ||
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
74
+ if (!tbi_check(mtedesc, bit55) ||
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
76
mtedesc = 0;
68
}
77
}
69
78
70
out_kdbg:
71
- free(kdbg);
72
+ g_free(kdbg);
73
out_pdb:
74
pdb_exit(&pdb);
75
out_pdb_file:
76
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/contrib/elf2dmp/pdb.c
79
+++ b/contrib/elf2dmp/pdb.c
80
@@ -XXX,XX +XXX,XX @@ uint64_t pdb_resolve(uint64_t img_base, struct pdb_reader *r, const char *name)
81
82
static void pdb_reader_ds_exit(struct pdb_reader *r)
83
{
84
- free(r->ds.toc);
85
+ g_free(r->ds.toc);
86
}
87
88
static void pdb_exit_symbols(struct pdb_reader *r)
89
{
90
- free(r->modimage);
91
- free(r->symbols);
92
+ g_free(r->modimage);
93
+ g_free(r->symbols);
94
}
95
96
static void pdb_exit_segments(struct pdb_reader *r)
97
{
98
- free(r->segs);
99
+ g_free(r->segs);
100
}
101
102
static void *pdb_ds_read(const PDB_DS_HEADER *header,
103
@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read(const PDB_DS_HEADER *header,
104
105
nBlocks = (size + header->block_size - 1) / header->block_size;
106
107
- buffer = malloc(nBlocks * header->block_size);
108
- if (!buffer) {
109
- return NULL;
110
- }
111
+ buffer = g_malloc(nBlocks * header->block_size);
112
113
for (i = 0; i < nBlocks; i++) {
114
memcpy(buffer + i * header->block_size, (const char *)header +
115
@@ -XXX,XX +XXX,XX @@ static int pdb_init_symbols(struct pdb_reader *r)
116
return 0;
117
118
out_symbols:
119
- free(symbols);
120
+ g_free(symbols);
121
122
return err;
123
}
124
@@ -XXX,XX +XXX,XX @@ static int pdb_reader_init(struct pdb_reader *r, void *data)
125
out_sym:
126
pdb_exit_symbols(r);
127
out_root:
128
- free(r->ds.root);
129
+ g_free(r->ds.root);
130
out_ds:
131
pdb_reader_ds_exit(r);
132
133
@@ -XXX,XX +XXX,XX @@ static void pdb_reader_exit(struct pdb_reader *r)
134
{
135
pdb_exit_segments(r);
136
pdb_exit_symbols(r);
137
- free(r->ds.root);
138
+ g_free(r->ds.root);
139
pdb_reader_ds_exit(r);
140
}
141
142
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/contrib/elf2dmp/qemu_elf.c
145
+++ b/contrib/elf2dmp/qemu_elf.c
146
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
147
148
printf("%zu CPU states has been found\n", cpu_nr);
149
150
- qe->state = malloc(sizeof(*qe->state) * cpu_nr);
151
- if (!qe->state) {
152
- return 1;
153
- }
154
+ qe->state = g_new(QEMUCPUState*, cpu_nr);
155
156
cpu_nr = 0;
157
158
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
159
160
static void exit_states(QEMU_Elf *qe)
161
{
162
- free(qe->state);
163
+ g_free(qe->state);
164
}
165
166
static bool check_ehdr(QEMU_Elf *qe)
167
--
79
--
168
2.34.1
80
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
which sets .valid.unaligned to indicate that it should support
3
unaligned accesses and which does not also set .impl.unaligned to
4
indicate that its read and write functions can do the unaligned
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
1
10
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
12
with the case of being passed an unaligned address, so we can fix the
13
missing unaligned access support by setting .impl.unaligned in the
14
MemoryRegionOps struct.
15
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
21
---
22
hw/pci-host/raven.c | 1 +
23
1 file changed, 1 insertion(+)
24
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/pci-host/raven.c
28
+++ b/hw/pci-host/raven.c
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
30
.write = raven_io_write,
31
.endianness = DEVICE_LITTLE_ENDIAN,
32
.impl.max_access_size = 4,
33
+ .impl.unaligned = true,
34
.valid.unaligned = true,
35
};
36
37
--
38
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
1
Suppress the deprecation warning when we're running under qtest,
2
to avoid "make check" including warning messages in its output.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
7
---
8
hw/block/tc58128.c | 4 +++-
9
1 file changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/block/tc58128.c
14
+++ b/hw/block/tc58128.c
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
16
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
18
{
19
- warn_report_once("The TC58128 flash device is deprecated");
20
+ if (!qtest_enabled()) {
21
+ warn_report_once("The TC58128 flash device is deprecated");
22
+ }
23
init_dev(&tc58128_devs[0], zone1);
24
init_dev(&tc58128_devs[1], zone2);
25
return sh7750_register_io_device(s, &tc58128);
26
--
27
2.34.1
28
29
diff view generated by jsdifflib
New patch
[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
because we already get the coverage of those tests via qtests_arm,
3
and we don't want to use extra CI minutes testing them twice.
1
4
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
6
that change.
7
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
12
---
13
tests/qtest/meson.build | 1 -
14
1 file changed, 1 deletion(-)
15
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
17
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/qtest/meson.build
19
+++ b/tests/qtest/meson.build
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
22
(config_all_accel.has_key('CONFIG_TCG') and \
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
25
['arm-cpu-features',
26
'numa-test',
27
'boot-serial-test',
28
--
29
2.34.1
30
31
diff view generated by jsdifflib
New patch
[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
[PULL 10/24] {include/}hw/arm: refactor virt PPI logic
[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
3
CPU model, but never wired up its IRQ line to the GIC.
4
As in, PPI0 is INTID16 .. PPI15 is INTID31.
4
5
Arm's Base System Architecture specification (BSA) lists the mandated and
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
recommended private interrupt IDs by INTID, not by PPI index. But current
6
interrupt or not, since it always creates the outbound IRQ line).
7
definitions in virt define them by PPI index, complicating cross
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
referencing.
8
9
9
The DTB binding is documented in the kernel's
10
Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
converting a PPI index to an INTID.
11
and the ACPI table entries are documented in the ACPI specification
12
12
version 6.3 or later.
13
Resolve this by redefining the BSA-allocated PPIs by their INTIDs,
13
14
and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required.
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
15
FADT table rev to show that we might be using 6.3 features.
16
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
16
17
Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
20
---
35
---
21
include/hw/arm/virt.h | 14 +++++++-------
36
include/hw/arm/virt.h | 2 ++
22
hw/arm/virt-acpi-build.c | 12 ++++++------
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
23
hw/arm/virt.c | 24 ++++++++++++++----------
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
24
3 files changed, 27 insertions(+), 23 deletions(-)
39
3 files changed, 67 insertions(+), 15 deletions(-)
25
40
26
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
27
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/virt.h
43
--- a/include/hw/arm/virt.h
29
+++ b/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
30
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
31
#define NUM_VIRTIO_TRANSPORTS 32
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
32
#define NUM_SMMU_IRQS 4
47
bool no_cpu_topology;
33
48
bool no_tcg_lpa2;
34
-#define ARCH_GIC_MAINT_IRQ 9
49
+ bool no_ns_el2_virt_timer_irq;
35
+#define ARCH_GIC_MAINT_IRQ 25
50
};
36
51
37
-#define ARCH_TIMER_VIRT_IRQ 11
52
struct VirtMachineState {
38
-#define ARCH_TIMER_S_EL1_IRQ 13
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
39
-#define ARCH_TIMER_NS_EL1_IRQ 14
54
PCIBus *bus;
40
-#define ARCH_TIMER_NS_EL2_IRQ 10
55
char *oem_id;
41
+#define ARCH_TIMER_VIRT_IRQ 27
56
char *oem_table_id;
42
+#define ARCH_TIMER_S_EL1_IRQ 29
57
+ bool ns_el2_virt_timer_irq;
43
+#define ARCH_TIMER_NS_EL1_IRQ 30
58
};
44
+#define ARCH_TIMER_NS_EL2_IRQ 26
59
45
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
46
-#define VIRTUAL_PMU_IRQ 7
47
+#define VIRTUAL_PMU_IRQ 23
48
49
-#define PPI(irq) ((irq) + 16)
50
+#define INTID_TO_PPI(irq) ((irq) - 16)
51
52
/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
53
#define PVTIME_SIZE_PER_CPU 64
54
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
55
index XXXXXXX..XXXXXXX 100644
62
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/virt-acpi-build.c
63
--- a/hw/arm/virt-acpi-build.c
57
+++ b/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
58
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
59
* The interrupt values are the same with the device tree when adding 16
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
60
*/
78
1 : /* Interrupt is Edge triggered */
61
/* Secure EL1 timer GSIV */
79
0; /* Interrupt is Level triggered */
62
- build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
63
+ build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
64
/* Secure EL1 timer Flags */
82
.oem_table_id = vms->oem_table_id };
65
build_append_int_noprefix(table_data, irqflags, 4);
83
66
/* Non-Secure EL1 timer GSIV */
84
acpi_table_begin(&table, table_data);
67
- build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
68
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
86
build_append_int_noprefix(table_data, 0, 4);
69
/* Non-Secure EL1 timer Flags */
87
/* Platform Timer Offset */
70
build_append_int_noprefix(table_data, irqflags |
88
build_append_int_noprefix(table_data, 0, 4);
71
1UL << 2, /* Always-on Capability */
89
-
72
4);
90
+ if (vms->ns_el2_virt_timer_irq) {
73
/* Virtual timer GSIV */
91
+ /* Virtual EL2 Timer GSIV */
74
- build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
75
+ build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
76
/* Virtual Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
77
build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
78
/* Non-Secure EL2 timer GSIV */
96
+ build_append_int_noprefix(table_data, 0, 4);
79
- build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
80
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
98
+ }
81
/* Non-Secure EL2 timer Flags */
99
acpi_table_end(linker, &table);
82
build_append_int_noprefix(table_data, irqflags, 4);
100
}
83
/* CntReadBase Physical address */
101
84
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
85
for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
86
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
87
uint64_t physical_base_address = 0, gich = 0, gicv = 0;
105
{
88
- uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
106
- /* ACPI v6.0 */
89
+ uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
107
+ /* ACPI v6.3 */
90
uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
108
AcpiFadtData fadt = {
91
- PPI(VIRTUAL_PMU_IRQ) : 0;
109
.rev = 6,
92
+ VIRTUAL_PMU_IRQ : 0;
110
- .minor_ver = 0,
93
111
+ .minor_ver = 3,
94
if (vms->gic_version == VIRT_GIC_VERSION_2) {
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
95
physical_base_address = memmap[VIRT_GIC_CPU].base;
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
96
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
97
index XXXXXXX..XXXXXXX 100644
116
index XXXXXXX..XXXXXXX 100644
98
--- a/hw/arm/virt.c
117
--- a/hw/arm/virt.c
99
+++ b/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
121
}
122
123
+/*
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
126
+ * table unless it's really going to do something.
127
+ */
128
+static bool ns_el2_virt_timer_present(void)
129
+{
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
131
+ CPUARMState *env = &cpu->env;
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
100
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
101
}
142
}
102
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
103
qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
104
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
145
- GIC_FDT_IRQ_TYPE_PPI,
105
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
106
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
107
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
108
+ GIC_FDT_IRQ_TYPE_PPI,
149
- GIC_FDT_IRQ_TYPE_PPI,
109
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
110
+ GIC_FDT_IRQ_TYPE_PPI,
151
- GIC_FDT_IRQ_TYPE_PPI,
111
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
112
+ GIC_FDT_IRQ_TYPE_PPI,
153
+ if (vms->ns_el2_virt_timer_irq) {
113
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
114
+ GIC_FDT_IRQ_TYPE_PPI,
155
+ GIC_FDT_IRQ_TYPE_PPI,
115
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
116
}
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
117
177
118
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
119
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
120
*/
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
121
for (i = 0; i < smp_cpus; i++) {
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
122
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
123
- int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
124
+ int intidbase = NUM_IRQS + i * GIC_INTERNAL;
184
};
125
/* Mapping from the output timer irq lines from the CPU to the
185
126
* GIC PPI inputs we use for the virt board.
127
*/
128
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
129
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
130
qdev_connect_gpio_out(cpudev, irq,
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
131
qdev_get_gpio_in(vms->gic,
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
132
- ppibase + timer_irq[irq]));
189
object_unref(cpuobj);
133
+ intidbase + timer_irq[irq]));
190
}
134
}
191
+
135
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
136
if (vms->gic_version != VIRT_GIC_VERSION_2) {
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
137
qemu_irq irq = qdev_get_gpio_in(vms->gic,
194
+ !vmc->no_ns_el2_virt_timer_irq;
138
- ppibase + ARCH_GIC_MAINT_IRQ);
195
+
139
+ intidbase + ARCH_GIC_MAINT_IRQ);
196
fdt_add_timer_nodes(vms);
140
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
197
fdt_add_cpu_nodes(vms);
141
0, irq);
198
142
} else if (vms->virt) {
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
143
qemu_irq irq = qdev_get_gpio_in(vms->gic,
200
144
- ppibase + ARCH_GIC_MAINT_IRQ);
201
static void virt_machine_8_2_options(MachineClass *mc)
145
+ intidbase + ARCH_GIC_MAINT_IRQ);
202
{
146
sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
147
}
204
+
148
205
virt_machine_9_0_options(mc);
149
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
150
- qdev_get_gpio_in(vms->gic, ppibase
207
+ /*
151
+ qdev_get_gpio_in(vms->gic, intidbase
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
152
+ VIRTUAL_PMU_IRQ));
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
153
210
+ * guest BIOS binaries.)
154
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
211
+ */
155
@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
212
+ vmc->no_ns_el2_virt_timer_irq = true;
156
if (pmu) {
213
}
157
assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
214
DEFINE_VIRT_MACHINE(8, 2)
158
if (kvm_irqchip_in_kernel()) {
215
159
- kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
160
+ kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ);
161
}
162
kvm_arm_pmu_init(cpu);
163
}
164
--
216
--
165
2.34.1
217
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
1
Currently QEMU will warn if there is a NIC on the board that
2
is not connected to a backend. By default the '-nic user' will
3
get used for all NICs, but if you manually connect a specific
4
NIC to a specific backend, then the other NICs on the board
5
have no backend and will be warned about:
1
6
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
10
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
18
---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
20
1 file changed, 4 insertions(+), 1 deletion(-)
21
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/tests/qtest/npcm7xx_emc-test.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
28
* in the 'model' field to specify the device to match.
29
*/
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
32
+ "-nic user,model=npcm7xx-emc "
33
+ "-nic user,model=npcm-gmac "
34
+ "-nic user,model=npcm-gmac",
35
test_sockets[1], module_num);
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
CPU, and in fact if you try to do it we will assert:
1
3
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
9
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
11
from the migration pre/post hooks in machine.c); this should always
12
return false because these CPUs don't set ARM_FEATURE_PMU.
13
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
15
have done the early return for "PMU not present".
16
17
This fixes an assertion failure if you try to do a loadvm or
18
savevm for an M-profile board.
19
20
Cc: qemu-stable@nongnu.org
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
26
---
27
target/arm/helper.c | 12 ++++++++++--
28
1 file changed, 10 insertions(+), 2 deletions(-)
29
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
35
bool enabled, prohibited = false, filtered;
36
bool secure = arm_is_secure(env);
37
int el = arm_current_el(env);
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
40
+ uint64_t mdcr_el2;
41
+ uint8_t hpmn;
42
43
+ /*
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
46
+ * must be before we read that value.
47
+ */
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
49
return false;
50
}
51
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
54
+
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
56
(counter < hpmn || counter == 31)) {
57
e = env->cp15.c9_pmcr & PMCRE;
58
--
59
2.34.1
60
61
diff view generated by jsdifflib
[PULL 05/24] xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
1
From: Tong Ho <tong.ho@amd.com>
1
From: Nabih Estefan <nabihestefan@google.com>
2
2
3
This change implements the ResettableClass interface for the device.
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
4
5
5
Signed-off-by: Tong Ho <tong.ho@amd.com>
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
6
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
7
Message-id: 20231004055339.323833-1-tong.ho@amd.com
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: commit message tweaks]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +++++---
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
11
1 file changed, 5 insertions(+), 3 deletions(-)
15
tests/qtest/meson.build | 3 +-
16
2 files changed, 4 insertions(+), 83 deletions(-)
12
17
13
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/nvram/xlnx-versal-efuse-ctrl.c
20
--- a/tests/qtest/npcm_gmac-test.c
16
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
21
+++ b/tests/qtest/npcm_gmac-test.c
17
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
18
* QEMU model of the Versal eFuse controller
23
const GMACModule *module;
19
*
24
} TestData;
20
* Copyright (c) 2020 Xilinx Inc.
25
21
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
26
-/* Values extracted from hw/arm/npcm8xx.c */
22
*
27
+/* Values extracted from hw/arm/npcm7xx.c */
23
* Permission is hereby granted, free of charge, to any person obtaining a copy
28
static const GMACModule gmac_module_list[] = {
24
* of this software and associated documentation files (the "Software"), to deal
29
{
25
@@ -XXX,XX +XXX,XX @@ static void efuse_ctrl_register_reset(RegisterInfo *reg)
30
.irq = 14,
26
register_reset(reg);
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
32
.irq = 15,
33
.base_addr = 0xf0804000
34
},
35
- {
36
- .irq = 16,
37
- .base_addr = 0xf0806000
38
- },
39
- {
40
- .irq = 17,
41
- .base_addr = 0xf0808000
42
- }
43
};
44
45
/* Returns the index of the GMAC module. */
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
47
return qtest_readl(qts, mod->base_addr + regno);
27
}
48
}
28
49
29
-static void efuse_ctrl_reset(DeviceState *dev)
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
30
+static void efuse_ctrl_reset_hold(Object *obj)
51
- NPCMRegister regno)
52
-{
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
55
- uint32_t read_offset = regno & 0x1ff;
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
57
-}
58
-
59
/* Check that GMAC registers are reset to default value */
60
static void test_init(gconstpointer test_data)
31
{
61
{
32
- XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
62
const TestData *td = test_data;
33
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
63
const GMACModule *mod = td->module;
34
unsigned int i;
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
35
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
36
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
66
37
@@ -XXX,XX +XXX,XX @@ static Property efuse_ctrl_props[] = {
67
#define CHECK_REG32(regno, value) \
38
static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
68
do { \
39
{
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
40
DeviceClass *dc = DEVICE_CLASS(klass);
70
} while (0)
41
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
71
42
72
-#define CHECK_REG_PCS(regno, value) \
43
- dc->reset = efuse_ctrl_reset;
73
- do { \
44
+ rc->phases.hold = efuse_ctrl_reset_hold;
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
45
dc->realize = efuse_ctrl_realize;
75
- } while (0)
46
dc->vmsd = &vmstate_efuse_ctrl;
76
-
47
device_class_set_props(dc, efuse_ctrl_props);
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
89
-
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
140
- }
141
-
142
qtest_quit(qts);
143
}
144
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
146
index XXXXXXX..XXXXXXX 100644
147
--- a/tests/qtest/meson.build
148
+++ b/tests/qtest/meson.build
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
150
'npcm7xx_sdhci-test',
151
'npcm7xx_smbus-test',
152
'npcm7xx_timer-test',
153
- 'npcm7xx_watchdog_timer-test'] + \
154
+ 'npcm7xx_watchdog_timer-test',
155
+ 'npcm_gmac-test'] + \
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
157
qtests_aspeed = \
158
['aspeed_hace-test',
48
--
159
--
49
2.34.1
160
2.34.1
diff view generated by jsdifflib
[PULL 16/24] hw/arm/smmuv3: Update ID register bit field definitions
[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
1
Update the SMMUv3 ID register bit field definitions to the
1
From: Luc Michel <luc.michel@amd.com>
2
set in the most recent specification (IHI0700 F.a).
3
2
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
An access fault is raised when the Access Flag is not set in the
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
7
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: Mostafa Saleh <smostafa@google.com>
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org
11
Tested-by: Mostafa Saleh <smostafa@google.com>
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
13
[PMM: tweaked comment text]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
15
---
10
hw/arm/smmuv3-internal.h | 38 ++++++++++++++++++++++++++++++++++++++
16
hw/arm/smmuv3-internal.h | 1 +
11
1 file changed, 38 insertions(+)
17
include/hw/arm/smmu-common.h | 1 +
18
hw/arm/smmu-common.c | 11 +++++++++++
19
hw/arm/smmuv3.c | 1 +
20
4 files changed, 14 insertions(+)
12
21
13
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
14
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/smmuv3-internal.h
24
--- a/hw/arm/smmuv3-internal.h
16
+++ b/hw/arm/smmuv3-internal.h
25
+++ b/hw/arm/smmuv3-internal.h
17
@@ -XXX,XX +XXX,XX @@ REG32(IDR0, 0x0)
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
18
FIELD(IDR0, S1P, 1 , 1)
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
19
FIELD(IDR0, TTF, 2 , 2)
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
20
FIELD(IDR0, COHACC, 4 , 1)
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
21
+ FIELD(IDR0, BTM, 5 , 1)
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
22
+ FIELD(IDR0, HTTU, 6 , 2)
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
23
+ FIELD(IDR0, DORMHINT, 8 , 1)
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
24
+ FIELD(IDR0, HYP, 9 , 1)
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
25
+ FIELD(IDR0, ATS, 10, 1)
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
26
+ FIELD(IDR0, NS1ATS, 11, 1)
35
index XXXXXXX..XXXXXXX 100644
27
FIELD(IDR0, ASID16, 12, 1)
36
--- a/include/hw/arm/smmu-common.h
28
+ FIELD(IDR0, MSI, 13, 1)
37
+++ b/include/hw/arm/smmu-common.h
29
+ FIELD(IDR0, SEV, 14, 1)
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
30
+ FIELD(IDR0, ATOS, 15, 1)
39
bool disabled; /* smmu is disabled */
31
+ FIELD(IDR0, PRI, 16, 1)
40
bool bypassed; /* translation is bypassed */
32
+ FIELD(IDR0, VMW, 17, 1)
41
bool aborted; /* translation is aborted */
33
FIELD(IDR0, VMID16, 18, 1)
42
+ bool affd; /* AF fault disable */
34
+ FIELD(IDR0, CD2L, 19, 1)
43
uint32_t iotlb_hits; /* counts IOTLB hits */
35
+ FIELD(IDR0, VATOS, 20, 1)
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
36
FIELD(IDR0, TTENDIAN, 21, 2)
45
/* Used by stage-1 only. */
37
+ FIELD(IDR0, ATSRECERR, 23, 1)
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
38
FIELD(IDR0, STALL_MODEL, 24, 2)
47
index XXXXXXX..XXXXXXX 100644
39
FIELD(IDR0, TERM_MODEL, 26, 1)
48
--- a/hw/arm/smmu-common.c
40
FIELD(IDR0, STLEVEL, 27, 2)
49
+++ b/hw/arm/smmu-common.c
41
+ FIELD(IDR0, RME_IMPL, 30, 1)
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
42
51
pte_addr, pte, iova, gpa,
43
REG32(IDR1, 0x4)
52
block_size >> 20);
44
FIELD(IDR1, SIDSIZE, 0 , 6)
53
}
45
+ FIELD(IDR1, SSIDSIZE, 6 , 5)
46
+ FIELD(IDR1, PRIQS, 11, 5)
47
FIELD(IDR1, EVENTQS, 16, 5)
48
FIELD(IDR1, CMDQS, 21, 5)
49
+ FIELD(IDR1, ATTR_PERMS_OVR, 26, 1)
50
+ FIELD(IDR1, ATTR_TYPES_OVR, 27, 1)
51
+ FIELD(IDR1, REL, 28, 1)
52
+ FIELD(IDR1, QUEUES_PRESET, 29, 1)
53
+ FIELD(IDR1, TABLES_PRESET, 30, 1)
54
+ FIELD(IDR1, ECMDQ, 31, 1)
55
56
#define SMMU_IDR1_SIDSIZE 16
57
#define SMMU_CMDQS 19
58
#define SMMU_EVENTQS 19
59
60
REG32(IDR2, 0x8)
61
+ FIELD(IDR2, BA_VATOS, 0, 10)
62
+
54
+
63
REG32(IDR3, 0xc)
55
+ /*
64
FIELD(IDR3, HAD, 2, 1);
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
65
+ FIELD(IDR3, PBHA, 3, 1);
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
66
+ FIELD(IDR3, XNX, 4, 1);
58
+ * An Access flag fault takes priority over a Permission fault.
67
+ FIELD(IDR3, PPS, 5, 1);
59
+ */
68
+ FIELD(IDR3, MPAM, 7, 1);
60
+ if (!PTE_AF(pte) && !cfg->affd) {
69
+ FIELD(IDR3, FWB, 8, 1);
61
+ info->type = SMMU_PTW_ERR_ACCESS;
70
+ FIELD(IDR3, STT, 9, 1);
62
+ goto error;
71
FIELD(IDR3, RIL, 10, 1);
63
+ }
72
FIELD(IDR3, BBML, 11, 2);
73
+ FIELD(IDR3, E0PD, 13, 1);
74
+ FIELD(IDR3, PTWNNC, 14, 1);
75
+ FIELD(IDR3, DPT, 15, 1);
76
+
64
+
77
REG32(IDR4, 0x10)
65
ap = PTE_AP(pte);
78
+
66
if (is_permission_fault(ap, perm)) {
79
REG32(IDR5, 0x14)
67
info->type = SMMU_PTW_ERR_PERMISSION;
80
FIELD(IDR5, OAS, 0, 3);
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
81
FIELD(IDR5, GRAN4K, 4, 1);
69
index XXXXXXX..XXXXXXX 100644
82
FIELD(IDR5, GRAN16K, 5, 1);
70
--- a/hw/arm/smmuv3.c
83
FIELD(IDR5, GRAN64K, 6, 1);
71
+++ b/hw/arm/smmuv3.c
84
+ FIELD(IDR5, VAX, 10, 2);
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
85
+ FIELD(IDR5, STALL_MAX, 16, 16);
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
86
74
cfg->tbi = CD_TBI(cd);
87
#define SMMU_IDR5_OAS 4
75
cfg->asid = CD_ASID(cd);
76
+ cfg->affd = CD_AFFD(cd);
77
78
trace_smmuv3_decode_cd(cfg->oas);
88
79
89
--
80
--
90
2.34.1
81
2.34.1
diff view generated by jsdifflib
[PULL 03/24] xlnx-bbram: hw/nvram: Remove deprecated device reset
[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
1
From: Tong Ho <tong.ho@amd.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
This change implements the ResettableClass interface for the device.
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Tong Ho <tong.ho@amd.com>
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20231003052345.199725-1-tong.ho@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
7
---
10
hw/nvram/xlnx-bbram.c | 8 +++++---
8
hw/arm/stellaris.c | 6 ++++--
11
1 file changed, 5 insertions(+), 3 deletions(-)
9
1 file changed, 4 insertions(+), 2 deletions(-)
12
10
13
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/nvram/xlnx-bbram.c
13
--- a/hw/arm/stellaris.c
16
+++ b/hw/nvram/xlnx-bbram.c
14
+++ b/hw/arm/stellaris.c
17
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
18
* QEMU model of the Xilinx BBRAM Battery Backed RAM
19
*
20
* Copyright (c) 2014-2021 Xilinx Inc.
21
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
22
*
23
* Permission is hereby granted, free of charge, to any person obtaining a copy
24
* of this software and associated documentation files (the "Software"), to deal
25
@@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = {
26
}
16
}
27
};
17
}
28
18
29
-static void bbram_ctrl_reset(DeviceState *dev)
19
-static void stellaris_adc_reset(StellarisADCState *s)
30
+static void bbram_ctrl_reset_hold(Object *obj)
20
+static void stellaris_adc_reset_hold(Object *obj)
31
{
21
{
32
- XlnxBBRam *s = XLNX_BBRAM(dev);
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
33
+ XlnxBBRam *s = XLNX_BBRAM(obj);
23
int n;
34
unsigned int i;
24
35
25
for (n = 0; n < 4; n++) {
36
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
37
@@ -XXX,XX +XXX,XX @@ static Property bbram_ctrl_props[] = {
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
38
static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
28
"adc", 0x1000);
29
sysbus_init_mmio(sbd, &s->iomem);
30
- stellaris_adc_reset(s);
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
32
}
33
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
39
{
36
{
40
DeviceClass *dc = DEVICE_CLASS(klass);
37
DeviceClass *dc = DEVICE_CLASS(klass);
41
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
42
39
43
- dc->reset = bbram_ctrl_reset;
40
+ rc->phases.hold = stellaris_adc_reset_hold;
44
+ rc->phases.hold = bbram_ctrl_reset_hold;
41
dc->vmsd = &vmstate_stellaris_adc;
45
dc->realize = bbram_ctrl_realize;
42
}
46
dc->vmsd = &vmstate_bbram_ctrl;
43
47
device_class_set_props(dc, bbram_ctrl_props);
48
--
44
--
49
2.34.1
45
2.34.1
50
46
51
47
diff view generated by jsdifflib
[PULL 04/24] xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
1
From: Tong Ho <tong.ho@amd.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
This change implements the ResettableClass interface for the device.
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Tong Ho <tong.ho@amd.com>
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
6
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20231004055713.324009-1-tong.ho@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
8
---
10
hw/nvram/xlnx-zynqmp-efuse.c | 8 +++++---
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
11
1 file changed, 5 insertions(+), 3 deletions(-)
10
1 file changed, 22 insertions(+), 4 deletions(-)
12
11
13
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/nvram/xlnx-zynqmp-efuse.c
14
--- a/hw/arm/stellaris.c
16
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
15
+++ b/hw/arm/stellaris.c
17
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
18
* QEMU model of the ZynqMP eFuse
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
19
*
20
* Copyright (c) 2015 Xilinx Inc.
21
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
22
*
23
* Written by Edgar E. Iglesias <edgari@xilinx.com>
24
*
25
@@ -XXX,XX +XXX,XX @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg)
26
register_reset(reg);
27
}
18
}
28
19
29
-static void zynqmp_efuse_reset(DeviceState *dev)
20
-/* I2C controller. */
30
+static void zynqmp_efuse_reset_hold(Object *obj)
21
+/*
22
+ * I2C controller.
23
+ * ??? For now we only implement the master interface.
24
+ */
25
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
29
stellaris_i2c_update(s);
30
}
31
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
31
{
34
{
32
- XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
33
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
36
+
34
unsigned int i;
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
35
38
i2c_end_transfer(s->bus);
36
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
39
+}
37
@@ -XXX,XX +XXX,XX @@ static Property zynqmp_efuse_props[] = {
40
+
38
static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
41
+static void stellaris_i2c_reset_hold(Object *obj)
42
+{
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
44
45
s->msa = 0;
46
s->mcs = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
48
s->mimr = 0;
49
s->mris = 0;
50
s->mcr = 0;
51
+}
52
+
53
+static void stellaris_i2c_reset_exit(Object *obj)
54
+{
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
56
+
57
stellaris_i2c_update(s);
58
}
59
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
62
"i2c", 0x1000);
63
sysbus_init_mmio(sbd, &s->iomem);
64
- /* ??? For now we only implement the master interface. */
65
- stellaris_i2c_reset(s);
66
}
67
68
/* Analogue to Digital Converter. This is only partially implemented,
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
39
{
71
{
40
DeviceClass *dc = DEVICE_CLASS(klass);
72
DeviceClass *dc = DEVICE_CLASS(klass);
41
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
42
74
43
- dc->reset = zynqmp_efuse_reset;
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
44
+ rc->phases.hold = zynqmp_efuse_reset_hold;
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
45
dc->realize = zynqmp_efuse_realize;
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
46
dc->vmsd = &vmstate_efuse;
78
dc->vmsd = &vmstate_stellaris_i2c;
47
device_class_set_props(dc, zynqmp_efuse_props);
79
}
80
48
--
81
--
49
2.34.1
82
2.34.1
83
84
diff view generated by jsdifflib
New patch
[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
5
6
This commit plug the devices which aren't part of the SoC;
7
they will be plugged into a SoC container in the next one.
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/stellaris.c | 4 ++++
15
1 file changed, 4 insertions(+)
16
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/stellaris.c
20
+++ b/hw/arm/stellaris.c
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
22
&error_fatal);
23
24
ssddev = qdev_new("ssd0323");
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
26
qdev_prop_set_uint8(ssddev, "cs", 1);
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
28
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
30
+ object_property_add_child(OBJECT(ms), "splitter",
31
+ OBJECT(gpio_d_splitter));
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
34
qdev_connect_gpio_out(
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
36
DeviceState *gpad;
37
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
42
}
43
--
44
2.34.1
45
46
diff view generated by jsdifflib
[PULL 02/24] hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'
[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
struct arm_boot_info is declared in "hw/arm/boot.h".
3
QDev objects created with qdev_new() need to manually add
4
By including the correct header we don't need to declare
4
their parent relationship with object_property_add_child().
5
it again in "target/arm/cpu-qom.h".
5
6
Since we don't model the SoC, just use a QOM container.
6
7
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20231013130214.95742-1-philmd@linaro.org
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
include/hw/arm/exynos4210.h | 2 +-
13
hw/arm/stellaris.c | 11 ++++++++++-
13
target/arm/cpu-qom.h | 2 --
14
1 file changed, 10 insertions(+), 1 deletion(-)
14
2 files changed, 1 insertion(+), 3 deletions(-)
15
15
16
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/exynos4210.h
18
--- a/hw/arm/stellaris.c
19
+++ b/include/hw/arm/exynos4210.h
19
+++ b/hw/arm/stellaris.c
20
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
21
#include "hw/intc/exynos4210_gic.h"
21
* 400fe000 system control
22
#include "hw/intc/exynos4210_combiner.h"
22
*/
23
#include "hw/core/split-irq.h"
23
24
-#include "target/arm/cpu-qom.h"
24
+ Object *soc_container;
25
+#include "hw/arm/boot.h"
25
DeviceState *gpio_dev[7], *nvic;
26
#include "qom/object.h"
26
qemu_irq gpio_in[7][8];
27
27
qemu_irq gpio_out[7][8];
28
#define EXYNOS4210_NCPUS 2
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
29
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
30
index XXXXXXX..XXXXXXX 100644
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
31
--- a/target/arm/cpu-qom.h
31
32
+++ b/target/arm/cpu-qom.h
32
+ soc_container = object_new("container");
33
@@ -XXX,XX +XXX,XX @@
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
34
#include "hw/core/cpu.h"
34
+
35
#include "qom/object.h"
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
36
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
37
-struct arm_boot_info;
37
&error_fatal);
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
39
* need its sysclk output.
40
*/
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
43
44
/*
45
* Most devices come preprogrammed with a MAC address in the user data.
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
48
49
nvic = qdev_new(TYPE_ARMV7M);
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
55
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
57
sbd = SYS_BUS_DEVICE(dev);
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
59
qdev_connect_clock_in(dev, "clk",
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
61
sysbus_realize_and_unref(sbd, &error_fatal);
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
63
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
38
-
66
-
39
#define TYPE_ARM_CPU "arm-cpu"
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
40
68
qdev_connect_clock_in(dev, "WDOGCLK",
41
OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
70
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
72
SysBusDevice *sbd;
73
74
dev = qdev_new("pl011_luminary");
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
76
sbd = SYS_BUS_DEVICE(dev);
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
78
sysbus_realize_and_unref(sbd, &error_fatal);
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
DeviceState *enet;
81
82
enet = qdev_new("stellaris_enet");
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
84
if (nd) {
85
qdev_set_nic_properties(enet, nd);
86
} else {
42
--
87
--
43
2.34.1
88
2.34.1
44
89
45
90
diff view generated by jsdifflib
[PULL 09/24] target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
1
From: Michal Orzel <michal.orzel@amd.com>
1
We support two different encodings for the AArch32 IMPDEF
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
have this at 4, c15, c0, 0; newer cores like the
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
2
5
3
On an attempt to access CNTPCT_EL0 from EL0 using a guest running on top
6
When we implemented this we picked which encoding to
4
of Xen, a trap from EL2 was observed which is something not reproducible
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
5
on HW (also, Xen does not trap accesses to physical counter).
8
However this isn't right for three cases:
9
* the qemu-system-arm 'max' CPU, which is supposed to be
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
6
19
7
This is because gt_counter_access() checks for an incorrect bit (1
20
Make the decision of the encoding be based on whether
8
instead of 0) of CNTHCTL_EL2 if HCR_EL2.E2H is 0 and access is made to
21
the CPU implements the ARM_FEATURE_V8 flag instead.
9
physical counter. Refer ARM ARM DDI 0487J.a, D19.12.2:
10
When HCR_EL2.E2H is 0:
11
- EL1PCTEN, bit [0]: refers to physical counter
12
- EL1PCEN, bit [1]: refers to physical timer registers
13
22
14
Drop entire block "if (hcr & HCR_E2H) {...} else {...}" from EL0 case
23
This changes the behaviour only for the qemu-system-arm
15
and fall through to EL1 case, given that after fixing checking for the
24
'-cpu max'. We don't expect anybody to be relying on the
16
correct bit, the handling is the same.
25
old behaviour because:
26
* it's not what the real hardware Cortex-A57 does
27
(and that's what our ID register claims we are)
28
* we don't implement the memory-mapped GICv3 support
29
which is the only thing that exists at the peripheral
30
base address pointed to by the register
17
31
18
Fixes: 5bc8437136fb ("target/arm: Update timer access for VHE")
19
Signed-off-by: Michal Orzel <michal.orzel@amd.com>
20
Tested-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
21
Message-id: 20230928094404.20802-1-michal.orzel@amd.com
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
24
---
35
---
25
target/arm/helper.c | 17 +----------------
36
target/arm/helper.c | 2 +-
26
1 file changed, 1 insertion(+), 16 deletions(-)
37
1 file changed, 1 insertion(+), 1 deletion(-)
27
38
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
33
if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
44
* AArch64 cores we might need to add a specific feature flag
34
return CP_ACCESS_TRAP;
45
* to indicate cores with "flavour 2" CBAR.
35
}
46
*/
36
-
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
37
- /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
38
- if (hcr & HCR_E2H) {
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
39
- if (timeridx == GTIMER_PHYS &&
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
40
- !extract32(env->cp15.cnthctl_el2, 10, 1)) {
51
| extract64(cpu->reset_cbar, 32, 12);
41
- return CP_ACCESS_TRAP_EL2;
42
- }
43
- } else {
44
- /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
45
- if (has_el2 && timeridx == GTIMER_PHYS &&
46
- !extract32(env->cp15.cnthctl_el2, 1, 1)) {
47
- return CP_ACCESS_TRAP_EL2;
48
- }
49
- }
50
- break;
51
-
52
+ /* fall through */
53
case 1:
54
/* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
55
if (has_el2 && timeridx == GTIMER_PHYS &&
56
--
52
--
57
2.34.1
53
2.34.1
diff view generated by jsdifflib
[PULL 21/24] target/arm/common-semi-target.h: Remove unnecessary boot.h include
[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
1
The hw/arm/boot.h include in common-semi-target.h is not actually
1
The Cortex-R52 implements the Configuration Base Address Register
2
needed, and it's a bit odd because it pulls a hw/arm header into a
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
target/arm file.
3
type, so that our implementation provides the register and the
4
4
associated qdev property.
5
This include was originally needed because the semihosting code used
6
the arm_boot_info struct to get the base address of the RAM in system
7
emulation, to use in a (bad) heuristic for the return values for the
8
SYS_HEAPINFO semihosting call. We've since overhauled how we
9
calculate the HEAPINFO values in system emulation, and the code no
10
longer uses the arm_boot_info struct.
11
12
Remove the now-redundant include line, and instead directly include
13
the cpu-qom.h header that we were previously getting via boot.h.
14
5
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20230925112219.3919261-1-peter.maydell@linaro.org
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
18
---
9
---
19
target/arm/common-semi-target.h | 4 +---
10
target/arm/tcg/cpu32.c | 1 +
20
1 file changed, 1 insertion(+), 3 deletions(-)
11
1 file changed, 1 insertion(+)
21
12
22
diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-target.h
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
23
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/common-semi-target.h
15
--- a/target/arm/tcg/cpu32.c
25
+++ b/target/arm/common-semi-target.h
16
+++ b/target/arm/tcg/cpu32.c
26
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
27
#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
28
#define TARGET_ARM_COMMON_SEMI_TARGET_H
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
29
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
30
-#ifndef CONFIG_USER_ONLY
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
31
-#include "hw/arm/boot.h"
22
cpu->midr = 0x411fd133; /* r1p3 */
32
-#endif
23
cpu->revidr = 0x00000000;
33
+#include "target/arm/cpu-qom.h"
24
cpu->reset_fpsid = 0x41034023;
34
35
static inline target_ulong common_semi_arg(CPUState *cs, int argno)
36
{
37
--
25
--
38
2.34.1
26
2.34.1
diff view generated by jsdifflib
[PULL 19/24] target/arm: Implement FEAT_HPMN0
[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
1
FEAT_HPMN0 is a small feature which defines that it is valid for
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided
2
also by enabling the AUXCR feature which defines the ACTLR
3
to an EL1 guest" (previously this setting was reserved). QEMU's
3
and HACTLR registers. As is our usual practice, we make these
4
implementation almost gets HPMN == 0 right, but we need to fix
4
simple reads-as-zero stubs for now.
5
one check in pmevcntr_is_64_bit(). That is enough for us to
6
advertise the feature in the 'max' CPU.
7
8
(We don't need to make the behaviour conditional on feature
9
presence, because the FEAT_HPMN0 behaviour is within the range
10
of permitted UNPREDICTABLE behaviour for a non-FEAT_HPMN0
11
implementation.)
12
5
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230921185445.3339214-1-peter.maydell@linaro.org
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
16
---
9
---
17
docs/system/arm/emulation.rst | 1 +
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
18
target/arm/helper.c | 2 +-
11
1 file changed, 108 insertions(+)
19
target/arm/tcg/cpu32.c | 4 ++++
20
target/arm/tcg/cpu64.c | 1 +
21
4 files changed, 7 insertions(+), 1 deletion(-)
22
12
23
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
24
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/system/arm/emulation.rst
26
+++ b/docs/system/arm/emulation.rst
27
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
28
- FEAT_HCX (Support for the HCRX_EL2 register)
29
- FEAT_HPDS (Hierarchical permission disables)
30
- FEAT_HPDS2 (Translation table page-based hardware attributes)
31
+- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
32
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
33
- FEAT_IDST (ID space trap handling)
34
- FEAT_IESB (Implicit error synchronization event)
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.c
38
+++ b/target/arm/helper.c
39
@@ -XXX,XX +XXX,XX @@ static bool pmevcntr_is_64_bit(CPUARMState *env, int counter)
40
bool hlp = env->cp15.mdcr_el2 & MDCR_HLP;
41
int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
42
43
- if (hpmn != 0 && counter >= hpmn) {
44
+ if (counter >= hpmn) {
45
return hlp;
46
}
47
}
48
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
49
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/tcg/cpu32.c
15
--- a/target/arm/tcg/cpu32.c
51
+++ b/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
52
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
53
t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
54
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
19
}
55
cpu->isar.id_dfr0 = t;
20
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
24
+ { .name = "IMP_ATCMREGIONR",
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
27
+ { .name = "IMP_BTCMREGIONR",
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
30
+ { .name = "IMP_CTCMREGIONR",
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ { .name = "IMP_CSCTLR",
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "IMP_BPCTLR",
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "IMP_MEMPROTCLR",
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "IMP_SLAVEPCTLR",
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "IMP_PERIPHREGIONR",
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "IMP_FLASHIFREGIONR",
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
56
+
124
+
57
+ t = cpu->isar.id_dfr1;
125
+
58
+ t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
126
static void cortex_r52_initfn(Object *obj)
59
+ cpu->isar.id_dfr1 = t;
127
{
128
ARMCPU *cpu = ARM_CPU(obj);
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
134
cpu->midr = 0x411fd133; /* r1p3 */
135
cpu->revidr = 0x00000000;
136
cpu->reset_fpsid = 0x41034023;
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
138
139
cpu->pmsav7_dregion = 16;
140
cpu->pmsav8r_hdregion = 16;
141
+
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
60
}
143
}
61
144
62
/* CPU models. These are not needed for the AArch64 linux-user build. */
145
static void cortex_r5f_initfn(Object *obj)
63
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/tcg/cpu64.c
66
+++ b/target/arm/tcg/cpu64.c
67
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
68
t = cpu->isar.id_aa64dfr0;
69
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
70
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
71
+ t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
72
cpu->isar.id_aa64dfr0 = t;
73
74
t = cpu->isar.id_aa64smfr0;
75
--
146
--
76
2.34.1
147
2.34.1
diff view generated by jsdifflib
[PULL 17/24] hw/arm/smmuv3: Sort ID register setting into field order
[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
1
In smmuv3_init_regs() when we set the various bits in the ID
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
registers, we do this almost in order of the fields in the
2
instructions are UNPREDICTABLE for attempts to access a banked
3
registers, but not quite. Move the initialization of
3
register that the guest could access in a more direct way (e.g.
4
SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places.
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
chosen to UNDEF on all of these.
6
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
8
out that real hardware permits this, with the same effect as if the
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
17
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
5
20
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Mostafa Saleh <smostafa@google.com>
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org
11
---
24
---
12
hw/arm/smmuv3.c | 4 ++--
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
13
1 file changed, 2 insertions(+), 2 deletions(-)
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
14
28
15
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
16
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/smmuv3.c
31
--- a/target/arm/tcg/op_helper.c
18
+++ b/hw/arm/smmuv3.c
32
+++ b/target/arm/tcg/op_helper.c
19
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
20
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
34
*/
21
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
35
int curmode = env->uncached_cpsr & CPSR_M;
22
36
23
- s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
37
- if (regno == 17) {
24
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
25
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
26
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
40
- goto undef;
27
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
28
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
42
+ /*
29
/* 4K, 16K and 64K granule support */
43
+ * Handle Hyp target regs first because some are special cases
30
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
44
+ * which don't want the usual "not accessible from tgtmode" check.
31
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1);
45
+ */
32
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
46
+ switch (regno) {
33
- s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
34
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
35
s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
49
+ goto undef;
36
s->cmdq.prod = 0;
50
+ }
51
+ break;
52
+ case 13:
53
+ if (curmode != ARM_CPU_MODE_MON) {
54
+ goto undef;
55
+ }
56
+ break;
57
+ default:
58
+ g_assert_not_reached();
59
}
60
return;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
63
}
64
}
65
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
68
- if (curmode != ARM_CPU_MODE_MON) {
69
- goto undef;
70
- }
71
- }
72
-
73
return;
74
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
37
--
135
--
38
2.34.1
136
2.34.1
diff view generated by jsdifflib
New patch
[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
1
We currently guard the CFG3 register read with
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
which is clearly wrong as it is never true.
1
4
5
This register is present on all board types except AN524
6
and AN527; correct the condition.
7
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
13
---
14
hw/misc/mps2-scc.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/mps2-scc.c
20
+++ b/hw/misc/mps2-scc.c
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
22
r = s->cfg2;
23
break;
24
case A_CFG3:
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
27
/* CFG3 reserved on AN524 */
28
goto bad_offset;
29
}
30
--
31
2.34.1
32
33
diff view generated by jsdifflib
New patch
[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
1
The MPS SCC device has a lot of different flavours for the various
2
different MPS FPGA images, which look mostly similar but have
3
differences in how particular registers are handled. Currently we
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
as we add more board types this is getting a bit hard to read.
1
6
7
Factor out the conditions into some functions which we can
8
give more descriptive names to.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
14
---
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
16
1 file changed, 31 insertions(+), 14 deletions(-)
17
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/mps2-scc.c
21
+++ b/hw/misc/mps2-scc.c
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
23
return extract32(s->id, 4, 8);
24
}
25
26
+/* Is CFG_REG2 present? */
27
+static bool have_cfg2(MPS2SCC *s)
28
+{
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
30
+}
31
+
32
+/* Is CFG_REG3 present? */
33
+static bool have_cfg3(MPS2SCC *s)
34
+{
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
36
+}
37
+
38
+/* Is CFG_REG5 present? */
39
+static bool have_cfg5(MPS2SCC *s)
40
+{
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
42
+}
43
+
44
+/* Is CFG_REG6 present? */
45
+static bool have_cfg6(MPS2SCC *s)
46
+{
47
+ return scc_partno(s) == 0x524;
48
+}
49
+
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
52
*/
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
54
r = s->cfg1;
55
break;
56
case A_CFG2:
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
58
- /* CFG2 reserved on other boards */
59
+ if (!have_cfg2(s)) {
60
goto bad_offset;
61
}
62
r = s->cfg2;
63
break;
64
case A_CFG3:
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
66
- /* CFG3 reserved on AN524 */
67
+ if (!have_cfg3(s)) {
68
goto bad_offset;
69
}
70
/* These are user-settable DIP switches on the board. We don't
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
72
r = s->cfg4;
73
break;
74
case A_CFG5:
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
76
- /* CFG5 reserved on other boards */
77
+ if (!have_cfg5(s)) {
78
goto bad_offset;
79
}
80
r = s->cfg5;
81
break;
82
case A_CFG6:
83
- if (scc_partno(s) != 0x524) {
84
- /* CFG6 reserved on other boards */
85
+ if (!have_cfg6(s)) {
86
goto bad_offset;
87
}
88
r = s->cfg6;
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
90
}
91
break;
92
case A_CFG2:
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
94
- /* CFG2 reserved on other boards */
95
+ if (!have_cfg2(s)) {
96
goto bad_offset;
97
}
98
/* AN524: QSPI Select signal */
99
s->cfg2 = value;
100
break;
101
case A_CFG5:
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
103
- /* CFG5 reserved on other boards */
104
+ if (!have_cfg5(s)) {
105
goto bad_offset;
106
}
107
/* AN524: ACLK frequency in Hz */
108
s->cfg5 = value;
109
break;
110
case A_CFG6:
111
- if (scc_partno(s) != 0x524) {
112
- /* CFG6 reserved on other boards */
113
+ if (!have_cfg6(s)) {
114
goto bad_offset;
115
}
116
/* AN524: Clock divider for BRAM */
117
--
118
2.34.1
119
120
diff view generated by jsdifflib
[PULL 18/24] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
1
The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
supported, so we should theoretically have implemented it as part of
2
minor differences in the behaviour of the CFG registers depending on
3
the recent S2P work. Fortunately, for us the implementation is a
3
the image. In many cases we don't really care about the functionality
4
no-op.
4
controlled by these registers and a reads-as-written or similar
5
5
behaviour is sufficient for the moment.
6
This feature is about interpretation of the stage 2 page table
6
7
descriptor XN bits, which control execute permissions.
7
For the AN536 the required behaviour is:
8
8
9
For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and
9
* A_CFG0 has CPU reset and halt bits
10
IOMMUAccessFlags) only indicate read and write; we do not distinguish
10
- implement as reads-as-written for the moment
11
data reads from instruction reads outside the CPU proper. In the
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
SMMU architecture's terms, our interconnect between the client device
12
- QEMU doesn't model this; implement as reads-as-written
13
and the SMMU doesn't have the ability to convey the INST attribute,
13
* A_CFG2 has QSPI select (like AN524)
14
and we therefore use the default value of "data" for this attribute.
14
- implemented (no behaviour, as with AN524)
15
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
We also do not support the bits in the Stream Table Entry that can
16
- QEMU doesn't care about these, so use the existing
17
override the on-the-bus transaction attribute permissions (we do not
17
RAZ behaviour for convenience
18
set SMMU_IDR1.ATTR_PERMS_OVR=1).
18
* A_CFG4 is board rev (like all other images)
19
19
- no change needed
20
These two things together mean that for our implementation, it never
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
has to deal with transactions with the INST attribute, and so it can
21
- implemented as reads-as-written, as for other boards
22
correctly ignore the XN bits entirely. So we already implement
22
* A_CFG6 is core 0 vector table base address
23
FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent
23
- implemented as reads-as-written for the moment
24
that we need to.
24
* A_CFG7 is core 1 vector table base address
25
25
- implemented as reads-as-written for the moment
26
Advertise the presence of the feature in SMMU_IDR3.XNX.
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
27
34
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
30
Reviewed-by: Mostafa Saleh <smostafa@google.com>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
31
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
32
Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org
33
---
39
---
34
hw/arm/smmuv3.c | 4 ++++
40
include/hw/misc/mps2-scc.h | 1 +
35
1 file changed, 4 insertions(+)
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
36
42
2 files changed, 92 insertions(+), 10 deletions(-)
37
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
43
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
38
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/smmuv3.c
46
--- a/include/hw/misc/mps2-scc.h
40
+++ b/hw/arm/smmuv3.c
47
+++ b/include/hw/misc/mps2-scc.h
41
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
42
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
49
uint32_t cfg4;
43
50
uint32_t cfg5;
44
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
51
uint32_t cfg6;
45
+ if (FIELD_EX32(s->idr[0], IDR0, S2P)) {
52
+ uint32_t cfg7;
46
+ /* XNX is a stage-2-specific feature */
53
uint32_t cfgdata_rtn;
47
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1);
54
uint32_t cfgdata_out;
55
uint32_t cfgctrl;
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/mps2-scc.c
59
+++ b/hw/misc/mps2-scc.c
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
61
REG32(CFG4, 0x10)
62
REG32(CFG5, 0x14)
63
REG32(CFG6, 0x18)
64
+REG32(CFG7, 0x1c)
65
REG32(CFGDATA_RTN, 0xa0)
66
REG32(CFGDATA_OUT, 0xa4)
67
REG32(CFGCTRL, 0xa8)
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
69
/* Is CFG_REG2 present? */
70
static bool have_cfg2(MPS2SCC *s)
71
{
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
74
+ scc_partno(s) == 0x536;
75
}
76
77
/* Is CFG_REG3 present? */
78
static bool have_cfg3(MPS2SCC *s)
79
{
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
82
+ scc_partno(s) != 0x536;
83
}
84
85
/* Is CFG_REG5 present? */
86
static bool have_cfg5(MPS2SCC *s)
87
{
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
90
+ scc_partno(s) == 0x536;
91
}
92
93
/* Is CFG_REG6 present? */
94
static bool have_cfg6(MPS2SCC *s)
95
{
96
- return scc_partno(s) == 0x524;
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
98
+}
99
+
100
+/* Is CFG_REG7 present? */
101
+static bool have_cfg7(MPS2SCC *s)
102
+{
103
+ return scc_partno(s) == 0x536;
104
+}
105
+
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
107
+static bool cfg0_is_remap(MPS2SCC *s)
108
+{
109
+ return scc_partno(s) != 0x536;
110
+}
111
+
112
+/* Is CFG_REG1 driving a set of LEDs? */
113
+static bool cfg1_is_leds(MPS2SCC *s)
114
+{
115
+ return scc_partno(s) != 0x536;
116
}
117
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
120
if (!have_cfg3(s)) {
121
goto bad_offset;
122
}
123
- /* These are user-settable DIP switches on the board. We don't
124
+ /*
125
+ * These are user-settable DIP switches on the board. We don't
126
* model that, so just return zeroes.
127
+ *
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
129
+ * bits". These change which part of the DDR4 the motherboard
130
+ * configuration controller can see in its memory map (see the
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
132
+ * bits are not interesting to us; read-as-zero is as good as anything
133
+ * else.
134
*/
135
r = 0;
136
break;
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
138
}
139
r = s->cfg6;
140
break;
141
+ case A_CFG7:
142
+ if (!have_cfg7(s)) {
143
+ goto bad_offset;
144
+ }
145
+ r = s->cfg7;
146
+ break;
147
case A_CFGDATA_RTN:
148
r = s->cfgdata_rtn;
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
151
* we always reflect bit 0 in the 'remap' GPIO output line,
152
* and let the board wire it up or not as it chooses.
153
* TODO on some boards bit 1 is CPU_WAIT.
154
+ *
155
+ * TODO: on the AN536 this register controls reset and halt
156
+ * for both CPUs. For the moment we don't implement this, so the
157
+ * register just reads as written.
158
*/
159
s->cfg0 = value;
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
161
+ if (cfg0_is_remap(s)) {
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
163
+ }
164
break;
165
case A_CFG1:
166
s->cfg1 = value;
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
168
- led_set_state(s->led[i], extract32(value, i, 1));
169
+ /*
170
+ * On most boards this register drives LEDs.
171
+ *
172
+ * TODO: for AN536 this controls whether flash and ATCM are
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
175
+ */
176
+ if (cfg1_is_leds(s)) {
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
178
+ led_set_state(s->led[i], extract32(value, i, 1));
179
+ }
180
}
181
break;
182
case A_CFG2:
183
if (!have_cfg2(s)) {
184
goto bad_offset;
185
}
186
- /* AN524: QSPI Select signal */
187
+ /* AN524, AN536: QSPI Select signal */
188
s->cfg2 = value;
189
break;
190
case A_CFG5:
191
if (!have_cfg5(s)) {
192
goto bad_offset;
193
}
194
- /* AN524: ACLK frequency in Hz */
195
+ /* AN524, AN536: ACLK frequency in Hz */
196
s->cfg5 = value;
197
break;
198
case A_CFG6:
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
200
goto bad_offset;
201
}
202
/* AN524: Clock divider for BRAM */
203
+ /* AN536: Core 0 vector table base address */
204
+ s->cfg6 = value;
205
+ break;
206
+ case A_CFG7:
207
+ if (!have_cfg7(s)) {
208
+ goto bad_offset;
209
+ }
210
+ /* AN536: Core 1 vector table base address */
211
s->cfg6 = value;
212
break;
213
case A_CFGDATA_OUT:
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
215
g_free(s->oscclk_reset);
216
}
217
218
+static bool cfg7_needed(void *opaque)
219
+{
220
+ MPS2SCC *s = opaque;
221
+
222
+ return have_cfg7(s);
223
+}
224
+
225
+static const VMStateDescription vmstate_cfg7 = {
226
+ .name = "mps2-scc/cfg7",
227
+ .version_id = 1,
228
+ .minimum_version_id = 1,
229
+ .needed = cfg7_needed,
230
+ .fields = (const VMStateField[]) {
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
232
+ VMSTATE_END_OF_LIST()
48
+ }
233
+ }
49
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
234
+};
50
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
235
+
236
static const VMStateDescription mps2_scc_vmstate = {
237
.name = "mps2-scc",
238
.version_id = 3,
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
241
0, vmstate_info_uint32, uint32_t),
242
VMSTATE_END_OF_LIST()
243
+ },
244
+ .subsections = (const VMStateDescription * const []) {
245
+ &vmstate_cfg7,
246
+ NULL
247
}
248
};
51
249
52
--
250
--
53
2.34.1
251
2.34.1
252
253
diff view generated by jsdifflib
[PULL 01/24] hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
1
From: Thomas Huth <thuth@redhat.com>
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
2
the existing FPGA images we already model, this board uses a Cortex-R
3
The file is obviously related to the raspberrypi machine, so
3
family CPU, and it does not use any equivalent to the M-profile
4
it should reside in hw/arm/ instead of hw/misc/. And while we're
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
at it, also adjust the wildcard in MAINTAINERS so that it covers
5
It's therefore more convenient for us to model it as a completely
6
this file, too.
6
separate C file.
7
7
8
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
This commit adds the basic skeleton of the board model, and the
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
code to create all the RAM and ROM. We assume that we're probably
10
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
going to want to add more images in future, so use the same
11
Message-id: 20231012073458.860187-1-thuth@redhat.com
11
base class/subclass setup that mps2-tz.c uses, even though at
12
the moment there's only a single subclass.
13
14
Following commits will add the CPUs and the peripherals.
15
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
13
---
19
---
14
MAINTAINERS | 2 +-
20
MAINTAINERS | 3 +-
15
include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0
21
configs/devices/arm-softmmu/default.mak | 1 +
16
hw/misc/bcm2835_property.c | 2 +-
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
17
3 files changed, 2 insertions(+), 2 deletions(-)
23
hw/arm/Kconfig | 5 +
18
rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)
24
hw/arm/meson.build | 1 +
25
5 files changed, 248 insertions(+), 1 deletion(-)
26
create mode 100644 hw/arm/mps3r.c
19
27
20
diff --git a/MAINTAINERS b/MAINTAINERS
28
diff --git a/MAINTAINERS b/MAINTAINERS
21
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
22
--- a/MAINTAINERS
30
--- a/MAINTAINERS
23
+++ b/MAINTAINERS
31
+++ b/MAINTAINERS
24
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
25
F: hw/arm/raspi.c
33
F: hw/pci-host/designware.c
26
F: hw/arm/raspi_platform.h
34
F: include/hw/pci-host/designware.h
27
F: hw/*/bcm283*
35
28
-F: include/hw/arm/raspi*
36
-MPS2
29
+F: include/hw/arm/rasp*
37
+MPS2 / MPS3
30
F: include/hw/*/bcm283*
38
M: Peter Maydell <peter.maydell@linaro.org>
31
F: docs/system/arm/raspi.rst
39
L: qemu-arm@nongnu.org
32
40
S: Maintained
33
diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/arm/raspberrypi-fw-defs.h
41
F: hw/arm/mps2.c
34
similarity index 100%
42
F: hw/arm/mps2-tz.c
35
rename from include/hw/misc/raspberrypi-fw-defs.h
43
+F: hw/arm/mps3r.c
36
rename to include/hw/arm/raspberrypi-fw-defs.h
44
F: hw/misc/mps2-*.c
37
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
38
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/misc/bcm2835_property.c
49
--- a/configs/devices/arm-softmmu/default.mak
40
+++ b/hw/misc/bcm2835_property.c
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
60
new file mode 100644
61
index XXXXXXX..XXXXXXX
62
--- /dev/null
63
+++ b/hw/arm/mps3r.c
41
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
42
#include "migration/vmstate.h"
65
+/*
43
#include "hw/irq.h"
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
44
#include "hw/misc/bcm2835_mbox_defs.h"
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
45
-#include "hw/misc/raspberrypi-fw-defs.h"
68
+ *
46
+#include "hw/arm/raspberrypi-fw-defs.h"
69
+ * Copyright (c) 2017 Linaro Limited
47
#include "sysemu/dma.h"
70
+ * Written by Peter Maydell
48
#include "qemu/log.h"
71
+ *
49
#include "qemu/module.h"
72
+ * This program is free software; you can redistribute it and/or modify
73
+ * it under the terms of the GNU General Public License version 2 or
74
+ * (at your option) any later version.
75
+ */
76
+
77
+/*
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
79
+ * which use the Cortex-R CPUs. We model these separately from the
80
+ * M-profile images, because on M-profile the FPGA image is based on
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
82
+ * the R-profile FPGA images don't have that abstraction layer.
83
+ *
84
+ * We model the following FPGA images here:
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
86
+ *
87
+ * Application Note AN536:
88
+ * https://developer.arm.com/documentation/dai0536/latest/
89
+ */
90
+
91
+#include "qemu/osdep.h"
92
+#include "qemu/units.h"
93
+#include "qapi/error.h"
94
+#include "exec/address-spaces.h"
95
+#include "cpu.h"
96
+#include "hw/boards.h"
97
+#include "hw/arm/boot.h"
98
+
99
+/* Define the layout of RAM and ROM in a board */
100
+typedef struct RAMInfo {
101
+ const char *name;
102
+ hwaddr base;
103
+ hwaddr size;
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
105
+ int flags;
106
+} RAMInfo;
107
+
108
+/*
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
110
+ * emulation of that much guest RAM, so artificially make it smaller.
111
+ */
112
+#if HOST_LONG_BITS == 32
113
+#define MPS3_DDR_SIZE (1 * GiB)
114
+#else
115
+#define MPS3_DDR_SIZE (3 * GiB)
116
+#endif
117
+
118
+/*
119
+ * Flag values:
120
+ * IS_MAIN: this is the main machine RAM
121
+ * IS_ROM: this area is read-only
122
+ */
123
+#define IS_MAIN 1
124
+#define IS_ROM 2
125
+
126
+#define MPS3R_RAM_MAX 9
127
+
128
+typedef enum MPS3RFPGAType {
129
+ FPGA_AN536,
130
+} MPS3RFPGAType;
131
+
132
+struct MPS3RMachineClass {
133
+ MachineClass parent;
134
+ MPS3RFPGAType fpga_type;
135
+ const RAMInfo *raminfo;
136
+};
137
+
138
+struct MPS3RMachineState {
139
+ MachineState parent;
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
141
+};
142
+
143
+#define TYPE_MPS3R_MACHINE "mps3r"
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
145
+
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
147
+
148
+static const RAMInfo an536_raminfo[] = {
149
+ {
150
+ .name = "ATCM",
151
+ .base = 0x00000000,
152
+ .size = 0x00008000,
153
+ .mrindex = 0,
154
+ }, {
155
+ /* We model the QSPI flash as simple ROM for now */
156
+ .name = "QSPI",
157
+ .base = 0x08000000,
158
+ .size = 0x00800000,
159
+ .flags = IS_ROM,
160
+ .mrindex = 1,
161
+ }, {
162
+ .name = "BRAM",
163
+ .base = 0x10000000,
164
+ .size = 0x00080000,
165
+ .mrindex = 2,
166
+ }, {
167
+ .name = "DDR",
168
+ .base = 0x20000000,
169
+ .size = MPS3_DDR_SIZE,
170
+ .mrindex = -1,
171
+ }, {
172
+ .name = "ATCM0",
173
+ .base = 0xee000000,
174
+ .size = 0x00008000,
175
+ .mrindex = 3,
176
+ }, {
177
+ .name = "BTCM0",
178
+ .base = 0xee100000,
179
+ .size = 0x00008000,
180
+ .mrindex = 4,
181
+ }, {
182
+ .name = "CTCM0",
183
+ .base = 0xee200000,
184
+ .size = 0x00008000,
185
+ .mrindex = 5,
186
+ }, {
187
+ .name = "ATCM1",
188
+ .base = 0xee400000,
189
+ .size = 0x00008000,
190
+ .mrindex = 6,
191
+ }, {
192
+ .name = "BTCM1",
193
+ .base = 0xee500000,
194
+ .size = 0x00008000,
195
+ .mrindex = 7,
196
+ }, {
197
+ .name = "CTCM1",
198
+ .base = 0xee600000,
199
+ .size = 0x00008000,
200
+ .mrindex = 8,
201
+ }, {
202
+ .name = NULL,
203
+ }
204
+};
205
+
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
207
+ const RAMInfo *raminfo)
208
+{
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
210
+ MemoryRegion *ram;
211
+
212
+ if (raminfo->mrindex < 0) {
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
214
+ MachineState *machine = MACHINE(mms);
215
+ assert(!(raminfo->flags & IS_ROM));
216
+ return machine->ram;
217
+ }
218
+
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
220
+ ram = &mms->ram[raminfo->mrindex];
221
+
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
223
+ raminfo->size, &error_fatal);
224
+ if (raminfo->flags & IS_ROM) {
225
+ memory_region_set_readonly(ram, true);
226
+ }
227
+ return ram;
228
+}
229
+
230
+static void mps3r_common_init(MachineState *machine)
231
+{
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
234
+ MemoryRegion *sysmem = get_system_memory();
235
+
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
239
+ }
240
+}
241
+
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
244
+ /*
245
+ * Set mc->default_ram_size and default_ram_id from the
246
+ * information in mmc->raminfo.
247
+ */
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
249
+ const RAMInfo *p;
250
+
251
+ for (p = mmc->raminfo; p->name; p++) {
252
+ if (p->mrindex < 0) {
253
+ /* Found the entry for "system memory" */
254
+ mc->default_ram_size = p->size;
255
+ mc->default_ram_id = p->name;
256
+ return;
257
+ }
258
+ }
259
+ g_assert_not_reached();
260
+}
261
+
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
263
+{
264
+ MachineClass *mc = MACHINE_CLASS(oc);
265
+
266
+ mc->init = mps3r_common_init;
267
+}
268
+
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
270
+{
271
+ MachineClass *mc = MACHINE_CLASS(oc);
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
273
+ static const char * const valid_cpu_types[] = {
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
275
+ NULL
276
+ };
277
+
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
279
+ mc->default_cpus = 2;
280
+ mc->min_cpus = mc->default_cpus;
281
+ mc->max_cpus = mc->default_cpus;
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
283
+ mc->valid_cpu_types = valid_cpu_types;
284
+ mmc->raminfo = an536_raminfo;
285
+ mps3r_set_default_ram_info(mmc);
286
+}
287
+
288
+static const TypeInfo mps3r_machine_types[] = {
289
+ {
290
+ .name = TYPE_MPS3R_MACHINE,
291
+ .parent = TYPE_MACHINE,
292
+ .abstract = true,
293
+ .instance_size = sizeof(MPS3RMachineState),
294
+ .class_size = sizeof(MPS3RMachineClass),
295
+ .class_init = mps3r_class_init,
296
+ }, {
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
298
+ .parent = TYPE_MPS3R_MACHINE,
299
+ .class_init = mps3r_an536_class_init,
300
+ },
301
+};
302
+
303
+DEFINE_TYPES(mps3r_machine_types);
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
305
index XXXXXXX..XXXXXXX 100644
306
--- a/hw/arm/Kconfig
307
+++ b/hw/arm/Kconfig
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
309
select PFLASH_CFI01
310
select SMC91C111
311
312
+config MPS3R
313
+ bool
314
+ default y
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
50
--
332
--
51
2.34.1
333
2.34.1
52
334
53
335
diff view generated by jsdifflib
[PULL 22/24] target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
1
The code for powering on a CPU in arm-powerctl.c has two separate
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
use cases:
2
the mps3-an536 board.
3
* emulation of a real hardware power controller
4
* emulation of firmware interfaces (primarily PSCI) with
5
CPU on/off APIs
6
3
7
For the first case, we only need to reset the CPU and set its
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
starting PC and X0. For the second case, because we're emulating the
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
9
firmware we need to ensure that it's in the state that the firmware
6
---
10
provides. In particular, when we reset to a lower EL than the
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
11
highest one we are emulating, we need to put the CPU into a state
8
1 file changed, 177 insertions(+), 3 deletions(-)
12
that permits correct running at that lower EL. We already do a
13
little of this in arm-powerctl.c (for instance we set SCR_HCE to
14
enable the HVC insn) but we don't do enough of it. This means that
15
in the case where we are emulating EL3 but also providing emulated
16
PSCI the guest will crash when a secondary core tries to use a
17
feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth.
18
9
19
The hw/arm/boot.c code also has to support this "start guest code in
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
20
an EL that's lower than the highest emulated EL" case in order to do
21
direct guest kernel booting; it has all the necessary initialization
22
code to set the SCR_EL3 bits. Pull the relevant boot.c code out into
23
a separate function so we can share it between there and
24
arm-powerctl.c.
25
26
This refactoring has a few code changes that look like they
27
might be behaviour changes but aren't:
28
* if info->secure_boot is false and info->secure_board_setup is
29
true, then the old code would start the first CPU in Hyp
30
mode but without changing SCR.NS and NSACR.{CP11,CP10}.
31
This was wrong behaviour because there's no such thing
32
as Secure Hyp mode. The new code will leave the CPU in SVC.
33
(There is no board which sets secure_boot to false and
34
secure_board_setup to true, so this isn't a behaviour
35
change for any of our boards.)
36
* we don't explicitly clear SCR.NS when arm-powerctl.c
37
does a CPU-on to EL3. This was a no-op because CPU reset
38
will reset to NS == 0.
39
40
And some real behaviour changes:
41
* we no longer set HCR_EL2.RW when booting into EL2: the guest
42
can and should do that themselves before dropping into their
43
EL1 code. (arm-powerctl and boot did this differently; I
44
opted to use the logic from arm-powerctl, which only sets
45
HCR_EL2.RW when it's directly starting the guest in EL1,
46
because it's more correct, and I don't expect guests to be
47
accidentally depending on our having set the RW bit for them.)
48
* if we are booting a CPU into AArch32 Secure SVC then we won't
49
set SCR.HCE any more. This affects only the vexpress-a15 and
50
raspi2b machine types. Guests booting in this case will either:
51
- be able to set SCR.HCE themselves as part of moving from
52
Secure SVC into NS Hyp mode
53
- will move from Secure SVC to NS SVC, and won't care about
54
behaviour of the HVC insn
55
- will stay in Secure SVC, and won't care about HVC
56
* on an arm-powerctl CPU-on we will now set the SCR bits for
57
pauth/mte/sve/sme/hcx/fgt features
58
59
The first two of these are very minor and I don't expect guest
60
code to trip over them, so I didn't judge it worth convoluting
61
the code in an attempt to keep exactly the same boot.c behaviour.
62
The third change fixes issue 1899.
63
64
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899
65
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
66
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
67
Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org
68
---
69
target/arm/cpu.h | 22 +++++++++
70
hw/arm/boot.c | 95 ++++++++++-----------------------------
71
target/arm/arm-powerctl.c | 53 +---------------------
72
target/arm/cpu.c | 95 +++++++++++++++++++++++++++++++++++++++
73
4 files changed, 141 insertions(+), 124 deletions(-)
74
75
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
76
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/cpu.h
12
--- a/hw/arm/mps3r.c
78
+++ b/target/arm/cpu.h
13
+++ b/hw/arm/mps3r.c
79
@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
14
@@ -XXX,XX +XXX,XX @@
80
int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
15
#include "qemu/osdep.h"
81
int cpuid, DumpState *s);
16
#include "qemu/units.h"
82
17
#include "qapi/error.h"
83
+/**
18
+#include "qapi/qmp/qlist.h"
84
+ * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
19
#include "exec/address-spaces.h"
85
+ * @cpu: CPU (which must have been freshly reset)
20
#include "cpu.h"
86
+ * @target_el: exception level to put the CPU into
21
#include "hw/boards.h"
87
+ * @secure: whether to put the CPU in secure state
22
+#include "hw/qdev-properties.h"
23
#include "hw/arm/boot.h"
24
+#include "hw/arm/bsa.h"
25
+#include "hw/intc/arm_gicv3.h"
26
27
/* Define the layout of RAM and ROM in a board */
28
typedef struct RAMInfo {
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
30
#define IS_ROM 2
31
32
#define MPS3R_RAM_MAX 9
33
+#define MPS3R_CPU_MAX 2
34
+
35
+#define PERIPHBASE 0xf0000000
36
+#define NUM_SPIS 96
37
38
typedef enum MPS3RFPGAType {
39
FPGA_AN536,
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
41
MachineClass parent;
42
MPS3RFPGAType fpga_type;
43
const RAMInfo *raminfo;
44
+ hwaddr loader_start;
45
};
46
47
struct MPS3RMachineState {
48
MachineState parent;
49
+ struct arm_boot_info bootinfo;
50
MemoryRegion ram[MPS3R_RAM_MAX];
51
+ Object *cpu[MPS3R_CPU_MAX];
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
55
+ GICv3State gic;
56
};
57
58
#define TYPE_MPS3R_MACHINE "mps3r"
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
60
return ram;
61
}
62
63
+/*
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
65
+ * because real hardware has a restriction that atomic operations between
66
+ * the two CPUs do not function correctly, and so true SMP is not
67
+ * possible. Therefore for cases where the user is directly booting
68
+ * a kernel, we treat the system as essentially uniprocessor, and
69
+ * put the secondary CPU into power-off state (as if the user on the
70
+ * real hardware had configured the secondary to be halted via the
71
+ * SCC config registers).
88
+ *
72
+ *
89
+ * When QEMU is directly running a guest kernel at a lower level than
73
+ * Note that the default secondary boot code would not work here anyway
90
+ * EL3 it implicitly emulates some aspects of the guest firmware.
74
+ * as it assumes a GICv2, and we have a GICv3.
91
+ * This includes that on reset we need to configure the parts of the
92
+ * CPU corresponding to EL3 so that the real guest code can run at its
93
+ * lower exception level. This function does that post-reset CPU setup,
94
+ * for when we do direct boot of a guest kernel, and for when we
95
+ * emulate PSCI and similar firmware interfaces starting a CPU at a
96
+ * lower exception level.
97
+ *
98
+ * @target_el must be an EL implemented by the CPU between 1 and 3.
99
+ * We do not support dropping into a Secure EL other than 3.
100
+ *
101
+ * It is the responsibility of the caller to call arm_rebuild_hflags().
102
+ */
75
+ */
103
+void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
104
+
77
+ const struct arm_boot_info *info)
105
#ifdef TARGET_AARCH64
106
int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
107
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
108
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/arm/boot.c
111
+++ b/hw/arm/boot.c
112
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
113
114
cpu_set_pc(cs, entry);
115
} else {
116
- /* If we are booting Linux then we need to check whether we are
117
- * booting into secure or non-secure state and adjust the state
118
- * accordingly. Out of reset, ARM is defined to be in secure state
119
- * (SCR.NS = 0), we change that here if non-secure boot has been
120
- * requested.
121
+ /*
122
+ * If we are booting Linux then we might need to do so at:
123
+ * - AArch64 NS EL2 or NS EL1
124
+ * - AArch32 Secure SVC (EL3)
125
+ * - AArch32 NS Hyp (EL2)
126
+ * - AArch32 NS SVC (EL1)
127
+ * Configure the CPU in the way boot firmware would do to
128
+ * drop us down to the appropriate level.
129
*/
130
- if (arm_feature(env, ARM_FEATURE_EL3)) {
131
- /* AArch64 is defined to come out of reset into EL3 if enabled.
132
- * If we are booting Linux then we need to adjust our EL as
133
- * Linux expects us to be in EL2 or EL1. AArch32 resets into
134
- * SVC, which Linux expects, so no privilege/exception level to
135
- * adjust.
136
- */
137
- if (env->aarch64) {
138
- env->cp15.scr_el3 |= SCR_RW;
139
- if (arm_feature(env, ARM_FEATURE_EL2)) {
140
- env->cp15.hcr_el2 |= HCR_RW;
141
- env->pstate = PSTATE_MODE_EL2h;
142
- } else {
143
- env->pstate = PSTATE_MODE_EL1h;
144
- }
145
- if (cpu_isar_feature(aa64_pauth, cpu)) {
146
- env->cp15.scr_el3 |= SCR_API | SCR_APK;
147
- }
148
- if (cpu_isar_feature(aa64_mte, cpu)) {
149
- env->cp15.scr_el3 |= SCR_ATA;
150
- }
151
- if (cpu_isar_feature(aa64_sve, cpu)) {
152
- env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
153
- env->vfp.zcr_el[3] = 0xf;
154
- }
155
- if (cpu_isar_feature(aa64_sme, cpu)) {
156
- env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
157
- env->cp15.scr_el3 |= SCR_ENTP2;
158
- env->vfp.smcr_el[3] = 0xf;
159
- }
160
- if (cpu_isar_feature(aa64_hcx, cpu)) {
161
- env->cp15.scr_el3 |= SCR_HXEN;
162
- }
163
- if (cpu_isar_feature(aa64_fgt, cpu)) {
164
- env->cp15.scr_el3 |= SCR_FGTEN;
165
- }
166
+ int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
167
168
- /* AArch64 kernels never boot in secure mode */
169
- assert(!info->secure_boot);
170
- /* This hook is only supported for AArch32 currently:
171
- * bootloader_aarch64[] will not call the hook, and
172
- * the code above has already dropped us into EL2 or EL1.
173
- */
174
- assert(!info->secure_board_setup);
175
- }
176
-
177
- if (arm_feature(env, ARM_FEATURE_EL2)) {
178
- /* If we have EL2 then Linux expects the HVC insn to work */
179
- env->cp15.scr_el3 |= SCR_HCE;
180
- }
181
-
182
- /* Set to non-secure if not a secure boot */
183
- if (!info->secure_boot &&
184
- (cs != first_cpu || !info->secure_board_setup)) {
185
- /* Linux expects non-secure state */
186
- env->cp15.scr_el3 |= SCR_NS;
187
- /* Set NSACR.{CP11,CP10} so NS can access the FPU */
188
- env->cp15.nsacr |= 3 << 10;
189
- }
190
- }
191
-
192
- if (!env->aarch64 && !info->secure_boot &&
193
- arm_feature(env, ARM_FEATURE_EL2)) {
194
+ if (env->aarch64) {
195
/*
196
- * This is an AArch32 boot not to Secure state, and
197
- * we have Hyp mode available, so boot the kernel into
198
- * Hyp mode. This is not how the CPU comes out of reset,
199
- * so we need to manually put it there.
200
+ * AArch64 kernels never boot in secure mode, and we don't
201
+ * support the secure_board_setup hook for AArch64.
202
*/
203
- cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
204
+ assert(!info->secure_boot);
205
+ assert(!info->secure_board_setup);
206
+ } else {
207
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
208
+ (info->secure_boot ||
209
+ (info->secure_board_setup && cs == first_cpu))) {
210
+ /* Start this CPU in Secure SVC */
211
+ target_el = 3;
212
+ }
213
}
214
215
+ arm_emulate_firmware_reset(cs, target_el);
216
+
217
if (cs == first_cpu) {
218
AddressSpace *as = arm_boot_address_space(cpu, info);
219
220
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
221
index XXXXXXX..XXXXXXX 100644
222
--- a/target/arm/arm-powerctl.c
223
+++ b/target/arm/arm-powerctl.c
224
@@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
225
226
/* Initialize the cpu we are turning on */
227
cpu_reset(target_cpu_state);
228
+ arm_emulate_firmware_reset(target_cpu_state, info->target_el);
229
target_cpu_state->halted = 0;
230
231
- if (info->target_aa64) {
232
- if ((info->target_el < 3) && arm_feature(&target_cpu->env,
233
- ARM_FEATURE_EL3)) {
234
- /*
235
- * As target mode is AArch64, we need to set lower
236
- * exception level (the requested level 2) to AArch64
237
- */
238
- target_cpu->env.cp15.scr_el3 |= SCR_RW;
239
- }
240
-
241
- if ((info->target_el < 2) && arm_feature(&target_cpu->env,
242
- ARM_FEATURE_EL2)) {
243
- /*
244
- * As target mode is AArch64, we need to set lower
245
- * exception level (the requested level 1) to AArch64
246
- */
247
- target_cpu->env.cp15.hcr_el2 |= HCR_RW;
248
- }
249
-
250
- target_cpu->env.pstate = aarch64_pstate_mode(info->target_el, true);
251
- } else {
252
- /* We are requested to boot in AArch32 mode */
253
- static const uint32_t mode_for_el[] = { 0,
254
- ARM_CPU_MODE_SVC,
255
- ARM_CPU_MODE_HYP,
256
- ARM_CPU_MODE_SVC };
257
-
258
- cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M,
259
- CPSRWriteRaw);
260
- }
261
-
262
- if (info->target_el == 3) {
263
- /* Processor is in secure mode */
264
- target_cpu->env.cp15.scr_el3 &= ~SCR_NS;
265
- } else {
266
- /* Processor is not in secure mode */
267
- target_cpu->env.cp15.scr_el3 |= SCR_NS;
268
-
269
- /* Set NSACR.{CP11,CP10} so NS can access the FPU */
270
- target_cpu->env.cp15.nsacr |= 3 << 10;
271
-
272
- /*
273
- * If QEMU is providing the equivalent of EL3 firmware, then we need
274
- * to make sure a CPU targeting EL2 comes out of reset with a
275
- * functional HVC insn.
276
- */
277
- if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3)
278
- && info->target_el == 2) {
279
- target_cpu->env.cp15.scr_el3 |= SCR_HCE;
280
- }
281
- }
282
-
283
/* We check if the started CPU is now at the correct level */
284
assert(info->target_el == arm_current_el(&target_cpu->env));
285
286
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
287
index XXXXXXX..XXXXXXX 100644
288
--- a/target/arm/cpu.c
289
+++ b/target/arm/cpu.c
290
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
291
}
292
}
293
294
+void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
295
+{
78
+{
296
+ ARMCPU *cpu = ARM_CPU(cpustate);
297
+ CPUARMState *env = &cpu->env;
298
+ bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
299
+ bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
300
+
301
+ /*
79
+ /*
302
+ * Check we have the EL we're aiming for. If that is the
80
+ * Power the secondary CPU off. This means we don't need to write any
303
+ * highest implemented EL, then cpu_reset has already done
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
304
+ * all the work.
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
305
+ */
85
+ */
306
+ switch (target_el) {
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
307
+ case 3:
87
+ if (cs != first_cpu) {
308
+ assert(have_el3);
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
309
+ return;
89
+ &error_abort);
310
+ case 2:
311
+ assert(have_el2);
312
+ if (!have_el3) {
313
+ return;
314
+ }
315
+ break;
316
+ case 1:
317
+ if (!have_el3 && !have_el2) {
318
+ return;
319
+ }
320
+ break;
321
+ default:
322
+ g_assert_not_reached();
323
+ }
324
+
325
+ if (have_el3) {
326
+ /*
327
+ * Set the EL3 state so code can run at EL2. This should match
328
+ * the requirements set by Linux in its booting spec.
329
+ */
330
+ if (env->aarch64) {
331
+ env->cp15.scr_el3 |= SCR_RW;
332
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
333
+ env->cp15.scr_el3 |= SCR_API | SCR_APK;
334
+ }
335
+ if (cpu_isar_feature(aa64_mte, cpu)) {
336
+ env->cp15.scr_el3 |= SCR_ATA;
337
+ }
338
+ if (cpu_isar_feature(aa64_sve, cpu)) {
339
+ env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
340
+ env->vfp.zcr_el[3] = 0xf;
341
+ }
342
+ if (cpu_isar_feature(aa64_sme, cpu)) {
343
+ env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
344
+ env->cp15.scr_el3 |= SCR_ENTP2;
345
+ env->vfp.smcr_el[3] = 0xf;
346
+ }
347
+ if (cpu_isar_feature(aa64_hcx, cpu)) {
348
+ env->cp15.scr_el3 |= SCR_HXEN;
349
+ }
350
+ if (cpu_isar_feature(aa64_fgt, cpu)) {
351
+ env->cp15.scr_el3 |= SCR_FGTEN;
352
+ }
353
+ }
354
+
355
+ if (target_el == 2) {
356
+ /* If the guest is at EL2 then Linux expects the HVC insn to work */
357
+ env->cp15.scr_el3 |= SCR_HCE;
358
+ }
359
+
360
+ /* Put CPU into non-secure state */
361
+ env->cp15.scr_el3 |= SCR_NS;
362
+ /* Set NSACR.{CP11,CP10} so NS can access the FPU */
363
+ env->cp15.nsacr |= 3 << 10;
364
+ }
365
+
366
+ if (have_el2 && target_el < 2) {
367
+ /* Set EL2 state so code can run at EL1. */
368
+ if (env->aarch64) {
369
+ env->cp15.hcr_el2 |= HCR_RW;
370
+ }
90
+ }
371
+ }
91
+ }
372
+
92
+}
373
+ /* Set the CPU to the desired state */
93
+
374
+ if (env->aarch64) {
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
375
+ env->pstate = aarch64_pstate_mode(target_el, true);
95
+ const struct arm_boot_info *info)
376
+ } else {
96
+{
377
+ static const uint32_t mode_for_el[] = {
97
+ /* We don't need to do anything here because the CPU will be off */
378
+ 0,
98
+}
379
+ ARM_CPU_MODE_SVC,
99
+
380
+ ARM_CPU_MODE_HYP,
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
381
+ ARM_CPU_MODE_SVC,
101
+{
102
+ MachineState *machine = MACHINE(mms);
103
+ DeviceState *gicdev;
104
+ QList *redist_region_count;
105
+
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
107
+ gicdev = DEVICE(&mms->gic);
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
110
+ redist_region_count = qlist_new();
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
114
+ OBJECT(sysmem), &error_fatal);
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
118
+ /*
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
122
+ */
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
127
+ int irq;
128
+ /*
129
+ * Mapping from the output timer irq lines from the CPU to the
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
131
+ * but it uses the standard convention for the PPI numbers.
132
+ */
133
+ const int timer_irq[] = {
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
382
+ };
137
+ };
383
+
138
+
384
+ cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
143
+ }
144
+
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
146
+ qdev_get_gpio_in(gicdev,
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
148
+
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
+ qdev_get_gpio_in(gicdev,
151
+ intidbase + VIRTUAL_PMU_IRQ));
152
+
153
+ sysbus_connect_irq(gicsbd, i,
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
385
+ }
161
+ }
386
+}
162
+}
387
+
163
+
388
+
164
static void mps3r_common_init(MachineState *machine)
389
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
165
{
390
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
391
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
169
memory_region_add_subregion(sysmem, ri->base, mr);
170
}
171
+
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
177
+
178
+ /*
179
+ * Each CPU has some private RAM/peripherals, so create the container
180
+ * which will house those, with the whole-machine system memory being
181
+ * used where there's no CPU-specific device. Note that we need the
182
+ * sysmem_alias aliases because we can't put one MR (the original
183
+ * 'sysmem') into more than one other MR.
184
+ */
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
186
+ sysmem_name, UINT64_MAX);
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
188
+ alias_name, sysmem, 0, UINT64_MAX);
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
190
+ &mms->sysmem_alias[i], -1);
191
+
192
+ mms->cpu[i] = object_new(machine->cpu_type);
193
+ object_property_set_link(mms->cpu[i], "memory",
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
196
+ PERIPHBASE, &error_abort);
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
198
+ object_unref(mms->cpu[i]);
199
+
200
+ /* Per-CPU RAM */
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
205
+ }
206
+
207
+ create_gic(mms, sysmem);
208
+
209
+ mms->bootinfo.ram_size = machine->ram_size;
210
+ mms->bootinfo.board_id = -1;
211
+ mms->bootinfo.loader_start = mmc->loader_start;
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
215
}
216
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
219
/* Found the entry for "system memory" */
220
mc->default_ram_size = p->size;
221
mc->default_ram_id = p->name;
222
+ mmc->loader_start = p->base;
223
return;
224
}
225
}
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
227
};
228
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
230
- mc->default_cpus = 2;
231
- mc->min_cpus = mc->default_cpus;
232
- mc->max_cpus = mc->default_cpus;
233
+ /*
234
+ * In the real FPGA image there are always two cores, but the standard
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
236
+ * that the second core is held in reset and halted. Many images built for
237
+ * the board do not expect the second core to run at startup (especially
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
240
+ *
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
242
+ * with the default being -smp 1. This seems a more intuitive UI for
243
+ * QEMU users than, for instance, having a machine property to allow
244
+ * the user to set the initial value of the SYSCON 0x000 register.
245
+ */
246
+ mc->default_cpus = 1;
247
+ mc->min_cpus = 1;
248
+ mc->max_cpus = 2;
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
250
mc->valid_cpu_types = valid_cpu_types;
251
mmc->raminfo = an536_raminfo;
392
--
252
--
393
2.34.1
253
2.34.1
diff view generated by jsdifflib
[PULL 15/24] target/arm: Permit T32 LDM with single register
[PULL 32/35] hw/arm/mps3r: Add UARTs
1
For the Thumb T32 encoding of LDM, if only a single register is
1
This board has a lot of UARTs: there is one UART per CPU in the
2
specified in the register list this instruction is UNPREDICTABLE,
2
per-CPU peripheral part of the address map, whose interrupts are
3
with the following choices:
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
* instruction UNDEFs
4
normal part of the peripheral space, whose interrupts are shared
5
* instruction is a NOP
5
peripheral interrupts.
6
* instruction loads a single register
7
* instruction loads an unspecified set of registers
8
6
9
Currently we choose to UNDEF (a behaviour chosen in commit
7
Connect and wire them all up; this involves some OR gates where
10
4b222545dbf30 in 2019; previously we treated it as "load the
8
multiple overflow interrupts are wired into one GIC input.
11
specified single register").
12
9
13
Unfortunately there is real world code out there (which shipped in at
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
least Android 11, 12 and 13) which incorrectly uses this
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
UNPREDICTABLE insn on the assumption that it does a single register
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
16
load, which is (presumably) what it happens to do on real hardware,
13
---
17
and is also what it does on the equivalent A32 encoding.
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
15
1 file changed, 94 insertions(+)
18
16
19
Revert to the pre-4b222545dbf30 behaviour of not UNDEFing
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
20
for this T32 encoding.
21
22
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1799
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20230927101853.39288-1-peter.maydell@linaro.org
27
---
28
target/arm/tcg/translate.c | 37 +++++++++++++++++++++++--------------
29
1 file changed, 23 insertions(+), 14 deletions(-)
30
31
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
32
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/translate.c
19
--- a/hw/arm/mps3r.c
34
+++ b/target/arm/tcg/translate.c
20
+++ b/hw/arm/mps3r.c
35
@@ -XXX,XX +XXX,XX @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a,
21
@@ -XXX,XX +XXX,XX @@
22
#include "qapi/qmp/qlist.h"
23
#include "exec/address-spaces.h"
24
#include "cpu.h"
25
+#include "sysemu/sysemu.h"
26
#include "hw/boards.h"
27
+#include "hw/or-irq.h"
28
#include "hw/qdev-properties.h"
29
#include "hw/arm/boot.h"
30
#include "hw/arm/bsa.h"
31
+#include "hw/char/cmsdk-apb-uart.h"
32
#include "hw/intc/arm_gicv3.h"
33
34
/* Define the layout of RAM and ROM in a board */
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
36
37
#define MPS3R_RAM_MAX 9
38
#define MPS3R_CPU_MAX 2
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
40
41
#define PERIPHBASE 0xf0000000
42
#define NUM_SPIS 96
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
46
GICv3State gic;
47
+ /* per-CPU UARTs followed by the shared UARTs */
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
50
+ OrIRQState uart_oflow;
51
};
52
53
#define TYPE_MPS3R_MACHINE "mps3r"
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
55
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
57
58
+/*
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
61
+ * model we just roll them all into one.
62
+ */
63
+#define CLK_FRQ 50000000
64
+
65
static const RAMInfo an536_raminfo[] = {
66
{
67
.name = "ATCM",
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
36
}
69
}
37
}
70
}
38
71
39
-static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
72
+/*
40
+static bool op_stm(DisasContext *s, arg_ldst_block *a)
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
75
+ */
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
79
+ qemu_irq combirq)
80
+{
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
82
+ SysBusDevice *sbd;
83
+
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
86
+ TYPE_CMSDK_APB_UART);
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
90
+ sysbus_realize(sbd, &error_fatal);
91
+ memory_region_add_subregion(mem, baseaddr,
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
98
+}
99
+
100
static void mps3r_common_init(MachineState *machine)
41
{
101
{
42
int i, j, n, list, mem_idx;
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
43
bool user = a->u;
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
44
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
104
MemoryRegion *sysmem = get_system_memory();
45
105
+ DeviceState *gicdev;
46
list = a->list;
106
47
n = ctpop16(list);
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
48
- if (n < min_n || a->rn == 15) {
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
110
}
111
112
create_gic(mms, sysmem);
113
+ gicdev = DEVICE(&mms->gic);
114
+
49
+ /*
115
+ /*
50
+ * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
51
+ * to UNDEF. In the T32 STM encoding n == 1 is also UNPREDICTABLE,
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
52
+ * but hardware treats it like the A32 version and implements the
53
+ * single-register-store, and some in-the-wild (buggy) software
54
+ * assumes that, so we don't UNDEF on that case.
55
+ */
118
+ */
56
+ if (n < 1 || a->rn == 15) {
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
57
unallocated_encoding(s);
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
58
return true;
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
59
}
122
+ DeviceState *orgate;
60
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
123
+
61
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
62
static bool trans_STM(DisasContext *s, arg_ldst_block *a)
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
63
{
126
+ TYPE_OR_IRQ);
64
- /* BitCount(list) < 1 is UNPREDICTABLE */
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
65
- return op_stm(s, a, 1);
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
66
+ return op_stm(s, a);
129
+ qdev_realize(orgate, NULL, &error_fatal);
67
}
130
+ qdev_connect_gpio_out(orgate, 0,
68
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
69
static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
132
+
70
@@ -XXX,XX +XXX,XX @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
71
unallocated_encoding(s);
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
72
return true;
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
73
}
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
74
- /* BitCount(list) < 2 is UNPREDICTABLE */
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
75
- return op_stm(s, a, 2);
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
76
+ return op_stm(s, a);
139
+ }
77
}
78
79
-static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
80
+static bool do_ldm(DisasContext *s, arg_ldst_block *a)
81
{
82
int i, j, n, list, mem_idx;
83
bool loaded_base;
84
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
85
86
list = a->list;
87
n = ctpop16(list);
88
- if (n < min_n || a->rn == 15) {
89
+ /*
140
+ /*
90
+ * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
91
+ * to UNDEF. In the T32 LDM encoding n == 1 is also UNPREDICTABLE,
142
+ * together into IRQ 17
92
+ * but hardware treats it like the A32 version and implements the
93
+ * single-register-load, and some in-the-wild (buggy) software
94
+ * assumes that, so we don't UNDEF on that case.
95
+ */
143
+ */
96
+ if (n < 1 || a->rn == 15) {
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
97
unallocated_encoding(s);
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
98
return true;
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
99
}
147
+ MPS3R_UART_MAX * 2);
100
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a)
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
101
unallocated_encoding(s);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
102
return true;
150
+ qdev_get_gpio_in(gicdev, 17));
103
}
151
+
104
- /* BitCount(list) < 1 is UNPREDICTABLE */
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
105
- return do_ldm(s, a, 1);
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
106
+ return do_ldm(s, a);
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
107
}
155
+
108
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
109
static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
157
+ qdev_get_gpio_in(gicdev, txirq),
110
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
158
+ qdev_get_gpio_in(gicdev, rxirq),
111
unallocated_encoding(s);
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
112
return true;
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
113
}
161
+ qdev_get_gpio_in(gicdev, combirq));
114
- /* BitCount(list) < 2 is UNPREDICTABLE */
162
+ }
115
- return do_ldm(s, a, 2);
163
116
+ return do_ldm(s, a);
164
mms->bootinfo.ram_size = machine->ram_size;
117
}
165
mms->bootinfo.board_id = -1;
118
119
static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
120
{
121
/* Writeback is conditional on the base register not being loaded. */
122
a->w = !(a->list & (1 << a->rn));
123
- /* BitCount(list) < 1 is UNPREDICTABLE */
124
- return do_ldm(s, a, 1);
125
+ return do_ldm(s, a);
126
}
127
128
static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
129
--
166
--
130
2.34.1
167
2.34.1
131
168
132
169
diff view generated by jsdifflib
[PULL 08/24] elf2dmp: check array bounds in pdb_get_file_size
[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
1
From: Viktor Prutyanov <viktor@daynix.com>
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
board. These are all simple devices that just need to be created and
3
wired up.
2
4
3
Index in file_size array must be checked against num_files, because the
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
entries we are looking for may be absent in the PDB.
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
8
---
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 59 insertions(+)
5
11
6
Fixes: Coverity CID 1521597
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
7
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
8
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20230930235317.11469-3-viktor@daynix.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
contrib/elf2dmp/pdb.c | 13 +++++++++----
14
1 file changed, 9 insertions(+), 4 deletions(-)
15
16
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/contrib/elf2dmp/pdb.c
14
--- a/hw/arm/mps3r.c
19
+++ b/contrib/elf2dmp/pdb.c
15
+++ b/hw/arm/mps3r.c
20
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
21
17
#include "sysemu/sysemu.h"
22
static uint32_t pdb_get_file_size(const struct pdb_reader *r, unsigned idx)
18
#include "hw/boards.h"
23
{
19
#include "hw/or-irq.h"
24
+ if (idx >= r->ds.toc->num_files) {
20
+#include "hw/qdev-clock.h"
25
+ return 0;
21
#include "hw/qdev-properties.h"
22
#include "hw/arm/boot.h"
23
#include "hw/arm/bsa.h"
24
#include "hw/char/cmsdk-apb-uart.h"
25
+#include "hw/i2c/arm_sbcon_i2c.h"
26
#include "hw/intc/arm_gicv3.h"
27
+#include "hw/misc/unimp.h"
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
30
31
/* Define the layout of RAM and ROM in a board */
32
typedef struct RAMInfo {
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
36
OrIRQState uart_oflow;
37
+ CMSDKAPBWatchdog watchdog;
38
+ CMSDKAPBDualTimer dualtimer;
39
+ ArmSbconI2CState i2c[5];
40
+ Clock *clk;
41
};
42
43
#define TYPE_MPS3R_MACHINE "mps3r"
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
45
MemoryRegion *sysmem = get_system_memory();
46
DeviceState *gicdev;
47
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
49
+ clock_set_hz(mms->clk, CLK_FRQ);
50
+
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
53
memory_region_add_subregion(sysmem, ri->base, mr);
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
55
qdev_get_gpio_in(gicdev, combirq));
56
}
57
58
+ for (int i = 0; i < 4; i++) {
59
+ /* CMSDK GPIO controllers */
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
26
+ }
62
+ }
27
+
63
+
28
return r->ds.toc->file_size[idx];
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
29
}
65
+ TYPE_CMSDK_APB_WATCHDOG);
30
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
31
@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read_file(struct pdb_reader* r, uint32_t file_number)
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
32
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
33
static int pdb_init_segments(struct pdb_reader *r)
69
+ qdev_get_gpio_in(gicdev, 0));
34
{
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
35
- char *segs;
71
+
36
unsigned stream_idx = r->segments;
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
37
73
+ TYPE_CMSDK_APB_DUALTIMER);
38
- segs = pdb_ds_read_file(r, stream_idx);
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
39
- if (!segs) {
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
40
+ r->segs = pdb_ds_read_file(r, stream_idx);
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
41
+ if (!r->segs) {
77
+ qdev_get_gpio_in(gicdev, 3));
42
return 1;
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
43
}
79
+ qdev_get_gpio_in(gicdev, 1));
44
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
45
- r->segs = segs;
81
+ qdev_get_gpio_in(gicdev, 2));
46
r->segs_size = pdb_get_file_size(r, stream_idx);
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
47
+ if (!r->segs_size) {
83
+
48
+ return 1;
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
86
+ 0xe0103000, /* Audio */
87
+ 0xe0107000, /* Shield0 */
88
+ 0xe0108000, /* Shield1 */
89
+ 0xe0109000}; /* DDR4 EEPROM */
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
91
+
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
93
+ TYPE_ARM_SBCON_I2C);
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
96
+ if (i != 2 && i != 3) {
97
+ /*
98
+ * internal-only bus: mark it full to avoid user-created
99
+ * i2c devices being plugged into it.
100
+ */
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
102
+ }
49
+ }
103
+ }
50
104
+
51
return 0;
105
mms->bootinfo.ram_size = machine->ram_size;
52
}
106
mms->bootinfo.board_id = -1;
107
mms->bootinfo.loader_start = mmc->loader_start;
53
--
108
--
54
2.34.1
109
2.34.1
55
110
56
111
diff view generated by jsdifflib
[PULL 14/24] arm/kvm: convert to kvm_get_one_reg
[PULL 34/35] hw/arm/mps3r: Add remaining devices
1
From: Cornelia Huck <cohuck@redhat.com>
1
Add the remaining devices (or unimplemented-device stubs) for
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
QSPI write-config block, and ethernet.
2
4
3
We can neaten the code by switching the callers that work on a
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
CPUstate to the kvm_get_one_reg function.
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
8
---
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 74 insertions(+)
5
11
6
Reviewed-by: Gavin Shan <gshan@redhat.com>
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
7
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20231010142453.224369-3-cohuck@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/kvm.c | 15 +++---------
14
target/arm/kvm64.c | 57 ++++++++++++----------------------------------
15
2 files changed, 18 insertions(+), 54 deletions(-)
16
17
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/kvm.c
14
--- a/hw/arm/mps3r.c
20
+++ b/target/arm/kvm.c
15
+++ b/hw/arm/mps3r.c
21
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
16
@@ -XXX,XX +XXX,XX @@
22
bool ok = true;
17
#include "hw/char/cmsdk-apb-uart.h"
23
18
#include "hw/i2c/arm_sbcon_i2c.h"
24
for (i = 0; i < cpu->cpreg_array_len; i++) {
19
#include "hw/intc/arm_gicv3.h"
25
- struct kvm_one_reg r;
20
+#include "hw/misc/mps2-scc.h"
26
uint64_t regidx = cpu->cpreg_indexes[i];
21
+#include "hw/misc/mps2-fpgaio.h"
27
uint32_t v32;
22
#include "hw/misc/unimp.h"
28
int ret;
23
+#include "hw/net/lan9118.h"
29
24
+#include "hw/rtc/pl031.h"
30
- r.id = regidx;
25
+#include "hw/ssi/pl022.h"
31
-
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
32
switch (regidx & KVM_REG_SIZE_MASK) {
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
33
case KVM_REG_SIZE_U32:
28
34
- r.addr = (uintptr_t)&v32;
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
35
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
30
CMSDKAPBWatchdog watchdog;
36
+ ret = kvm_get_one_reg(cs, regidx, &v32);
31
CMSDKAPBDualTimer dualtimer;
37
if (!ret) {
32
ArmSbconI2CState i2c[5];
38
cpu->cpreg_values[i] = v32;
33
+ PL022State spi[3];
39
}
34
+ MPS2SCC scc;
40
break;
35
+ MPS2FPGAIO fpgaio;
41
case KVM_REG_SIZE_U64:
36
+ UnimplementedDeviceState i2s_audio;
42
- r.addr = (uintptr_t)(cpu->cpreg_values + i);
37
+ PL031State rtc;
43
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
38
Clock *clk;
44
+ ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i);
39
};
45
break;
40
46
default:
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
47
g_assert_not_reached();
42
}
48
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
43
};
49
void kvm_arm_get_virtual_time(CPUState *cs)
44
45
+static const int an536_oscclk[] = {
46
+ 24000000, /* 24MHz reference for RTC and timers */
47
+ 50000000, /* 50MHz ACLK */
48
+ 50000000, /* 50MHz MCLK */
49
+ 50000000, /* 50MHz GPUCLK */
50
+ 24576000, /* 24.576MHz AUDCLK */
51
+ 23750000, /* 23.75MHz HDLCDCLK */
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
53
+};
54
+
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
56
const RAMInfo *raminfo)
50
{
57
{
51
ARMCPU *cpu = ARM_CPU(cs);
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
52
- struct kvm_one_reg reg = {
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
53
- .id = KVM_REG_ARM_TIMER_CNT,
60
MemoryRegion *sysmem = get_system_memory();
54
- .addr = (uintptr_t)&cpu->kvm_vtime,
61
DeviceState *gicdev;
55
- };
62
+ QList *oscclk;
56
int ret;
63
57
64
mms->clk = clock_new(OBJECT(machine), "CLK");
58
if (cpu->kvm_vtime_dirty) {
65
clock_set_hz(mms->clk, CLK_FRQ);
59
return;
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
60
}
61
62
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
63
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
64
if (ret) {
65
error_report("Failed to get KVM_REG_ARM_TIMER_CNT");
66
abort();
67
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/kvm64.c
70
+++ b/target/arm/kvm64.c
71
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
72
static int kvm_arch_get_fpsimd(CPUState *cs)
73
{
74
CPUARMState *env = &ARM_CPU(cs)->env;
75
- struct kvm_one_reg reg;
76
int i, ret;
77
78
for (i = 0; i < 32; i++) {
79
uint64_t *q = aa64_vfp_qreg(env, i);
80
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
81
- reg.addr = (uintptr_t)q;
82
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
83
+ ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
84
if (ret) {
85
return ret;
86
} else {
87
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
88
{
89
ARMCPU *cpu = ARM_CPU(cs);
90
CPUARMState *env = &cpu->env;
91
- struct kvm_one_reg reg;
92
uint64_t *r;
93
int n, ret;
94
95
for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
96
r = &env->vfp.zregs[n].d[0];
97
- reg.addr = (uintptr_t)r;
98
- reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
99
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
100
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
101
if (ret) {
102
return ret;
103
}
104
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
105
106
for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
107
r = &env->vfp.pregs[n].p[0];
108
- reg.addr = (uintptr_t)r;
109
- reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
110
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
111
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
112
if (ret) {
113
return ret;
114
}
115
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
116
}
117
118
r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
119
- reg.addr = (uintptr_t)r;
120
- reg.id = KVM_REG_ARM64_SVE_FFR(0);
121
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
122
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
123
if (ret) {
124
return ret;
125
}
126
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
127
128
int kvm_arch_get_registers(CPUState *cs)
129
{
130
- struct kvm_one_reg reg;
131
uint64_t val;
132
unsigned int el;
133
uint32_t fpr;
134
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
135
CPUARMState *env = &cpu->env;
136
137
for (i = 0; i < 31; i++) {
138
- reg.id = AARCH64_CORE_REG(regs.regs[i]);
139
- reg.addr = (uintptr_t) &env->xregs[i];
140
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
141
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
142
+ &env->xregs[i]);
143
if (ret) {
144
return ret;
145
}
67
}
146
}
68
}
147
69
148
- reg.id = AARCH64_CORE_REG(regs.sp);
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
149
- reg.addr = (uintptr_t) &env->sp_el[0];
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
150
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
151
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
73
+
152
if (ret) {
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
153
return ret;
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
154
}
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
155
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
156
- reg.id = AARCH64_CORE_REG(sp_el1);
78
+ qdev_get_gpio_in(gicdev, 22 + i));
157
- reg.addr = (uintptr_t) &env->sp_el[1];
79
+ }
158
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
80
+
159
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
160
if (ret) {
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
161
return ret;
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
162
}
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
163
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
164
- reg.id = AARCH64_CORE_REG(regs.pstate);
86
+ oscclk = qlist_new();
165
- reg.addr = (uintptr_t) &val;
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
166
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
167
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
89
+ }
168
if (ret) {
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
169
return ret;
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
170
}
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
171
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
93
+
172
*/
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
173
aarch64_restore_sp(env, 1);
95
+
174
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
175
- reg.id = AARCH64_CORE_REG(regs.pc);
97
+ TYPE_MPS2_FPGAIO);
176
- reg.addr = (uintptr_t) &env->pc;
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
177
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
178
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
179
if (ret) {
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
180
return ret;
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
181
}
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
182
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
104
+
183
aarch64_sync_64_to_32(env);
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
184
}
106
+
185
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
186
- reg.id = AARCH64_CORE_REG(elr_el1);
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
187
- reg.addr = (uintptr_t) &env->elr_el[1];
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
188
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
189
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
111
+ qdev_get_gpio_in(gicdev, 4));
190
if (ret) {
112
+
191
return ret;
113
+ /*
192
}
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
193
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
115
+ * except that it doesn't support the checksum-offload feature.
194
* KVM SPSRs 0-4 map to QEMU banks 1-5
116
+ */
195
*/
117
+ lan9118_init(0xe0300000,
196
for (i = 0; i < KVM_NR_SPSR; i++) {
118
+ qdev_get_gpio_in(gicdev, 18));
197
- reg.id = AARCH64_CORE_REG(spsr[i]);
119
+
198
- reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
199
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
200
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
122
+
201
+ &env->banked_spsr[i + 1]);
123
mms->bootinfo.ram_size = machine->ram_size;
202
if (ret) {
124
mms->bootinfo.board_id = -1;
203
return ret;
125
mms->bootinfo.loader_start = mmc->loader_start;
204
}
205
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
206
return ret;
207
}
208
209
- reg.addr = (uintptr_t)(&fpr);
210
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
211
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
212
+ ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
213
if (ret) {
214
return ret;
215
}
216
vfp_set_fpsr(env, fpr);
217
218
- reg.addr = (uintptr_t)(&fpr);
219
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
220
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
221
+ ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
222
if (ret) {
223
return ret;
224
}
225
--
126
--
226
2.34.1
127
2.34.1
227
128
228
129
diff view generated by jsdifflib
[PULL 20/24] target/arm/kvm64.c: Remove unused include
[PULL 35/35] docs: Add documentation for the mps3-an536 board
1
The include of hw/arm/virt.h in kvm64.c is unnecessary and also a
1
Add documentation for the mps3-an536 board type.
2
layering violation since the generic KVM code shouldn't need to know
3
anything about board-specifics. The include line is an accidental
4
leftover from commit 15613357ba53a4763, where we cleaned up the code
5
to not depend on virt board internals but forgot to also remove the
6
now-redundant include line.
7
2
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Gavin Shan <gshan@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20230925110429.3917202-1-peter.maydell@linaro.org
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
12
---
6
---
13
target/arm/kvm64.c | 1 -
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
14
1 file changed, 1 deletion(-)
8
1 file changed, 34 insertions(+), 3 deletions(-)
15
9
16
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm64.c
12
--- a/docs/system/arm/mps2.rst
19
+++ b/target/arm/kvm64.c
13
+++ b/docs/system/arm/mps2.rst
20
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
21
#include "internals.h"
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
22
#include "hw/acpi/acpi.h"
16
-=========================================================================================================================================================
23
#include "hw/acpi/ghes.h"
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
24
-#include "hw/arm/virt.h"
18
+=========================================================================================================================================================================
25
19
26
static bool have_guest_debug;
20
-These board models all use Arm M-profile CPUs.
27
21
+These board models use Arm M-profile or R-profile CPUs.
22
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
26
27
QEMU models the following FPGA images:
28
29
+FPGA images using M-profile CPUs:
30
+
31
``mps2-an385``
32
Cortex-M3 as documented in Arm Application Note AN385
33
``mps2-an386``
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
35
``mps3-an547``
36
Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
37
38
+FPGA images using R-profile CPUs:
39
+
40
+``mps3-an536``
41
+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
42
+
43
Differences between QEMU and real hardware:
44
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
47
flash, but only as simple ROM, so attempting to rewrite the flash
48
from the guest will fail
49
- QEMU does not model the USB controller in MPS3 boards
50
+- AN536 does not support runtime control of CPU reset and halt via
51
+ the SCC CFG_REG0 register.
52
+- AN536 does not support enabling or disabling the flash and ATCM
53
+ interfaces via the SCC CFG_REG1 register.
54
+- AN536 does not support setting of the initial vector table
55
+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
56
+ and does not provide a mechanism for specifying these values at
57
+ startup, so all guest images must be built to start from TCM
58
+ (i.e. to expect the interrupt vector base at 0 from reset).
59
+- AN536 defaults to only creating a single CPU; this is the equivalent
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
61
+ held in halt via the initial SCC CFG_REG0 register setting. You can
62
+ create the second CPU with ``-smp 2``; both CPUs will then start
63
+ execution immediately on startup.
64
+
65
+Note that for the AN536 the first UART is accessible only by
66
+CPU0, and the second UART is accessible only by CPU1. The
67
+first UART accessible shared between both CPUs is the third
68
+UART. Guest software might therefore be built to use either
69
+the first UART or the third UART; if you don't see any output
70
+from the UART you are looking at, try one of the others.
71
+(Even if the AN536 machine is started with a single CPU and so
72
+no "CPU1-only UART", the UART numbering remains the same,
73
+with the third UART being the first of the shared ones.)
74
75
Machine-specific options
76
""""""""""""""""""""""""
28
--
77
--
29
2.34.1
78
2.34.1
30
79
31
80
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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