target/riscv/cpu.c | 8 +++----- target/riscv/cpu_cfg.h | 2 +- target/riscv/csr.c | 6 +++--- target/riscv/pmp.c | 12 ++++++------ target/riscv/tcg/tcg-cpu.c | 4 ++-- 5 files changed, 15 insertions(+), 17 deletions(-)
From: Himanshu Chauhan <hchauhan@ventanamicro.com>
Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
Changes in v2:
====
- Rebase on latest riscv-to-apply.next
- Remove ePMP version comment
target/riscv/cpu.c | 8 +++-----
target/riscv/cpu_cfg.h | 2 +-
target/riscv/csr.c | 6 +++---
target/riscv/pmp.c | 12 ++++++------
target/riscv/tcg/tcg-cpu.c | 4 ++--
5 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2f98ce56e06..dad167833cc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -133,7 +133,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
- ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
+ ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
@@ -599,12 +599,11 @@ static void rv32_ibex_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
- cpu->cfg.epmp = true;
-
/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_zicsr = true;
cpu->cfg.pmp = true;
+ cpu->cfg.ext_smepmp = true;
}
static void rv32_imafcu_nommu_cpu_init(Object *obj)
@@ -1257,6 +1256,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
+ MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
@@ -1322,8 +1322,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
/* These are experimental so mark with 'x-' */
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
- /* ePMP 0.9.3 */
- MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 208cac1c7c9..e7ce977189c 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -102,6 +102,7 @@ struct RISCVCPUConfig {
bool ext_smaia;
bool ext_ssaia;
bool ext_sscofpmf;
+ bool ext_smepmp;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
@@ -134,7 +135,6 @@ struct RISCVCPUConfig {
uint16_t cboz_blocksize;
bool mmu;
bool pmp;
- bool epmp;
bool debug;
bool misa_w;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a5be1c202c3..f4e0a3962f0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -524,9 +524,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
-static RISCVException epmp(CPURISCVState *env, int csrno)
+static RISCVException smepmp(CPURISCVState *env, int csrno)
{
- if (riscv_cpu_cfg(env)->epmp) {
+ if (riscv_cpu_cfg(env)->ext_smepmp) {
return RISCV_EXCP_NONE;
}
@@ -4762,7 +4762,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
/* Physical Memory Protection */
- [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
+ [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
.min_priv_ver = PRIV_VERSION_1_11_0 },
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5e60c26031b..21d2489e27e 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -91,7 +91,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
if (pmp_index < MAX_RISCV_PMPS) {
bool locked = true;
- if (riscv_cpu_cfg(env)->epmp) {
+ if (riscv_cpu_cfg(env)->ext_smepmp) {
/* mseccfg.RLB is set */
if (MSECCFG_RLB_ISSET(env)) {
locked = false;
@@ -340,9 +340,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/*
* Convert the PMP permissions to match the truth table in the
- * ePMP spec.
+ * Smepmp spec.
*/
- const uint8_t epmp_operation =
+ const uint8_t smepmp_operation =
((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
(env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
@@ -367,7 +367,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
* If mseccfg.MML Bit set, do the enhanced pmp priv check
*/
if (mode == PRV_M) {
- switch (epmp_operation) {
+ switch (smepmp_operation) {
case 0:
case 1:
case 4:
@@ -398,7 +398,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
g_assert_not_reached();
}
} else {
- switch (epmp_operation) {
+ switch (smepmp_operation) {
case 0:
case 8:
case 9:
@@ -574,7 +574,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
}
}
- if (riscv_cpu_cfg(env)->epmp) {
+ if (riscv_cpu_cfg(env)->ext_smepmp) {
/* Sticky bits */
val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index bbce254ee13..fce58d4375a 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -591,12 +591,12 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
- if (cpu->cfg.epmp && !cpu->cfg.pmp) {
+ if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
- error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+ error_setg(errp, "Invalid configuration: Smepmp requires PMP support");
return false;
}
--
2.34.1On Thu, Oct 19, 2023 at 4:56 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> From: Himanshu Chauhan <hchauhan@ventanamicro.com>
>
> Smepmp is a ratified extension which qemu refers to as epmp.
> Rename epmp to smepmp and add it to extension list so that
> it is added to the isa string.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Changes in v2:
> ====
> - Rebase on latest riscv-to-apply.next
> - Remove ePMP version comment
>
> target/riscv/cpu.c | 8 +++-----
> target/riscv/cpu_cfg.h | 2 +-
> target/riscv/csr.c | 6 +++---
> target/riscv/pmp.c | 12 ++++++------
> target/riscv/tcg/tcg-cpu.c | 4 ++--
> 5 files changed, 15 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2f98ce56e06..dad167833cc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -133,7 +133,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> - ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
> + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
> ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
> ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
> @@ -599,12 +599,11 @@ static void rv32_ibex_cpu_init(Object *obj)
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> #endif
> - cpu->cfg.epmp = true;
> -
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> + cpu->cfg.ext_smepmp = true;
> }
>
> static void rv32_imafcu_nommu_cpu_init(Object *obj)
> @@ -1257,6 +1256,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
> MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
>
> + MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
> MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
> MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> @@ -1322,8 +1322,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
>
> /* These are experimental so mark with 'x-' */
> const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> - /* ePMP 0.9.3 */
> - MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
> MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
> MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 208cac1c7c9..e7ce977189c 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -102,6 +102,7 @@ struct RISCVCPUConfig {
> bool ext_smaia;
> bool ext_ssaia;
> bool ext_sscofpmf;
> + bool ext_smepmp;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
>
> @@ -134,7 +135,6 @@ struct RISCVCPUConfig {
> uint16_t cboz_blocksize;
> bool mmu;
> bool pmp;
> - bool epmp;
> bool debug;
> bool misa_w;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index a5be1c202c3..f4e0a3962f0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -524,9 +524,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> -static RISCVException epmp(CPURISCVState *env, int csrno)
> +static RISCVException smepmp(CPURISCVState *env, int csrno)
> {
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> return RISCV_EXCP_NONE;
> }
>
> @@ -4762,7 +4762,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
>
> /* Physical Memory Protection */
> - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
> + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
> .min_priv_ver = PRIV_VERSION_1_11_0 },
> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 5e60c26031b..21d2489e27e 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -91,7 +91,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> if (pmp_index < MAX_RISCV_PMPS) {
> bool locked = true;
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* mseccfg.RLB is set */
> if (MSECCFG_RLB_ISSET(env)) {
> locked = false;
> @@ -340,9 +340,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>
> /*
> * Convert the PMP permissions to match the truth table in the
> - * ePMP spec.
> + * Smepmp spec.
> */
> - const uint8_t epmp_operation =
> + const uint8_t smepmp_operation =
> ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
> ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
> (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
> @@ -367,7 +367,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> * If mseccfg.MML Bit set, do the enhanced pmp priv check
> */
> if (mode == PRV_M) {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 1:
> case 4:
> @@ -398,7 +398,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> g_assert_not_reached();
> }
> } else {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 8:
> case 9:
> @@ -574,7 +574,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> }
> }
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* Sticky bits */
> val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index bbce254ee13..fce58d4375a 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -591,12 +591,12 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
> return false;
> }
>
> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
> /*
> * Enhanced PMP should only be available
> * on harts with PMP support
> */
> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> + error_setg(errp, "Invalid configuration: Smepmp requires PMP support");
> return false;
> }
>
> --
> 2.34.1
>
>
On Thu, Oct 19, 2023 at 4:56 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> From: Himanshu Chauhan <hchauhan@ventanamicro.com>
>
> Smepmp is a ratified extension which qemu refers to as epmp.
> Rename epmp to smepmp and add it to extension list so that
> it is added to the isa string.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> Changes in v2:
> ====
> - Rebase on latest riscv-to-apply.next
> - Remove ePMP version comment
>
> target/riscv/cpu.c | 8 +++-----
> target/riscv/cpu_cfg.h | 2 +-
> target/riscv/csr.c | 6 +++---
> target/riscv/pmp.c | 12 ++++++------
> target/riscv/tcg/tcg-cpu.c | 4 ++--
> 5 files changed, 15 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2f98ce56e06..dad167833cc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -133,7 +133,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> - ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
> + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
> ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
> ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
> @@ -599,12 +599,11 @@ static void rv32_ibex_cpu_init(Object *obj)
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> #endif
> - cpu->cfg.epmp = true;
> -
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> + cpu->cfg.ext_smepmp = true;
> }
>
> static void rv32_imafcu_nommu_cpu_init(Object *obj)
> @@ -1257,6 +1256,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
> MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
>
> + MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
> MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
> MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> @@ -1322,8 +1322,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
>
> /* These are experimental so mark with 'x-' */
> const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> - /* ePMP 0.9.3 */
> - MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
> MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
> MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 208cac1c7c9..e7ce977189c 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -102,6 +102,7 @@ struct RISCVCPUConfig {
> bool ext_smaia;
> bool ext_ssaia;
> bool ext_sscofpmf;
> + bool ext_smepmp;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
>
> @@ -134,7 +135,6 @@ struct RISCVCPUConfig {
> uint16_t cboz_blocksize;
> bool mmu;
> bool pmp;
> - bool epmp;
> bool debug;
> bool misa_w;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index a5be1c202c3..f4e0a3962f0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -524,9 +524,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> -static RISCVException epmp(CPURISCVState *env, int csrno)
> +static RISCVException smepmp(CPURISCVState *env, int csrno)
> {
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> return RISCV_EXCP_NONE;
> }
>
> @@ -4762,7 +4762,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
>
> /* Physical Memory Protection */
> - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
> + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
> .min_priv_ver = PRIV_VERSION_1_11_0 },
> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 5e60c26031b..21d2489e27e 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -91,7 +91,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> if (pmp_index < MAX_RISCV_PMPS) {
> bool locked = true;
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* mseccfg.RLB is set */
> if (MSECCFG_RLB_ISSET(env)) {
> locked = false;
> @@ -340,9 +340,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>
> /*
> * Convert the PMP permissions to match the truth table in the
> - * ePMP spec.
> + * Smepmp spec.
> */
> - const uint8_t epmp_operation =
> + const uint8_t smepmp_operation =
> ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
> ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
> (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
> @@ -367,7 +367,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> * If mseccfg.MML Bit set, do the enhanced pmp priv check
> */
> if (mode == PRV_M) {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 1:
> case 4:
> @@ -398,7 +398,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> g_assert_not_reached();
> }
> } else {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 8:
> case 9:
> @@ -574,7 +574,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> }
> }
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* Sticky bits */
> val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index bbce254ee13..fce58d4375a 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -591,12 +591,12 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
> return false;
> }
>
> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
> /*
> * Enhanced PMP should only be available
> * on harts with PMP support
> */
> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> + error_setg(errp, "Invalid configuration: Smepmp requires PMP support");
> return false;
> }
>
> --
> 2.34.1
>
>
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