Various updates for the Cadence GEM model

[PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC

Posted by Luc Michel 1 year, 1 month ago

The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.

Signed-off-by: Luc Michel <luc.michel@amd.com>
---
 hw/net/cadence_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 21146f4242..d52530bae4 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1103,11 +1103,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 
     /* Strip of FCS field ? (usually yes) */
     if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
         rxbuf_ptr = (void *)buf;
     } else {
-        unsigned crc_val;
+        uint32_t crc_val;
 
         if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
             size = MAX_FRAME_SIZE - sizeof(crc_val);
         }
         bytes_to_copy = size;
-- 
2.39.2

RE: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC

Posted by Boddu, Sai Pavan 1 year, 1 month ago


>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for
>CRC
>
>The CRC was stored in an unsigned variable in gem_receive. Change it for a
>uint32_t to ensure we have the correct variable size here.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>

Reviewed-by: sai.pavan.boddu@amd.com


>---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>21146f4242..d52530bae4 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -1103,11 +1103,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>
>     /* Strip of FCS field ? (usually yes) */
>     if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
>         rxbuf_ptr = (void *)buf;
>     } else {
>-        unsigned crc_val;
>+        uint32_t crc_val;
>
>         if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
>             size = MAX_FRAME_SIZE - sizeof(crc_val);
>         }
>         bytes_to_copy = size;
>--
>2.39.2

Re: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC

Posted by Philippe Mathieu-Daudé 1 year, 1 month ago

On 17/10/23 21:44, Luc Michel wrote:
> The CRC was stored in an unsigned variable in gem_receive. Change it for
> a uint32_t to ensure we have the correct variable size here.
> 

Fixes: e9f186e514 ("cadence_gem: initial version of device model")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> Signed-off-by: Luc Michel <luc.michel@amd.com>
> ---
>   hw/net/cadence_gem.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)