The following changes since commit 63011373ad22c794a013da69663c03f1297a5c56:

Merge tag 'pull-riscv-to-apply-20231012-1' of https://github.com/alistair23/qemu into staging (2023-10-12 10:24:44 -0400)

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20231013

for you to fetch changes up to 1bea6930ca7b9587ea8d8fbb77069b6a13aa031a:

LoongArch: step down as general arch maintainer (2023-10-13 10:05:32 +0800)

pull-loongarch-20231013

*Fix ASXE flag conflict

*Add preldx instruction

*Add preldx instruction

*Remove unused region

*Xiao juan step down as general arch maintainer

Jiajie Chen (1):

target/loongarch: fix ASXE flag conflict

Philippe Mathieu-Daudé (2):

hw/loongarch/virt: Remove unused ISA UART

hw/loongarch/virt: Remove unused ISA Bus

Song Gao (2):

target/loongarch: Add preldx instruction

hw/loongarch/virt: Remove unused 'loongarch_virt_pm' region

Thomas Weißschuh (1):

hw/loongarch: remove global loaderparams variable

Xiaojuan Yang (1):

LoongArch: step down as general arch maintainer

MAINTAINERS | 2 -

hw/loongarch/Kconfig | 2 -

hw/loongarch/virt.c | 103 +++++++------------------

include/hw/loongarch/virt.h | 3 -

target/loongarch/cpu.h | 4 +-

target/loongarch/disas.c | 7 ++

target/loongarch/insn_trans/trans_memory.c.inc | 5 ++

target/loongarch/insns.decode | 3 +

tests/tcg/loongarch64/system/boot.S | 7 +-

9 files changed, 49 insertions(+), 87 deletions(-)

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

I haven't really been working on LoongArch for some time now,

so let's remove myself from this entry.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Acked-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20231012095135.1423071-1-yangxiaojuan@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

MAINTAINERS | 2 --

1 file changed, 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ F: disas/hppa.c

LoongArch TCG CPUs

M: Song Gao <gaosong@loongson.cn>

-M: Xiaojuan Yang <yangxiaojuan@loongson.cn>

S: Maintained

F: target/loongarch/

F: tests/tcg/loongarch64/

@@ -XXX,XX +XXX,XX @@ F: pc-bios/hppa-firmware.img

LoongArch Machines

------------------

Virt

-M: Xiaojuan Yang <yangxiaojuan@loongson.cn>

M: Song Gao <gaosong@loongson.cn>

S: Maintained

F: docs/system/loongarch/virt.rst

2.25.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The LoongArch 'virt' machine doesn't use its ISA I/O region.

If a ISA device were to be mapped there, there is no support

for ISA IRQ. Unlikely useful. Simply remove.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20231010135342.40219-3-philmd@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

---

hw/loongarch/Kconfig | 1 -

hw/loongarch/virt.c | 5 -----

include/hw/loongarch/virt.h | 3 ---

3 files changed, 9 deletions(-)

diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig

--- a/hw/loongarch/Kconfig

+++ b/hw/loongarch/Kconfig

@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT

imply VIRTIO_VGA

imply PCI_DEVICES

imply NVDIMM

- select ISA_BUS

select SERIAL

select VIRTIO_PCI

select PLATFORM_BUS

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/loongarch/virt.c

+++ b/hw/loongarch/virt.c

@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)

machine_memory_devices_init(machine, device_mem_base, device_mem_size);

2.25.1

The system test shutdown uses the 'loongarch_virt_pm' region.

We can use the write AcpiFadtData.sleep_clt register to realize the shutdown.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Message-ID: <20231012072351.1409344-1-gaosong@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

hw/loongarch/virt.c | 48 +----------------------------

tests/tcg/loongarch64/system/boot.S | 7 +++--

2 files changed, 5 insertions(+), 50 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void fdt_add_memory_node(MachineState *ms,

g_free(nodename);

}

-#define PM_BASE 0x10080000

-#define PM_SIZE 0x100

-#define PM_CTRL 0x10

-

static void virt_build_smbios(LoongArchMachineState *lams)

MachineState *ms = MACHINE(lams);

@@ -XXX,XX +XXX,XX @@ static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)

memmap_entries++;

}

-/*

- * This is a placeholder for missing ACPI,

- * and will eventually be replaced.

- */

-static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size)

-{

- return 0;

-}

-

-static void loongarch_virt_pm_write(void *opaque, hwaddr addr,

- uint64_t val, unsigned size)

-{

- if (addr != PM_CTRL) {

- return;

- }

-

- switch (val) {

- case 0x00:

- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

- return;

- case 0xff:

- qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);

- return;

- default:

- return;

- }

-}

-

-static const MemoryRegionOps loongarch_virt_pm_ops = {

- .read = loongarch_virt_pm_read,

- .write = loongarch_virt_pm_write,

- .endianness = DEVICE_NATIVE_ENDIAN,

- .valid = {

- .min_access_size = 1,

- .max_access_size = 1

- }

-};

-

static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)

return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);

@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *

SysBusDevice *d;

PCIBus *pci_bus;

MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;

- MemoryRegion *mmio_alias, *mmio_reg, *pm_mem;

+ MemoryRegion *mmio_alias, *mmio_reg;

int i;

gpex_dev = qdev_new(TYPE_GPEX_HOST);

@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *

fdt_add_rtc_node(lams);

- pm_mem = g_new(MemoryRegion, 1);

- memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,

- NULL, "loongarch_virt_pm", PM_SIZE);

- memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem);

lams->acpi_ged = create_acpi_ged(pch_pic, lams);

/* platform bus */

diff --git a/tests/tcg/loongarch64/system/boot.S b/tests/tcg/loongarch64/system/boot.S

index XXXXXXX..XXXXXXX 100644

--- a/tests/tcg/loongarch64/system/boot.S

+++ b/tests/tcg/loongarch64/system/boot.S

@@ -XXX,XX +XXX,XX @@ _start:

    .align 16

_exit:

2: /* QEMU ACPI poweroff */

-    li.w t0, 0xff

-    li.w t1, 0x10080010

-    st.w t0, t1, 0

+    li.w t0, 0x34

+    li.w t1, 0x100e001c

+    st.b t0, t1, 0

+

    idle 0

    bl 2b

2.25.1

From: Thomas Weißschuh <thomas@t-8ch.de>

Passing the struct around explicitly makes the control-flow more

obvious.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Song Gao <gaosong@loongson.cn>

Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de>

Message-Id: <20231010-loongarch-loader-params-v2-1-512cc7959683@t-8ch.de>

Signed-off-by: Song Gao <gaosong@loongson.cn>

hw/loongarch/virt.c | 50 ++++++++++++++++++++++++---------------------

1 file changed, 27 insertions(+), 23 deletions(-)

@@ -XXX,XX +XXX,XX @@

#include "qemu/error-report.h"

+struct loaderparams {

+ uint64_t ram_size;

+ const char *kernel_filename;

+ const char *kernel_cmdline;

+ const char *initrd_filename;

+};

static void virt_flash_create(LoongArchMachineState *lams)

{

DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_virt_pm_ops = {

}

};

-static struct _loaderparams {

- uint64_t ram_size;

- const char *kernel_filename;

- const char *kernel_cmdline;

- const char *initrd_filename;

-} loaderparams;

static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)

{

return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);

}

-static int64_t load_kernel_info(void)

+static int64_t load_kernel_info(const struct loaderparams *loaderparams)

{

uint64_t kernel_entry, kernel_low, kernel_high;

ssize_t kernel_size;

- kernel_size = load_elf(loaderparams.kernel_filename, NULL,

+ kernel_size = load_elf(loaderparams->kernel_filename, NULL,

cpu_loongarch_virt_to_phys, NULL,

&kernel_entry, &kernel_low,

&kernel_high, NULL, 0,

@@ -XXX,XX +XXX,XX @@ static int64_t load_kernel_info(void)

if (kernel_size < 0) {

error_report("could not load kernel '%s': %s",

- loaderparams.kernel_filename,

+ loaderparams->kernel_filename,

load_elf_strerror(kernel_size));

exit(1);

}

@@ -XXX,XX +XXX,XX @@ static void reset_load_elf(void *opaque)

2.25.1

From: Jiajie Chen <c@jia.je>

HW_FLAGS_EUEN_ASXE acccidentally conflicts with HW_FLAGS_CRMD_PG,

enabling LASX instructions even when CSR_EUEN.ASXE=0.

Closes: https://gitlab.com/qemu-project/qemu/-/issues/1907

Signed-off-by: Jiajie Chen <c@jia.je>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20230930112837.1871691-1-c@jia.je>

Signed-off-by: Song Gao <gaosong@loongson.cn>

---

target/loongarch/cpu.h | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)

* LoongArch CPUs hardware flags.

*/

#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */

-#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */

#define HW_FLAGS_EUEN_FPE 0x04

#define HW_FLAGS_EUEN_SXE 0x08

-#define HW_FLAGS_EUEN_ASXE 0x10

+#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */

#define HW_FLAGS_VA32 0x20

+#define HW_FLAGS_EUEN_ASXE 0x40

static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,

uint64_t *cs_base, uint32_t *flags)

2.25.1

Resolve the issue of starting the Loongnix 20.5[1] system failure.

Logs:

Loading Linux 4.19.0-19-loongson-3 ...

Loading initial ramdisk ...

PROGRESS CODE: V02010004 I0

PROGRESS CODE: V03101019 I0

Error: unknown opcode. 90000000003a3e6c: 0x382c6d82

[1] http://pkg.loongnix.cn/loongnix/isos/Loongnix-20.5/Loongnix-20.5.cartoon.gui.loongarch64.en.qcow2

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20230905123910.3052023-1-gaosong@loongson.cn>

---

target/loongarch/disas.c | 7 +++++++

target/loongarch/insn_trans/trans_memory.c.inc | 5 +++++

target/loongarch/insns.decode | 3 +++

3 files changed, 15 insertions(+)

diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c

--- a/target/loongarch/disas.c

+++ b/target/loongarch/disas.c

@@ -XXX,XX +XXX,XX @@ static void output_hint_r_i(DisasContext *ctx, arg_hint_r_i *a,

output(ctx, mnemonic, "%d, r%d, %d", a->hint, a->rj, a->imm);

+static void output_hint_rr(DisasContext *ctx, arg_hint_rr *a,

+ const char *mnemonic)

+ output(ctx, mnemonic, "%d, r%d, r%d", a->hint, a->rj, a->rk);

static void output_i(DisasContext *ctx, arg_i *a, const char *mnemonic)

output(ctx, mnemonic, "%d", a->imm);

@@ -XXX,XX +XXX,XX @@ INSN(ld_bu, rr_i)

INSN(ld_hu, rr_i)

INSN(ld_wu, rr_i)

INSN(preld, hint_r_i)

+INSN(preldx, hint_rr)

INSN(fld_s, fr_i)

INSN(fst_s, fr_i)

INSN(fld_d, fr_i)

diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/insn_trans/trans_memory.c.inc

+++ b/target/loongarch/insn_trans/trans_memory.c.inc

@@ -XXX,XX +XXX,XX @@ static bool trans_preld(DisasContext *ctx, arg_preld *a)

return true;

}

+static bool trans_preldx(DisasContext *ctx, arg_preldx * a)

+{

+ return true;

+}

static bool trans_dbar(DisasContext *ctx, arg_dbar * a)

{

tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);

diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/insns.decode

+++ b/target/loongarch/insns.decode

@@ -XXX,XX +XXX,XX @@

&rrr rd rj rk

&rr_i rd rj imm

&hint_r_i hint rj imm

+&hint_rr hint rj rk

&rrr_sa rd rj rk sa

&rr_ms_ls rd rj ms ls

&ff fd fj

@@ -XXX,XX +XXX,XX @@

@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i

@rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16

@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i

+@hint_rr .... ........ ..... rk:5 rj:5 hint:5 &hint_rr

@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1

@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa

@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa

@@ -XXX,XX +XXX,XX @@ ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr

ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr

ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr

preld 0010 101011 ............ ..... ..... @hint_r_i12

+preldx 0011 10000010 11000 ..... ..... ..... @hint_rr

dbar 0011 10000111 00100 ............... @i15

ibar 0011 10000111 00101 ............... @i15

ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2

2.25.1