Series comparison

-[PULL 00/54] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2:
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-  Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into staging (2023-10-11 09:43:10 -0400)
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
 are available in the Git repository at:
-  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231012-1
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to 837570cef237b634eb4c245363470deebea7089d:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  target/riscv: Fix vfwmaccbf16.vf (2023-10-12 12:50:13 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-Second RISC-V PR for 8.2
+RISC-V PR for 9.1
- * Add support for the max CPU
+* APLICs add child earlier than realize
- * Detect user choice in TCG
+* Fix exposure of Zkr
- * Clear CSR values at reset and sync MPSTATE with host
+* Raise exceptions on wrs.nto
- * Fix the typo of inverted order of pmpaddr13 and pmpaddr14
+* Implement SBI debug console (DBCN) calls for KVM
- * Split TCG/KVM accelerators from cpu.c
+* Support 64-bit addresses for initrd
- * Add extension properties for all cpus
+* Change RISCV_EXCP_SEMIHOST exception number to 63
- * Replace GDB exit calls with proper shutdown
+* Tolerate KVM disable ext errors
- * Support KVM_GET_REG_LIST
+* Set tval in breakpoints
- * Remove RVG warning
+* Add support for Zve32x extension
- * Use env_archcpu for better performance
+* Add support for Zve64x extension
- * Deprecate capital 'Z' CPU properties
+* Relax vector register check in RISCV gdbstub
- * Fix vfwmaccbf16.vf
+* Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alvin Chang (1):
+Alexei Filippov (1):
-      disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
+      target/riscv: do not set mtval2 for non guest-page faults
-Clément Chigot (5):
+Alistair Francis (2):
-      softmmu: add means to pass an exit code when requesting a shutdown
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
-      softmmu: pass the main loop status to gdb "Wxx" packet
+      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
       hw/misc/sifive_test.c: replace exit calls with proper shutdown
       hw/char: riscv_htif: replace exit calls with proper shutdown
       gdbstub: replace exit calls with proper shutdown for softmmu
-Daniel Henrique Barboza (45):
+Andrew Jones (2):
-      target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
+      target/riscv/kvm: Fix exposure of Zkr
-      target/riscv/cpu.c: skip 'bool' check when filtering KVM props
+      target/riscv: Raise exceptions on wrs.nto
       target/riscv/cpu.c: split kvm prop handling to its own helper
       target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
       target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
       target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
       target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
       target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
       target/riscv/cpu.c: limit cfg->vext_spec log message
       target/riscv: add 'max' CPU type
       avocado, risc-v: add tuxboot tests for 'max' CPU
       target/riscv: deprecate the 'any' CPU type
       target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
       target/riscv: make CPUCFG() macro public
       target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
       target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
       target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
       target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
       target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
       target/riscv/cpu.c: consider user option with RVG
       target/riscv: introduce TCG AccelCPUClass
       target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
       target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
       target/riscv: move riscv_tcg_ops to tcg-cpu.c
       target/riscv/cpu.c: add .instance_post_init()
       target/riscv: move 'host' CPU declaration to kvm.c
       target/riscv/cpu.c: mark extensions arrays as 'const'
       target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
       target/riscv: make riscv_add_satp_mode_properties() public
       target/riscv: remove kvm-stub.c
       target/riscv: introduce KVM AccelCPUClass
       target/riscv: move KVM only files to kvm subdir
       target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
       target/riscv/cpu.c: export set_misa()
       target/riscv/tcg: introduce tcg_cpu_instance_init()
       target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
       target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
       target/riscv/cpu.c: export isa_edata_arr[]
       target/riscv/cpu: move priv spec functions to tcg-cpu.c
       target/riscv: add riscv_cpu_get_name()
       target/riscv/tcg-cpu.c: add extension properties for all cpus
       target/riscv/kvm: improve 'init_multiext_cfg' error msg
       target/riscv/kvm: support KVM_GET_REG_LIST
       target/riscv/tcg: remove RVG warning
       target/riscv: deprecate capital 'Z' CPU properties
-Max Chou (1):
+Cheng Yang (1):
-      target/riscv: Fix vfwmaccbf16.vf
+      hw/riscv/boot.c: Support 64-bit address for initrd
-Richard W.M. Jones (1):
+Christoph Müllner (1):
-      target/riscv: Use env_archcpu for better performance
+      riscv: thead: Add th.sxstatus CSR emulation
-liguang.zhang (1):
+Clément Léger (1):
-      target/riscv: Clear CSR values at reset and sync MPSTATE with host
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
- docs/about/deprecated.rst             |   35 ++
+Daniel Henrique Barboza (6):
- include/gdbstub/syscalls.h            |    9 +
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
- include/sysemu/runstate.h             |    2 +
+      target/riscv/kvm: tolerate KVM disable ext errors
- include/sysemu/sysemu.h               |    2 +-
+      target/riscv/debug: set tval=pc in breakpoint exceptions
- target/riscv/cpu-qom.h                |    1 +
+      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
- target/riscv/cpu.h                    |   34 +-
+      target/riscv: prioritize pmp errors in raise_mmu_exception()
- target/riscv/{ => kvm}/kvm_riscv.h    |    2 +-
+      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
  target/riscv/tcg/tcg-cpu.h            |   27 +
  disas/riscv.c                         |    4 +-
  gdbstub/gdbstub.c                     |    5 +-
  gdbstub/system.c                      |    6 +
  gdbstub/user.c                        |    6 +
  hw/char/riscv_htif.c                  |    5 +-
  hw/intc/riscv_aplic.c                 |    2 +-
  hw/misc/sifive_test.c                 |    9 +-
  hw/riscv/virt.c                       |    2 +-
  system/main.c                         |    2 +-
  system/runstate.c                     |   16 +-
  target/riscv/cpu.c                    | 1030 +++++++--------------------------
  target/riscv/cpu_helper.c             |    3 +-
  target/riscv/csr.c                    |    1 +
  target/riscv/kvm-stub.c               |   30 -
  target/riscv/{kvm.c => kvm/kvm-cpu.c} |  272 ++++++++-
  target/riscv/tcg/tcg-cpu.c            |  949 ++++++++++++++++++++++++++++++
  target/riscv/vector_helper.c          |    2 +-
  target/riscv/kvm/meson.build          |    1 +
  target/riscv/meson.build              |    4 +-
  target/riscv/tcg/meson.build          |    2 +
  tests/avocado/tuxrun_baselines.py     |   32 +
 files changed, 1604 insertions(+), 891 deletions(-)
  rename target/riscv/{ => kvm}/kvm_riscv.h (95%)
  create mode 100644 target/riscv/tcg/tcg-cpu.h
  delete mode 100644 target/riscv/kvm-stub.c
  rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (81%)
  create mode 100644 target/riscv/tcg/tcg-cpu.c
  create mode 100644 target/riscv/kvm/meson.build
  create mode 100644 target/riscv/tcg/meson.build
+Huang Tao (2):
+      target/riscv: Fix the element agnostic function problem
+      target/riscv: Implement dynamic establishment of custom decoder
+Jason Chien (3):
+      target/riscv: Add support for Zve32x extension
+      target/riscv: Add support for Zve64x extension
+      target/riscv: Relax vector register check in RISCV gdbstub
+Max Chou (4):
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+      target/riscv: rvv: Check single width operator for vector fp widen instructions
+      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+Rob Bradford (1):
+      target/riscv: Remove experimental prefix from "B" extension
+Yangyu Chen (1):
+      target/riscv/cpu.c: fix Zvkb extension config
+Yong-Xuan Wang (1):
+      target/riscv/kvm.c: Fix the hart bit setting of AIA
+Yu-Ming Chang (1):
+      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+yang.zhang (1):
+      hw/intc/riscv_aplic: APLICs should add child earlier than realize
+ MAINTAINERS                                    |   1 +
+ target/riscv/cpu.h                             |  11 ++
+ target/riscv/cpu_bits.h                        |   2 +-
+ target/riscv/cpu_cfg.h                         |   2 +
+ target/riscv/helper.h                          |   1 +
+ target/riscv/sbi_ecall_interface.h             |  17 +++
+ target/riscv/tcg/tcg-cpu.h                     |  15 +++
+ disas/riscv.c                                  |  65 +++++++++-
+ hw/intc/riscv_aplic.c                          |   8 +-
+ hw/riscv/boot.c                                |   4 +-
+ target/riscv/cpu.c                             |  10 +-
+ target/riscv/cpu_helper.c                      |  37 +++---
+ target/riscv/csr.c                             |  71 +++++++++--
+ target/riscv/debug.c                           |   3 +
+ target/riscv/gdbstub.c                         |   8 +-
+ target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
+ target/riscv/op_helper.c                       |  17 ++-
+ target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
+ target/riscv/th_csr.c                          |  79 +++++++++++++
+ target/riscv/translate.c                       |  31 +++--
+ target/riscv/vector_internals.c                |  22 ++++
+ target/riscv/insn_trans/trans_privileged.c.inc |   2 +
+ target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
+ target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
+ target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
+ target/riscv/meson.build                       |   1 +
+files changed, 596 insertions(+), 109 deletions(-)
+ create mode 100644 target/riscv/th_csr.c

-[PULL 01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We'll add a new CPU type that will enable a considerable amount of
-extensions. To make it easier for us we'll do a few cleanups in our
-existing riscv_cpu_extensions[] array.
-Start by splitting all CPU non-boolean options from it. Create a new
-riscv_cpu_options[] array for them. Add all these properties in
-riscv_cpu_add_user_properties() as it is already being done today.
-'mmu' and 'pmp' aren't really extensions in the usual way we think about
-RISC-V extensions. These are closer to CPU features/options, so move
-both to riscv_cpu_options[] too. In the near future we'll need to match
-all extensions with all entries in isa_edata_arr[], and so it happens
-that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv
-spec version restriction). This further emphasizes the point that these
-are more a CPU option than an extension.
-No functional changes made.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-2-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
-file changed, 23 insertions(+), 10 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
- static Property riscv_cpu_extensions[] = {
-     /* Defaults for standard extensions */
--    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
-     DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
-     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
-     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
-     DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
--    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
--    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-     DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
--    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
--    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
--    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
--
-     DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
-     DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
-     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
-     DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
--    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
-     DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
--    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
-     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     DEFINE_PROP_END_OF_LIST(),
- };
-+static Property riscv_cpu_options[] = {
-+    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
-+
-+    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
-+    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-+
-+    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-+    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
-+
-+    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
-+    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-+
-+    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
-+    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
-+};
- #ifndef CONFIG_USER_ONLY
- static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
- #endif
-         qdev_property_add_static(dev, prop);
-     }
-+
-+    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
-+        /* Check if KVM created the property already */
-+        if (object_property_find(obj, riscv_cpu_options[i].name)) {
-+            continue;
-+        }
-+        qdev_property_add_static(dev, &riscv_cpu_options[i]);
-+    }
- }
- static Property riscv_cpu_properties[] = {
---
-.41.0

-[PULL 02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-After the introduction of riscv_cpu_options[] all properties in
-riscv_cpu_extensions[] are booleans. This check is now obsolete.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-3-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 14 ++++----------
-file changed, 4 insertions(+), 10 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
-              * Set the default to disabled for every extension
-              * unknown to KVM and error out if the user attempts
-              * to enable any of them.
--             *
--             * We're giving a pass for non-bool properties since they're
--             * not related to the availability of extensions and can be
--             * safely ignored as is.
-              */
--            if (prop->info == &qdev_prop_bool) {
--                object_property_add(obj, prop->name, "bool",
--                                    NULL, cpu_set_cfg_unavailable,
--                                    NULL, (void *)prop->name);
--                continue;
--            }
-+            object_property_add(obj, prop->name, "bool",
-+                                NULL, cpu_set_cfg_unavailable,
-+                                NULL, (void *)prop->name);
-+            continue;
-         }
- #endif
-         qdev_property_add_static(dev, prop);
---
-.41.0

-[PULL 34/54] target/riscv: move KVM only files to kvm subdir
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: "yang.zhang" <yang.zhang@hexintek.com>
-Move the files to a 'kvm' dir to promote more code separation between
+Since only root APLICs can have hw IRQ lines, aplic->parent should
-accelerators and making our lives easier supporting build options such
+be initialized first.
 as --disable-tcg.
-Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/{ => kvm}/kvm_riscv.h    | 0
+ hw/intc/riscv_aplic.c | 8 ++++----
- hw/intc/riscv_aplic.c                 | 2 +-
+file changed, 4 insertions(+), 4 deletions(-)
  hw/riscv/virt.c                       | 2 +-
  target/riscv/cpu.c                    | 2 +-
  target/riscv/{kvm.c => kvm/kvm-cpu.c} | 0
  target/riscv/kvm/meson.build          | 1 +
  target/riscv/meson.build              | 2 +-
 files changed, 5 insertions(+), 4 deletions(-)
  rename target/riscv/{ => kvm}/kvm_riscv.h (100%)
  rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (100%)
  create mode 100644 target/riscv/kvm/meson.build
-diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
-similarity index 100%
-rename from target/riscv/kvm_riscv.h
-rename to target/riscv/kvm/kvm_riscv.h
 diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/riscv_aplic.c
 +++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
- #include "target/riscv/cpu.h"
+     qdev_prop_set_bit(dev, "msimode", msimode);
- #include "sysemu/sysemu.h"
+     qdev_prop_set_bit(dev, "mmode", mmode);
- #include "sysemu/kvm.h"
--#include "kvm_riscv.h"
++    if (parent) {
-+#include "kvm/kvm_riscv.h"
++        riscv_aplic_add_child(parent, dev);
- #include "migration/vmstate.h"
++    }
++
- #define APLIC_MAX_IDC                  (1UL << 14)
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
+     if (!is_kvm_aia(msimode)) {
---- a/hw/riscv/virt.c
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
-+++ b/hw/riscv/virt.c
+     }
-@@ -XXX,XX +XXX,XX @@
- #include "hw/riscv/virt.h"
+-    if (parent) {
- #include "hw/riscv/boot.h"
+-        riscv_aplic_add_child(parent, dev);
- #include "hw/riscv/numa.h"
+-    }
--#include "kvm_riscv.h"
+-
-+#include "kvm/kvm_riscv.h"
+     if (!msimode) {
- #include "hw/intc/riscv_aclint.h"
+         for (i = 0; i < num_harts; i++) {
- #include "hw/intc/riscv_aplic.h"
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
  #include "hw/intc/riscv_imsic.h"
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "fpu/softfloat-helpers.h"
  #include "sysemu/kvm.h"
  #include "sysemu/tcg.h"
 -#include "kvm_riscv.h"
 +#include "kvm/kvm_riscv.h"
  #include "tcg/tcg.h"
  /* RISC-V CPU definitions */
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c
 similarity index 100%
 rename from target/riscv/kvm.c
 rename to target/riscv/kvm/kvm-cpu.c
 diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/kvm/meson.build
@@ -0,0 +1 @@
 +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
    'zce_helper.c',
    'vcrypto_helper.c'
  ))
 -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
  riscv_system_ss = ss.source_set()
  riscv_system_ss.add(files(
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
  ))
  subdir('tcg')
 +subdir('kvm')
  target_arch += {'riscv': riscv_ss}
  target_system_arch += {'riscv': riscv_system_ss}
 --
-.41.0
+.45.1

-[PULL 37/54] target/riscv/tcg: introduce tcg_cpu_instance_init()
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Andrew Jones <ajones@ventanamicro.com>
-tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
+The Zkr extension may only be exposed to KVM guests if the VMM
-accelerator. It'll be called from within riscv_cpu_post_init(), via
+implements the SEED CSR. Use the same implementation as TCG.
 accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
 preserve behavior, the implementation will be similar to what
 riscv_cpu_post_init() already does.
-In this patch we'll move riscv_cpu_add_user_properties() and
+Without this patch, running with a KVM which does not forward the
-riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
+SEED CSR access to QEMU will result in an ILL exception being
-All multi-extension properties code was moved. The 'multi_ext_user_opts'
+injected into the guest (this results in Linux guests crashing on
-hash table was also moved to tcg-cpu.c since it's a TCG only structure,
+boot). And, when running with a KVM which does forward the access,
-meaning that we won't have to worry about initializing a TCG hash table
+QEMU will crash, since QEMU doesn't know what to do with the exit.
 when running a KVM CPU anymore.
-riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
+Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
-much code it requires to be moved at the same time. We'll do that in the
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-next patch.
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20230925175709.35696-16-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |   1 -
+ target/riscv/cpu.h         |  3 +++
- target/riscv/cpu.c         | 150 -------------------------------------
+ target/riscv/csr.c         | 18 ++++++++++++++----
- target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++
+ target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
-files changed, 149 insertions(+), 151 deletions(-)
+files changed, 42 insertions(+), 4 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
- /* used by tcg/tcg-cpu.c*/
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
- void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
--bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
++target_ulong riscv_new_csr_seed(target_ulong new_value,
- bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
++                                target_ulong write_mask);
- int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
++
- void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
+ uint8_t satp_mode_max_from_map(uint32_t map);
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/target/riscv/csr.c
-+++ b/target/riscv/cpu.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
-     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+ #endif
- };
+ /* Crypto Extension */
--/* Hash that stores user set extensions */
+-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
--static GHashTable *multi_ext_user_opts;
+-                               target_ulong *ret_value,
--
+-                               target_ulong new_value,
- bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+-                               target_ulong write_mask)
 +target_ulong riscv_new_csr_seed(target_ulong new_value,
 +                                target_ulong write_mask)
  {
-     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
+     uint16_t random_v;
-@@ -XXX,XX +XXX,XX @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+     Error *random_e = NULL;
-     g_assert_not_reached();
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- }
+         rval = random_v | SEED_OPST_ES16;
+     }
--bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
--{
++    return rval;
 -    return g_hash_table_contains(multi_ext_user_opts,
 -                                 GUINT_TO_POINTER(ext_offset));
 -}
 -
  const char * const riscv_int_regnames[] = {
      "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
      "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
      "reserved"
  };
 -static void riscv_cpu_add_user_properties(Object *obj);
 -static void riscv_init_max_cpu_extensions(Object *obj);
 -
  const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
  {
      if (async) {
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
      return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
  }
 -static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
 -{
 -    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
 -}
 -
 -static bool riscv_cpu_has_user_properties(Object *cpu_obj)
 -{
 -    if (kvm_enabled() &&
 -        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
 -        return true;
 -    }
 -
 -    return riscv_cpu_is_dynamic(cpu_obj);
 -}
 -
  static void riscv_cpu_post_init(Object *obj)
  {
      accel_cpu_instance_init(CPU(obj));
 -
 -    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
 -        riscv_cpu_add_user_properties(obj);
 -    }
 -
 -    if (riscv_cpu_has_max_extensions(obj)) {
 -        riscv_init_max_cpu_extensions(obj);
 -    }
  }
  static void riscv_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
      qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
                        IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
  #endif /* CONFIG_USER_ONLY */
 -
 -    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
  }
  typedef struct RISCVCPUMisaExtConfig {
@@ -XXX,XX +XXX,XX @@ Property riscv_cpu_options[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 -static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 -                                  void *opaque, Error **errp)
 -{
 -    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 -    bool value;
 -
 -    if (!visit_type_bool(v, name, &value, errp)) {
 -        return;
 -    }
 -
 -    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
 -
 -    g_hash_table_insert(multi_ext_user_opts,
 -                        GUINT_TO_POINTER(multi_ext_cfg->offset),
 -                        (gpointer)value);
 -}
 -
 -static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 -                                  void *opaque, Error **errp)
 -{
 -    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 -    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
 -
 -    visit_type_bool(v, name, &value, errp);
 -}
 -
 -static void cpu_add_multi_ext_prop(Object *cpu_obj,
 -                                   const RISCVCPUMultiExtConfig *multi_cfg)
 -{
 -    object_property_add(cpu_obj, multi_cfg->name, "bool",
 -                        cpu_get_multi_ext_cfg,
 -                        cpu_set_multi_ext_cfg,
 -                        NULL, (void *)multi_cfg);
 -
 -    /*
 -     * Set def val directly instead of using
 -     * object_property_set_bool() to save the set()
 -     * callback hash for user inputs.
 -     */
 -    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
 -                           multi_cfg->enabled);
 -}
 -
 -static void riscv_cpu_add_multiext_prop_array(Object *obj,
 -                                        const RISCVCPUMultiExtConfig *array)
 -{
 -    const RISCVCPUMultiExtConfig *prop;
 -
 -    g_assert(array);
 -
 -    for (prop = array; prop && prop->name; prop++) {
 -        cpu_add_multi_ext_prop(obj, prop);
 -    }
 -}
 -
 -/*
 - * Add CPU properties with user-facing flags.
 - *
 - * This will overwrite existing env->misa_ext values with the
 - * defaults set via riscv_cpu_add_misa_properties().
 - */
 -static void riscv_cpu_add_user_properties(Object *obj)
 -{
 -#ifndef CONFIG_USER_ONLY
 -    riscv_add_satp_mode_properties(obj);
 -#endif
 -
 -    riscv_cpu_add_misa_properties(obj);
 -
 -    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
 -    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
 -    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
 -
 -    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
 -        qdev_property_add_static(DEVICE(obj), prop);
 -    }
 -}
 -
 -/*
 - * The 'max' type CPU will have all possible ratified
 - * non-vendor extensions enabled.
 - */
 -static void riscv_init_max_cpu_extensions(Object *obj)
 -{
 -    RISCVCPU *cpu = RISCV_CPU(obj);
 -    CPURISCVState *env = &cpu->env;
 -    const RISCVCPUMultiExtConfig *prop;
 -
 -    /* Enable RVG, RVJ and RVV that are disabled by default */
 -    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 -
 -    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
 -        isa_ext_update_enabled(cpu, prop->offset, true);
 -    }
 -
 -    /* set vector version */
 -    env->vext_ver = VEXT_VERSION_1_00_0;
 -
 -    /* Zfinx is not compatible with F. Disable it */
 -    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
 -    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
 -    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
 -    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
 -
 -    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
 -    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
 -    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
 -
 -    if (env->misa_mxl != MXL_RV32) {
 -        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
 -    }
 -}
 -
  static Property riscv_cpu_properties[] = {
      DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "pmu.h"
  #include "time_helper.h"
  #include "qapi/error.h"
 +#include "qapi/visitor.h"
  #include "qemu/accel.h"
  #include "qemu/error-report.h"
  #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
  #include "hw/core/tcg-cpu-ops.h"
  #include "tcg/tcg.h"
 +/* Hash that stores user set extensions */
 +static GHashTable *multi_ext_user_opts;
 +
 +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
 +{
 +    return g_hash_table_contains(multi_ext_user_opts,
 +                                 GUINT_TO_POINTER(ext_offset));
 +}
 +
- static void riscv_cpu_synchronize_from_tb(CPUState *cs,
++static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                                           const TranslationBlock *tb)
++                               target_ulong *ret_value,
- {
++                               target_ulong new_value,
-@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
++                               target_ulong write_mask)
-     return true;
++{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
-+static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
++static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
 +                                  void *opaque, Error **errp)
 +{
-+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
++    target_ulong csr_num = run->riscv_csr.csr_num;
-+    bool value;
++    target_ulong new_value = run->riscv_csr.new_value;
 +    target_ulong write_mask = run->riscv_csr.write_mask;
 +    int ret = 0;
 +
-+    if (!visit_type_bool(v, name, &value, errp)) {
++    switch (csr_num) {
-+        return;
++    case CSR_SEED:
 +        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled CSR EXIT for CSR %lx\n",
 +                      __func__, csr_num);
 +        ret = -1;
 +        break;
 +    }
 +
-+    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
++    return ret;
 +
 +    g_hash_table_insert(multi_ext_user_opts,
 +                        GUINT_TO_POINTER(multi_ext_cfg->offset),
 +                        (gpointer)value);
 +}
 +
-+static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 +                                  void *opaque, Error **errp)
 +{
 +    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 +    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
 +
 +    visit_type_bool(v, name, &value, errp);
 +}
 +
 +static void cpu_add_multi_ext_prop(Object *cpu_obj,
 +                                   const RISCVCPUMultiExtConfig *multi_cfg)
 +{
 +    object_property_add(cpu_obj, multi_cfg->name, "bool",
 +                        cpu_get_multi_ext_cfg,
 +                        cpu_set_multi_ext_cfg,
 +                        NULL, (void *)multi_cfg);
 +
 +    /*
 +     * Set def val directly instead of using
 +     * object_property_set_bool() to save the set()
 +     * callback hash for user inputs.
 +     */
 +    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
 +                           multi_cfg->enabled);
 +}
 +
 +static void riscv_cpu_add_multiext_prop_array(Object *obj,
 +                                        const RISCVCPUMultiExtConfig *array)
 +{
 +    const RISCVCPUMultiExtConfig *prop;
 +
 +    g_assert(array);
 +
 +    for (prop = array; prop && prop->name; prop++) {
 +        cpu_add_multi_ext_prop(obj, prop);
 +    }
 +}
 +
 +/*
 + * Add CPU properties with user-facing flags.
 + *
 + * This will overwrite existing env->misa_ext values with the
 + * defaults set via riscv_cpu_add_misa_properties().
 + */
 +static void riscv_cpu_add_user_properties(Object *obj)
 +{
 +#ifndef CONFIG_USER_ONLY
 +    riscv_add_satp_mode_properties(obj);
 +#endif
 +
 +    riscv_cpu_add_misa_properties(obj);
 +
 +    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
 +    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
 +    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
 +
 +    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
 +        qdev_property_add_static(DEVICE(obj), prop);
 +    }
 +}
 +
 +/*
 + * The 'max' type CPU will have all possible ratified
 + * non-vendor extensions enabled.
 + */
 +static void riscv_init_max_cpu_extensions(Object *obj)
 +{
 +    RISCVCPU *cpu = RISCV_CPU(obj);
 +    CPURISCVState *env = &cpu->env;
 +    const RISCVCPUMultiExtConfig *prop;
 +
 +    /* Enable RVG, RVJ and RVV that are disabled by default */
 +    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 +
 +    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
 +        isa_ext_update_enabled(cpu, prop->offset, true);
 +    }
 +
 +    /* set vector version */
 +    env->vext_ver = VEXT_VERSION_1_00_0;
 +
 +    /* Zfinx is not compatible with F. Disable it */
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
 +
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
 +
 +    if (env->misa_mxl != MXL_RV32) {
 +        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
 +    }
 +}
 +
 +static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
 +{
 +    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
 +}
 +
 +static bool riscv_cpu_has_user_properties(Object *cpu_obj)
 +{
 +    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 +}
 +
 +static void tcg_cpu_instance_init(CPUState *cs)
 +{
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    Object *obj = OBJECT(cpu);
 +
 +    if (riscv_cpu_has_user_properties(obj)) {
 +        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 +        riscv_cpu_add_user_properties(obj);
 +    }
 +
 +    if (riscv_cpu_has_max_extensions(obj)) {
 +        riscv_init_max_cpu_extensions(obj);
 +    }
 +}
 +
  static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
  {
-     /*
+     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+     case KVM_EXIT_RISCV_SBI:
+         ret = kvm_riscv_handle_sbi(cs, run);
-     acc->cpu_class_init = tcg_cpu_class_init;
+         break;
-+    acc->cpu_instance_init = tcg_cpu_instance_init;
++    case KVM_EXIT_RISCV_CSR:
-     acc->cpu_target_realize = tcg_cpu_realize;
++        ret = kvm_riscv_handle_csr(cs, run);
- }
++        break;
+     default:
          qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                        __func__, run->exit_reason);
 --
-.41.0
+.45.1

-[PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Andrew Jones <ajones@ventanamicro.com>
-riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
+Implementing wrs.nto to always just return is consistent with the
-realize() path during the common riscv_cpu_realize(), making it a good
+specification, as the instruction is permitted to terminate the
-choice to start moving TCG exclusive code to tcg-cpu.c.
+stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Rename it to tcg_cpu_realizefn() and assign it as a implementation of
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
-riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-approach with KVM in the near future.
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 riscv_cpu_validate_set_extensions() is too big and with too many
 dependencies to be moved in this same patch. We'll do that next.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20230925175709.35696-3-dbarboza@ventanamicro.com>
 [ Changes by AF:
  - Renames to fix build failures after rebase
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c         | 128 -----------------------------------
+ target/riscv/helper.h                       |  1 +
- target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
+ target/riscv/op_helper.c                    | 11 ++++++++
-files changed, 133 insertions(+), 128 deletions(-)
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 files changed, 32 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/target/riscv/helper.h
-+++ b/target/riscv/cpu.c
++++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
- #include "qemu/log.h"
+ DEF_HELPER_1(sret, tl, env)
- #include "cpu.h"
+ DEF_HELPER_1(mret, tl, env)
- #include "cpu_vendorid.h"
+ DEF_HELPER_1(wfi, void, env)
--#include "pmu.h"
++DEF_HELPER_1(wrs_nto, void, env)
- #include "internals.h"
+ DEF_HELPER_1(tlb_flush, void, env)
--#include "time_helper.h"
+ DEF_HELPER_1(tlb_flush_all, void, env)
- #include "exec/exec-all.h"
+ /* Native Debug */
- #include "qapi/error.h"
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
- #include "qapi/visitor.h"
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+--- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
      }
  }
--static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
++void helper_wrs_nto(CPURISCVState *env)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    int priv_version = -1;
 -
 -    if (cpu->cfg.priv_spec) {
 -        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
 -            priv_version = PRIV_VERSION_1_12_0;
 -        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 -            priv_version = PRIV_VERSION_1_11_0;
 -        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 -            priv_version = PRIV_VERSION_1_10_0;
 -        } else {
 -            error_setg(errp,
 -                       "Unsupported privilege spec version '%s'",
 -                       cpu->cfg.priv_spec);
 -            return;
 -        }
 -
 -        env->priv_ver = priv_version;
 -    }
 -}
 -
  static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
      }
  }
 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
 -{
 -    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 -    CPUClass *cc = CPU_CLASS(mcc);
 -    CPURISCVState *env = &cpu->env;
 -
 -    /* Validate that MISA_MXL is set properly. */
 -    switch (env->misa_mxl_max) {
 -#ifdef TARGET_RISCV64
 -    case MXL_RV64:
 -    case MXL_RV128:
 -        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 -        break;
 -#endif
 -    case MXL_RV32:
 -        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -
 -    if (env->misa_mxl_max != env->misa_mxl) {
 -        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
 -        return;
 -    }
 -}
 -
  /*
   * Check consistency between chosen extensions while setting
   * cpu->cfg accordingly.
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
  #endif
  }
 -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
 -{
 -    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
 -        error_setg(errp, "H extension requires priv spec 1.12.0");
 -        return;
 -    }
 -}
 -
 -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
 -{
 -    RISCVCPU *cpu = RISCV_CPU(dev);
 -    CPURISCVState *env = &cpu->env;
 -    Error *local_err = NULL;
 -
 -    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
 -        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
 -        return;
 -    }
 -
 -    riscv_cpu_validate_misa_mxl(cpu, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -    riscv_cpu_validate_priv_spec(cpu, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -    riscv_cpu_validate_misa_priv(env, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
 -        /*
 -         * Enhanced PMP should only be available
 -         * on harts with PMP support
 -         */
 -        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
 -        return;
 -    }
 -
 -    riscv_cpu_validate_set_extensions(cpu, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -#ifndef CONFIG_USER_ONLY
 -    CPU(dev)->tcg_cflags |= CF_PCREL;
 -
 -    if (cpu->cfg.ext_sstc) {
 -        riscv_timer_init(cpu);
 -    }
 -
 -    if (cpu->cfg.pmu_num) {
 -        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
 -            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 -                                          riscv_pmu_timer_cb, cpu);
 -        }
 -     }
 -#endif
 -}
 -
  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  {
      CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
          return;
      }
 -    if (tcg_enabled()) {
 -        riscv_cpu_realize_tcg(dev, &local_err);
 -        if (local_err != NULL) {
 -            error_propagate(errp, local_err);
 -            return;
 -        }
 -    }
 -
      riscv_cpu_finalize_features(cpu, &local_err);
      if (local_err != NULL) {
          error_propagate(errp, local_err);
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
 +#include "exec/exec-all.h"
  #include "cpu.h"
 +#include "pmu.h"
 +#include "time_helper.h"
 +#include "qapi/error.h"
  #include "qemu/accel.h"
  #include "hw/core/accel-cpu.h"
 +
 +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
 +{
-+    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
-+        error_setg(errp, "H extension requires priv spec 1.12.0");
++        get_field(env->hstatus, HSTATUS_VTW) &&
-+        return;
++        !get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +}
 +
-+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+ void helper_tlb_flush(CPURISCVState *env)
  {
      CPUState *cs = env_cpu(env);
 diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
 +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
 -#define GEN_TRANS_WRS(insn)                                     \
 -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
 -{                                                               \
 -    (void)a;                                                    \
 -    return trans_wrs(ctx);                                      \
 -}
 +static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
 +{
-+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
++    if (!ctx->cfg_ptr->ext_zawrs) {
 +    CPUClass *cc = CPU_CLASS(mcc);
 +    CPURISCVState *env = &cpu->env;
 +
 +    /* Validate that MISA_MXL is set properly. */
 +    switch (env->misa_mxl_max) {
 +#ifdef TARGET_RISCV64
 +    case MXL_RV64:
 +    case MXL_RV128:
 +        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 +        break;
 +#endif
 +    case MXL_RV32:
 +        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    if (env->misa_mxl_max != env->misa_mxl) {
 +        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
 +        return;
 +    }
 +}
 +
 +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
 +{
 +    CPURISCVState *env = &cpu->env;
 +    int priv_version = -1;
 +
 +    if (cpu->cfg.priv_spec) {
 +        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
 +            priv_version = PRIV_VERSION_1_12_0;
 +        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 +            priv_version = PRIV_VERSION_1_11_0;
 +        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 +            priv_version = PRIV_VERSION_1_10_0;
 +        } else {
 +            error_setg(errp,
 +                       "Unsupported privilege spec version '%s'",
 +                       cpu->cfg.priv_spec);
 +            return;
 +        }
 +
 +        env->priv_ver = priv_version;
 +    }
 +}
 +
 +/*
 + * We'll get here via the following path:
 + *
 + * riscv_cpu_realize()
 + *   -> cpu_exec_realizefn()
 + *      -> tcg_cpu_realize() (via accel_cpu_common_realize())
 + */
 +static bool tcg_cpu_realize(CPUState *cs, Error **errp)
 +{
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    CPURISCVState *env = &cpu->env;
 +    Error *local_err = NULL;
 +
 +    if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
 +        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
 +        return false;
 +    }
-+
-+    riscv_cpu_validate_misa_mxl(cpu, &local_err);
+-GEN_TRANS_WRS(wrs_nto)
-+    if (local_err != NULL) {
+-GEN_TRANS_WRS(wrs_sto)
-+        error_propagate(errp, local_err);
++    /*
-+        return false;
++     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
-+    }
++     * should raise an exception when the implementation-specific bounded time
-+
++     * limit has expired. Our time limit is zero, so we either return
-+    riscv_cpu_validate_priv_spec(cpu, &local_err);
++     * immediately, as does our implementation of wrs.sto, or raise an
-+    if (local_err != NULL) {
++     * exception, as handled by the wrs.nto helper.
-+        error_propagate(errp, local_err);
++     */
 +        return false;
 +    }
 +
 +    riscv_cpu_validate_misa_priv(env, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return false;
 +    }
 +
 +    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
 +        /*
 +         * Enhanced PMP should only be available
 +         * on harts with PMP support
 +         */
 +        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
 +        return false;
 +    }
 +
 +    riscv_cpu_validate_set_extensions(cpu, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return false;
 +    }
 +
 +#ifndef CONFIG_USER_ONLY
-+    CPU(cs)->tcg_cflags |= CF_PCREL;
++    gen_helper_wrs_nto(tcg_env);
 +
 +    if (cpu->cfg.ext_sstc) {
 +        riscv_timer_init(cpu);
 +    }
 +
 +    if (cpu->cfg.pmu_num) {
 +        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
 +            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 +                                          riscv_pmu_timer_cb, cpu);
 +        }
 +     }
 +#endif
 +
-+    return true;
++    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
 +    return trans_wrs_sto(ctx, NULL);
 +}
-+
- static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
- {
-     /*
-@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
-     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
-     acc->cpu_class_init = tcg_cpu_class_init;
-+    acc->cpu_target_realize = tcg_cpu_realize;
- }
- static const TypeInfo tcg_cpu_accel_type_info = {
 --
-.41.0
+.45.1

-[PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We'll introduce the KVM accelerator class with a 'cpu_instance_init'
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
-implementation that is going to be invoked during the common
+the legacy console putchar and getchar SBI extensions.
-riscv_cpu_post_init() (via accel_cpu_instance_init()). This
-instance_init will execute KVM exclusive code that TCG doesn't care
+The appeal of the DBCN extension is that it allows multiple bytes to be
-about, such as adding KVM specific properties, initing registers using a
+read/written in the SBI console in a single SBI call.
-KVM scratch CPU and so on.
+As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
-The core of the forementioned cpu_instance_init impl is the current
+module to userspace. But this will only happens if the KVM module
-riscv_cpu_add_kvm_properties() that is being used by the common code via
+actually supports this SBI extension and we activate it.
-riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
-will all the relevant artifacts, exporting and renaming it to
+We'll check for DBCN support during init time, checking if get-reg-list
-kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.
+is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
+kvm_set_one_reg() during kvm_arch_init_vcpu().
-To make this work we'll need to export riscv_cpu_extensions,
-riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
+Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
-well. The TCG accelerator will also need to access those in the near
+SBI_EXT_DBCN, reading and writing as required.
-future so this export will benefit us in the long run.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20230925175709.35696-9-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h       | 14 +++++++
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- target/riscv/kvm_riscv.h |  3 --
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
- target/riscv/cpu.c       | 85 +++-------------------------------------
+files changed, 128 insertions(+)
- target/riscv/kvm.c       | 68 +++++++++++++++++++++++++++++++-
-files changed, 86 insertions(+), 84 deletions(-)
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/sbi_ecall_interface.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/sbi_ecall_interface.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/core/cpu.h"
+ /* clang-format off */
- #include "hw/registerfields.h"
-+#include "hw/qdev-properties.h"
++#define SBI_SUCCESS                      0
- #include "exec/cpu-defs.h"
++#define SBI_ERR_FAILED                  -1
- #include "qemu/cpu-float.h"
++#define SBI_ERR_NOT_SUPPORTED           -2
- #include "qom/object.h"
++#define SBI_ERR_INVALID_PARAM           -3
-@@ -XXX,XX +XXX,XX @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
++#define SBI_ERR_DENIED                  -4
- int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
++#define SBI_ERR_INVALID_ADDRESS         -5
- void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
++#define SBI_ERR_ALREADY_AVAILABLE       -6
++#define SBI_ERR_ALREADY_STARTED         -7
-+typedef struct RISCVCPUMultiExtConfig {
++#define SBI_ERR_ALREADY_STOPPED         -8
-+    const char *name;
++#define SBI_ERR_NO_SHMEM                -9
-+    uint32_t offset;
++
-+    bool enabled;
+ /* SBI Extension IDs */
-+} RISCVCPUMultiExtConfig;
+ #define SBI_EXT_0_1_SET_TIMER           0x0
-+
+ #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
-+extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
+@@ -XXX,XX +XXX,XX @@
-+extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
+ #define SBI_EXT_IPI                     0x735049
-+extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+ #define SBI_EXT_RFENCE                  0x52464E43
-+extern Property riscv_cpu_options[];
+ #define SBI_EXT_HSM                     0x48534D
-+
++#define SBI_EXT_DBCN                    0x4442434E
-+void riscv_cpu_add_misa_properties(Object *cpu_obj);
-+
+ /* SBI function IDs for BASE extension */
- /* CSR function table */
+ #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
- extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
+@@ -XXX,XX +XXX,XX @@
+ #define SBI_EXT_HSM_HART_STOP           0x1
-diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
+ #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm_riscv.h
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/kvm_riscv.h
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
- #ifndef QEMU_KVM_RISCV_H
+                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  #define QEMU_KVM_RISCV_H
 -/* Temporarily implemented in cpu.c */
  void kvm_riscv_cpu_add_kvm_properties(Object *obj);
 -
 -void kvm_riscv_init_user_properties(Object *cpu_obj);
  void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
  void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
  void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
   * change MISA bits during realize() (RVG enables MISA
   * bits but the user is warned about it).
   */
 -static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 +void riscv_cpu_add_misa_properties(Object *cpu_obj)
  {
      int i;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
      }
  }
 -typedef struct RISCVCPUMultiExtConfig {
 -    const char *name;
 -    uint32_t offset;
 -    bool enabled;
 -} RISCVCPUMultiExtConfig;
 -
  #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
      {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
       .enabled = _defval}
 -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
 +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      /* Defaults for standard extensions */
      MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
      MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
--static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
++static KVMCPUConfig kvm_sbi_dbcn = {
-+const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
++    .name = "sbi_dbcn",
-     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
++    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
-     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
++                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
-     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
++};
-@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
++
- };
+ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
+ {
- /* These are experimental so mark with 'x-' */
+     CPURISCVState *env = &cpu->env;
--static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
-+const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+     return 0;
-     /* ePMP 0.9.3 */
+ }
-     MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
-     MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
++static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
-@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
++                                             KVMScratchCPU *kvmcpu,
-     DEFINE_PROP_END_OF_LIST(),
++                                             struct kvm_reg_list *reglist)
  };
 -static Property riscv_cpu_options[] = {
 +Property riscv_cpu_options[] = {
      DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
      }
  }
 -#ifdef CONFIG_KVM
 -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
 -                                    const char *name,
 -                                    void *opaque, Error **errp)
 -{
 -    const char *propname = opaque;
 -    bool value;
 -
 -    if (!visit_type_bool(v, name, &value, errp)) {
 -        return;
 -    }
 -
 -    if (value) {
 -        error_setg(errp, "extension %s is not available with KVM",
 -                   propname);
 -    }
 -}
 -
 -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 -{
 -    /* Check if KVM created the property already */
 -    if (object_property_find(obj, prop_name)) {
 -        return;
 -    }
 -
 -    /*
 -     * Set the default to disabled for every extension
 -     * unknown to KVM and error out if the user attempts
 -     * to enable any of them.
 -     */
 -    object_property_add(obj, prop_name, "bool",
 -                        NULL, cpu_set_cfg_unavailable,
 -                        NULL, (void *)prop_name);
 -}
 -
 -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
 -                                        const RISCVCPUMultiExtConfig *array)
 -{
 -    const RISCVCPUMultiExtConfig *prop;
 -
 -    g_assert(array);
 -
 -    for (prop = array; prop && prop->name; prop++) {
 -        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
 -    }
 -}
 -
 -void kvm_riscv_cpu_add_kvm_properties(Object *obj)
 -{
 -    Property *prop;
 -    DeviceState *dev = DEVICE(obj);
 -
 -    kvm_riscv_init_user_properties(obj);
 -    riscv_cpu_add_misa_properties(obj);
 -
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 -
 -    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
 -        /* Check if KVM created the property already */
 -        if (object_property_find(obj, prop->name)) {
 -            continue;
 -        }
 -        qdev_property_add_static(dev, prop);
 -    }
 -}
 -#endif
 -
  /*
   * Add CPU properties with user-facing flags.
   *
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
      }
  }
 +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
 +                                    const char *name,
 +                                    void *opaque, Error **errp)
 +{
-+    const char *propname = opaque;
++    struct kvm_reg_list *reg_search;
-+    bool value;
++
-+
++    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
-+    if (!visit_type_bool(v, name, &value, errp)) {
++                         sizeof(uint64_t), uint64_cmp);
-+        return;
++
-+    }
++    if (reg_search) {
-+
++        kvm_sbi_dbcn.supported = true;
 +    if (value) {
 +        error_setg(errp, "extension %s is not available with KVM",
 +                   propname);
 +    }
 +}
 +
-+static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                   struct kvm_reg_list *reglist)
  {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
-+    /* Check if KVM created the property already */
++    target_ulong reg = 1;
-+    if (object_property_find(obj, prop_name)) {
++
-+        return;
++    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
-+    /*
++    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +     * Set the default to disabled for every extension
 +     * unknown to KVM and error out if the user attempts
 +     * to enable any of them.
 +     */
 +    object_property_add(obj, prop_name, "bool",
 +                        NULL, cpu_set_cfg_unavailable,
 +                        NULL, (void *)prop_name);
 +}
 +
-+static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
+ int kvm_arch_init_vcpu(CPUState *cs)
-+                                        const RISCVCPUMultiExtConfig *array)
+ {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
-+    const RISCVCPUMultiExtConfig *prop;
++    g_autofree uint8_t *buf = NULL;
-+
++    RISCVCPU *cpu = RISCV_CPU(cs);
-+    g_assert(array);
++    target_ulong num_bytes;
-+
++    uint64_t addr;
-+    for (prop = array; prop && prop->name; prop++) {
++    unsigned char ch;
-+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
++    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
 +}
 +
- static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
+ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
-     int i;
+     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
-     }
+         }
- }
+         ret = 0;
+         break;
--void kvm_riscv_init_user_properties(Object *cpu_obj)
++    case SBI_EXT_DBCN:
-+static void riscv_init_user_properties(Object *cpu_obj)
++        kvm_riscv_handle_sbi_dbcn(cs, run);
- {
++        break;
-     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
+     default:
-     KVMScratchCPU kvmcpu;
+         qemu_log_mask(LOG_UNIMP,
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
      kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
  }
 +void kvm_riscv_cpu_add_kvm_properties(Object *obj)
 +{
 +    DeviceState *dev = DEVICE(obj);
 +
 +    riscv_init_user_properties(obj);
 +    riscv_cpu_add_misa_properties(obj);
 +
 +    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
 +    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
 +    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 +
 +    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
 +        /* Check if KVM created the property already */
 +        if (object_property_find(obj, prop->name)) {
 +            continue;
 +        }
 +        qdev_property_add_static(dev, prop);
 +    }
 +}
 +
  static void riscv_host_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 --
-.41.0
+.45.1

-[PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Cheng Yang <yangcheng.work@foxmail.com>
-The array isn't marked as 'const' because we're initializing their
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
-elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
+to set the address of initrd in FDT to support 64-bit address.
 fields.
-In a closer look we can see that we're not using these 2 fields after
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
 creating the MISA properties. And we can create the properties by using
 riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
 directly.
 Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
 and make misa_ext_cfgs[] a const array.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com>
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 21 ++++++++-------------
+ hw/riscv/boot.c | 4 ++--
-file changed, 8 insertions(+), 13 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/hw/riscv/boot.c
-+++ b/target/riscv/cpu.c
++++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
- }
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+     if (fdt) {
- typedef struct RISCVCPUMisaExtConfig {
+         end = start + size;
--    const char *name;
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
--    const char *description;
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
-     target_ulong misa_bit;
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
-     bool enabled;
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
  } RISCVCPUMisaExtConfig;
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
  #define MISA_CFG(_bit, _enabled) \
      {.misa_bit = _bit, .enabled = _enabled}
 -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
 +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
      MISA_CFG(RVA, true),
      MISA_CFG(RVC, true),
      MISA_CFG(RVD, true),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_add_misa_properties(Object *cpu_obj)
      int i;
      for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
 -        RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 +        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
          int bit = misa_cfg->misa_bit;
 -
 -        misa_cfg->name = riscv_get_misa_ext_name(bit);
 -        misa_cfg->description = riscv_get_misa_ext_description(bit);
 +        const char *name = riscv_get_misa_ext_name(bit);
 +        const char *desc = riscv_get_misa_ext_description(bit);
          /* Check if KVM already created the property */
 -        if (object_property_find(cpu_obj, misa_cfg->name)) {
 +        if (object_property_find(cpu_obj, name)) {
              continue;
          }
 -        object_property_add(cpu_obj, misa_cfg->name, "bool",
 +        object_property_add(cpu_obj, name, "bool",
                              cpu_get_misa_ext_cfg,
                              cpu_set_misa_ext_cfg,
                              NULL, (void *)misa_cfg);
 -        object_property_set_description(cpu_obj, misa_cfg->name,
 -                                        misa_cfg->description);
 -        object_property_set_bool(cpu_obj, misa_cfg->name,
 -                                 misa_cfg->enabled, NULL);
 +        object_property_set_description(cpu_obj, name, desc);
 +        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
      }
  }
 --
-.41.0
+.45.1

-[PULL 49/54] target/riscv/kvm: improve 'init_multiext_cfg' error msg
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Clément Léger <cleger@rivosinc.com>
-Our error message is returning the value of 'ret', which will be always
+The current semihost exception number (16) is a reserved number (range
--1 in case of error, and will not be that useful:
+[16-17]). The upcoming double trap specification uses that number for
 the double trap exception. Since the privileged spec (Table 22) defines
 ranges for custom uses change the semihosting exception number to 63
 which belongs to the range [48-63] in order to avoid any future
 collisions with reserved exception.
-qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error -1
+Signed-off-by: Clément Léger <cleger@rivosinc.com>
-Improve the error message by outputting 'errno' instead of 'ret'. Use
-strerrorname_np() to output the error name instead of the error code.
-This will give us what we need to know right away:
-qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error code: ENOENT
-Given that we're going to exit(1) in this condition instead of
-attempting to recover, remove the 'kvm_riscv_destroy_scratch_vcpu()'
-call.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-ID: <20231003132148.797921-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm/kvm-cpu.c | 4 ++--
+ target/riscv/cpu_bits.h | 2 +-
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm/kvm-cpu.c
+--- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
-                 val = false;
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
-             } else {
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
-                 error_report("Unable to read ISA_EXT KVM register %s, "
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
--                             "error %d", multi_ext_cfg->name, ret);
+-    RISCV_EXCP_SEMIHOST = 0x10,
--                kvm_riscv_destroy_scratch_vcpu(kvmcpu);
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
-+                             "error code: %s", multi_ext_cfg->name,
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
-+                             strerrorname_np(errno));
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
-                 exit(EXIT_FAILURE);
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
-             }
++    RISCV_EXCP_SEMIHOST = 0x3f,
-         } else {
+ } RISCVException;
  #define RISCV_EXCP_INT_FLAG                0x80000000
 --
-.41.0
+.45.1

-[PULL 35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-riscv_cpu_add_misa_properties() is being used to fill the missing KVM
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
-MISA properties but it is a TCG helper that was adapted to do so. We'll
+enabled, will fail with a kernel oops SIGILL right at the start. The
-move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
+reason is that we can't expose zkr without implementing the SEED CSR.
-the remaining MISA properties on its own.
+Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
-Do not use riscv_cpu_add_misa_properties(). Let's create a new array
+In hindsight this is too strict. If we keep proceeding, despite not
-with all available MISA bits we support that can be read by KVM. The
+disabling the extension in the KVM vcpu, we'll not add the extension in
-array is zero terminate to allow us to iterate through it without
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
-knowing its size.
+it doesn't matter if the KVM vcpu has it enabled underneath or not. So
 it's ok to keep booting in this case.
-Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
+Change our current logic to not error out if we fail to disable an
-MISA properties as usual and then use this array to add any missing MISA
+extension in kvm_set_one_reg(), but show a warning and keep booting. It
-properties with the riscv_cpu_add_kvm_unavail_prop() helper.
+is important to throw a warning because we must make the user aware that
 the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
-Note that we're creating misa_bits[], and not using the existing
+The case we're handling happens with an EINVAL error code. If we fail to
-'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
+disable the extension in KVM for any other reason, error out.
 related functions and it doesn't have all MISA bits we support. Commit
 e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
 full context.
-While we're at it, move both satp and the multi-letter extension
+We'll also keep erroring out when we fail to enable an extension in KVM,
-properties to kvm_riscv_add_cpu_user_properties() as well.
+since adding the extension in riscv,isa at this point will cause a guest
 malfunction because the extension isn't enabled in the vcpu.
+Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-ID: <20230925175709.35696-14-dbarboza@ventanamicro.com>
+Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  3 ++-
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
- target/riscv/cpu.c         |  2 ++
+file changed, 8 insertions(+), 4 deletions(-)
  target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++--------
 files changed, 18 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
- #define RV(x) ((target_ulong)1 << (x - 'A'))
- /*
-- * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[]
-+ * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
-  * when adding new MISA bits here.
-  */
- #define RVI RV('I')
-@@ -XXX,XX +XXX,XX @@
- #define RVJ RV('J')
- #define RVG RV('G')
-+extern const uint32_t misa_bits[];
- const char *riscv_get_misa_ext_name(uint32_t bit);
- const char *riscv_get_misa_ext_description(uint32_t bit);
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
- /* RISC-V CPU definitions */
- static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
-+const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
-+                              RVC, RVS, RVU, RVH, RVJ, RVG, 0};
- struct isa_ext_data {
-     const char *name;
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
- {
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
-     int i;
+         ret = kvm_set_one_reg(cs, id, &reg);
+         if (ret != 0) {
-+    riscv_add_satp_mode_properties(cpu_obj);
+-            error_report("Unable to %s extension %s in KVM, error %d",
-+
+-                         reg ? "enable" : "disable",
-     for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) {
+-                         multi_ext_cfg->name, ret);
-         KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i];
+-            exit(EXIT_FAILURE);
-         int bit = misa_cfg->offset;
++            if (!reg && ret == -EINVAL) {
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
++                warn_report("KVM cannot disable extension %s",
-                                         misa_cfg->description);
++                            multi_ext_cfg->name);
-     }
++            } else {
++                error_report("Unable to enable extension %s in KVM, error %d",
-+    for (i = 0; misa_bits[i] != 0; i++) {
++                             multi_ext_cfg->name, ret);
-+        const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]);
++                exit(EXIT_FAILURE);
-+        riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name);
++            }
-+    }
+         }
 +
      for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
          KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i];
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
      object_property_add(cpu_obj, "cboz_blocksize", "uint16",
                          NULL, kvm_cpu_set_cbomz_blksize,
                          NULL, &kvm_cboz_blocksize);
 +
 +    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions);
 +    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts);
 +    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts);
  }
  static int kvm_riscv_get_regs_core(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      }
  }
--static void riscv_init_user_properties(Object *cpu_obj)
-+static void riscv_init_kvm_registers(Object *cpu_obj)
- {
-     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
-     KVMScratchCPU kvmcpu;
-@@ -XXX,XX +XXX,XX @@ static void riscv_init_user_properties(Object *cpu_obj)
-         return;
-     }
--    kvm_riscv_add_cpu_user_properties(cpu_obj);
-     kvm_riscv_init_machine_ids(cpu, &kvmcpu);
-     kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
-     kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
-@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_instance_init(CPUState *cs)
-     Object *obj = OBJECT(RISCV_CPU(cs));
-     DeviceState *dev = DEVICE(obj);
--    riscv_init_user_properties(obj);
--    riscv_add_satp_mode_properties(obj);
--    riscv_cpu_add_misa_properties(obj);
-+    riscv_init_kvm_registers(obj);
--    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
--    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
--    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
-+    kvm_riscv_add_cpu_user_properties(obj);
-     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
-         /* Check if we have a specific KVM handler for the option */
 --
-.41.0
+.45.1

-[PULL 43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-At this moment we do not expose extension properties for vendor CPUs
+We're not setting (s/m)tval when triggering breakpoints of type 2
-because that would allow users to change them via command line. The
+(mcontrol) and 6 (mcontrol6). According to the debug spec section
-drawback is that if we were to add an API that shows all CPU properties,
+.7.12, "Match Control Type 6":
 e.g. qmp-query-cpu-model-expansion, we won't be able to show extensions
 state of vendor CPUs.
-We have the required machinery to create extension properties for vendor
+"The Privileged Spec says that breakpoint exceptions that occur on
-CPUs while not allowing users to enable extensions. Disabling existing
+instruction fetches, loads, or stores update the tval CSR with either
-extensions is allowed since it can be useful for debugging.
+zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
-Change the set() callback cpu_set_multi_ext_cfg() to allow enabling
+A similar text is also found in the Debug spec section 5.7.11 w.r.t.
-extensions only for generic CPUs. In cpu_add_multi_ext_prop() let's not
+mcontrol.
 set the default values for the properties if we're not dealing with
 generic CPUs, otherwise the values set in cpu_init() of vendor CPUs will
 be overwritten. And finally, in tcg_cpu_instance_init(), add cpu user
 properties for all CPUs.
-For the veyron-v1 CPU, we're now able to disable existing extensions
+Note that what we're doing ATM is not violating the spec, but it's
-like smstateen:
+simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
-$ ./build/qemu-system-riscv64 --nographic -M virt \
+Given that we always use action = 0, save the faulting address for the
-    -cpu veyron-v1,smstateen=false
+mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
+used as as scratch area for traps with address information. 'tval' is
-But setting extensions that the CPU didn't set during cpu_init(), like
+then set during riscv_cpu_do_interrupt().
 V, is not allowed:
 $ ./build/qemu-system-riscv64 --nographic -M virt \
     -cpu veyron-v1,v=true
 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.v=true:
   'veyron-v1' CPU does not allow enabling extensions
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230926183109.165878-3-dbarboza@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/tcg/tcg-cpu.c | 64 +++++++++++++++++++++++++++++---------
+ target/riscv/cpu_helper.c | 1 +
-file changed, 50 insertions(+), 14 deletions(-)
+ target/riscv/debug.c      | 3 +++
 files changed, 4 insertions(+)
-diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/tcg/tcg-cpu.c
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-     riscv_cpu_disable_priv_spec_isa_exts(cpu);
+             tval = env->bins;
- }
+             break;
+         case RISCV_EXCP_BREAKPOINT:
-+static bool riscv_cpu_is_generic(Object *cpu_obj)
++            tval = env->badaddr;
-+{
+             if (cs->watchpoint_hit) {
-+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+                 tval = cs->watchpoint_hit->hitaddr;
-+}
+                 cs->watchpoint_hit = NULL;
-+
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
- /*
+index XXXXXXX..XXXXXXX 100644
-  * We'll get here via the following path:
+--- a/target/riscv/debug.c
-  *
++++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
-     target_ulong misa_bit = misa_ext_cfg->misa_bit;
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-     RISCVCPU *cpu = RISCV_CPU(obj);
+                     /* check U/S/M bit against current privilege level */
-     CPURISCVState *env = &cpu->env;
+                     if ((ctrl >> 3) & BIT(env->priv)) {
--    bool value;
++                        env->badaddr = pc;
-+    bool generic_cpu = riscv_cpu_is_generic(obj);
+                         return true;
-+    bool prev_val, value;
+                     }
+                 }
-     if (!visit_type_bool(v, name, &value, errp)) {
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
-         return;
+                     if (env->virt_enabled) {
-     }
+                         /* check VU/VS bit against current privilege level */
+                         if ((ctrl >> 23) & BIT(env->priv)) {
-+    prev_val = env->misa_ext & misa_bit;
++                            env->badaddr = pc;
-+
+                             return true;
-+    if (value == prev_val) {
+                         }
-+        return;
+                     } else {
-+    }
+                         /* check U/S/M bit against current privilege level */
-+
+                         if ((ctrl >> 3) & BIT(env->priv)) {
-     if (value) {
++                            env->badaddr = pc;
-+        if (!generic_cpu) {
+                             return true;
-+            g_autofree char *cpuname = riscv_cpu_get_name(cpu);
+                         }
-+            error_setg(errp, "'%s' CPU does not allow enabling extensions",
+                     }
 +                       cpuname);
 +            return;
 +        }
 +
          env->misa_ext |= misa_bit;
          env->misa_ext_mask |= misa_bit;
      } else {
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
   */
  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
  {
 +    bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
      int i;
      for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
                              cpu_set_misa_ext_cfg,
                              NULL, (void *)misa_cfg);
          object_property_set_description(cpu_obj, name, desc);
 -        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
 +        if (use_def_vals) {
 +            object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
 +        }
      }
  }
@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                    void *opaque, Error **errp)
  {
      const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 -    bool value;
 +    RISCVCPU *cpu = RISCV_CPU(obj);
 +    bool generic_cpu = riscv_cpu_is_generic(obj);
 +    bool prev_val, value;
      if (!visit_type_bool(v, name, &value, errp)) {
          return;
      }
 -    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
 -
      g_hash_table_insert(multi_ext_user_opts,
                          GUINT_TO_POINTER(multi_ext_cfg->offset),
                          (gpointer)value);
 +
 +    prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
 +
 +    if (value == prev_val) {
 +        return;
 +    }
 +
 +    if (value && !generic_cpu) {
 +        g_autofree char *cpuname = riscv_cpu_get_name(cpu);
 +        error_setg(errp, "'%s' CPU does not allow enabling extensions",
 +                   cpuname);
 +        return;
 +    }
 +
 +    isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value);
  }
  static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
  static void cpu_add_multi_ext_prop(Object *cpu_obj,
                                     const RISCVCPUMultiExtConfig *multi_cfg)
  {
 +    bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
 +
      object_property_add(cpu_obj, multi_cfg->name, "bool",
                          cpu_get_multi_ext_cfg,
                          cpu_set_multi_ext_cfg,
                          NULL, (void *)multi_cfg);
 +    if (!generic_cpu) {
 +        return;
 +    }
 +
      /*
       * Set def val directly instead of using
       * object_property_set_bool() to save the set()
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
      return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
  }
 -static bool riscv_cpu_has_user_properties(Object *cpu_obj)
 -{
 -    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 -}
 -
  static void tcg_cpu_instance_init(CPUState *cs)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
      Object *obj = OBJECT(cpu);
 -    if (riscv_cpu_has_user_properties(obj)) {
 -        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 -        riscv_cpu_add_user_properties(obj);
 -    }
 +    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 +    riscv_cpu_add_user_properties(obj);
      if (riscv_cpu_has_max_extensions(obj)) {
          riscv_init_max_cpu_extensions(obj);
 --
-.41.0
+.45.1

-[PULL 42/54] target/riscv: add riscv_cpu_get_name()
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We'll introduce generic errors that will output a CPU type name via its
+Privileged spec section 4.1.9 mentions:
 RISCVCPU pointer. Create a helper for that.
-Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host'
+"When a trap is taken into S-mode, stval is written with
-CPU name.
+exception-specific information to assist software in handling the trap.
 (...)
 If stval is written with a nonzero value when a breakpoint,
 address-misaligned, access-fault, or page-fault exception occurs on an
 instruction fetch, load, or store, then stval will contain the faulting
 virtual address."
 A similar text is found for mtval in section 3.1.16.
 Setting mtval/stval in this scenario is optional, but some softwares read
 these regs when handling ebreaks.
 Write 'badaddr' in all ebreak breakpoints to write the appropriate
 'tval' during riscv_do_cpu_interrrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230926183109.165878-2-dbarboza@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  1 +
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
- target/riscv/cpu.c         | 11 +++++++++++
+file changed, 2 insertions(+)
  target/riscv/tcg/tcg-cpu.c |  4 +++-
 files changed, 15 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ typedef struct isa_ext_data {
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
-     int ext_enable_offset;
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
- } RISCVIsaExtData;
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
- extern const RISCVIsaExtData isa_edata_arr[];
+     } else {
-+char *riscv_cpu_get_name(RISCVCPU *cpu);
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
++                      offsetof(CPURISCVState, badaddr));
- void riscv_add_satp_mode_properties(Object *obj);
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
      return oc;
  }
 +char *riscv_cpu_get_name(RISCVCPU *cpu)
 +{
 +    RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
 +    const char *typename = object_class_get_name(OBJECT_CLASS(rcc));
 +
 +    g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX));
 +
 +    return g_strndup(typename,
 +                     strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX));
 +}
 +
  static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
      Error *local_err = NULL;
      if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
 -        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
 +        g_autofree char *name = riscv_cpu_get_name(cpu);
 +        error_setg(errp, "'%s' CPU is not compatible with TCG acceleration",
 +                   name);
          return false;
      }
+     return true;
 --
-.41.0
+.45.1

-[PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Jason Chien <jason.chien@sifive.com>
-Let's change the other instances in realize() where we're enabling an
+Add support for Zve32x extension and replace some checks for Zve32f with
-extension based on a certain criteria (e.g. it's a dependency of another
+Zve32x, since Zve32f depends on Zve32x.
 extension).
-We're leaving icsr and ifencei being enabled during RVG for later -
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-we'll want to error out in that case. Every other extension enablement
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-during realize is now done via cpu_cfg_ext_auto_update().
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The end goal is that only cpu init() functions will handle extension
+Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 flags directly via "cpu->cfg.ext_N = true|false".
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230912132423.268494-17-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 50 +++++++++++++++++++++++-----------------------
+ target/riscv/cpu_cfg.h                  |  1 +
-file changed, 25 insertions(+), 25 deletions(-)
+ target/riscv/cpu.c                      |  2 ++
  target/riscv/cpu_helper.c               |  2 +-
  target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu_cfg.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zhinx;
+     bool ext_zhinxmin;
+     bool ext_zve32f;
++    bool ext_zve32x;
+     bool ext_zve64f;
+     bool ext_zve64d;
+     bool ext_zvbb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
++    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
+     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
+     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
++    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
+     *cs_base = 0;
+-    if (cpu->cfg.ext_zve32f) {
++    if (cpu->cfg.ext_zve32x) {
+         /*
+          * If env->vl equals to VLMAX, we can use generic vector operation
+          * expanders (GVEC) to accerlate the vector operations.
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
+ static RISCVException vs(CPURISCVState *env, int csrno)
+ {
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
+ #if !defined(CONFIG_USER_ONLY)
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+             return RISCV_EXCP_ILLEGAL_INST;
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
 @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+         return;
      }
-     if (cpu->cfg.ext_zfh) {
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
--        cpu->cfg.ext_zfhmin = true;
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
+-        return;
 +    /* The Zve32f extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve32f) {
 +        if (!riscv_has_ext(env, RVF)) {
 +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +            return;
 +        }
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
-     if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
+     if (cpu->cfg.ext_zvfh) {
 @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-         }
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
          /* The V vector extension depends on the Zve64d extension */
 -        cpu->cfg.ext_zve64d = true;
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
      }
-     /* The Zve64d extension depends on the Zve64f extension */
+-    /*
-     if (cpu->cfg.ext_zve64d) {
+-     * In principle Zve*x would also suffice here, were they supported
--        cpu->cfg.ext_zve64f = true;
+-     * in qemu
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
+-     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
      TCGv s1, dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
-     /* The Zve64f extension depends on the Zve32f extension */
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
-     if (cpu->cfg.ext_zve64f) {
+ {
--        cpu->cfg.ext_zve32f = true;
+     TCGv dst;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
-     if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     }
-     if (cpu->cfg.ext_zvfh) {
--        cpu->cfg.ext_zvfhmin = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
-     }
-     if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     /* Set the ISA extensions, checks should have happened above */
-     if (cpu->cfg.ext_zhinx) {
--        cpu->cfg.ext_zhinxmin = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-     }
-     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     }
-     if (cpu->cfg.ext_zce) {
--        cpu->cfg.ext_zca = true;
--        cpu->cfg.ext_zcb = true;
--        cpu->cfg.ext_zcmp = true;
--        cpu->cfg.ext_zcmt = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
-         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
--            cpu->cfg.ext_zcf = true;
-+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     }
-     if (cpu->cfg.ext_zk) {
--        cpu->cfg.ext_zkn = true;
--        cpu->cfg.ext_zkr = true;
--        cpu->cfg.ext_zkt = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
-     }
-     if (cpu->cfg.ext_zkn) {
--        cpu->cfg.ext_zbkb = true;
--        cpu->cfg.ext_zbkc = true;
--        cpu->cfg.ext_zbkx = true;
--        cpu->cfg.ext_zkne = true;
--        cpu->cfg.ext_zknd = true;
--        cpu->cfg.ext_zknh = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
-     }
-     if (cpu->cfg.ext_zks) {
--        cpu->cfg.ext_zbkb = true;
--        cpu->cfg.ext_zbkc = true;
--        cpu->cfg.ext_zbkx = true;
--        cpu->cfg.ext_zksed = true;
--        cpu->cfg.ext_zksh = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
-     }
-     /*
 --
-.41.0
+.45.1

-[PULL 53/54] target/riscv: deprecate capital 'Z' CPU properties
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Jason Chien <jason.chien@sifive.com>
-At this moment there are eleven CPU extension properties that starts
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
-with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa,
+enabling Zve64x enables Zve32x according to their dependency.
 Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named
 with lower-case letters.
-We want all properties to be named with lower-case letters since it's
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
-consistent with the riscv-isa string that we create in the FDT. Having
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-these 11 properties to be exceptions can be confusing.
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Deprecate all of them. Create their lower-case counterpart to be used as
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-maintained CPU properties. When trying to use any deprecated property a
+Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 warning message will be displayed, recommending users to switch to the
 lower-case variant:
 ./build/qemu-system-riscv64 -M virt -cpu rv64,Zifencei=true --nographic
 qemu-system-riscv64: warning: CPU property 'Zifencei' is deprecated. Please use 'zifencei' instead
 This will give users some time to change their scripts before we remove
 the capital 'Z' properties entirely.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20231009112817.8896-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/about/deprecated.rst  | 23 ++++++++++++++++++++++
+ target/riscv/cpu_cfg.h     |  1 +
- target/riscv/cpu.h         |  1 +
+ target/riscv/cpu.c         |  2 ++
- target/riscv/cpu.c         | 39 +++++++++++++++++++++++++++-----------
+ target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
- target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++-
+files changed, 14 insertions(+), 6 deletions(-)
 files changed, 82 insertions(+), 12 deletions(-)
-diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/about/deprecated.rst
+--- a/target/riscv/cpu_cfg.h
-+++ b/docs/about/deprecated.rst
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
+     bool ext_zve32x;
- CPU type starting in 8.2.
+     bool ext_zve64f;
+     bool ext_zve64d;
-+RISC-V CPU properties which start with capital 'Z' (since 8.2)
++    bool ext_zve64x;
-+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+     bool ext_zvbb;
-+
+     bool ext_zvbc;
-+All RISC-V CPU properties which start with capital 'Z' are being deprecated
+     bool ext_zvkb;
 +starting in 8.2. The reason is that they were wrongly added with capital 'Z'
 +in the past. CPU properties were later added with lower-case names, which
 +is the format we want to use from now on.
 +
 +Users which try to use these deprecated properties will receive a warning
 +recommending to switch to their stable counterparts:
 +
 +- "Zifencei" should be replaced with "zifencei"
 +- "Zicsr" should be replaced with "zicsr"
 +- "Zihintntl" should be replaced with "zihintntl"
 +- "Zihintpause" should be replaced with "zihintpause"
 +- "Zawrs" should be replaced with "zawrs"
 +- "Zfa" should be replaced with "zfa"
 +- "Zfh" should be replaced with "zfh"
 +- "Zfhmin" should be replaced with "zfhmin"
 +- "Zve32f" should be replaced with "zve32f"
 +- "Zve64f" should be replaced with "zve64f"
 +- "Zve64d" should be replaced with "zve64d"
 +
  Block device options
  ''''''''''''''''''''
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
  extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
  extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
  extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 +extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
  extern Property riscv_cpu_options[];
  typedef struct isa_ext_data {
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
- const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
-     /* Defaults for standard extensions */
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
-     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
--    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
--    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
--    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
--    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
--    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
--    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
+     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
--    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
--    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
--    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
++    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
--    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
--    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
+     MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
-+    MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true),
+     MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 +    MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
 +    MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
 +    MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
 +    MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
 +    MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
 +    MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
 +    MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
 +    MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
 +    MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
      MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
      MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 +/* Deprecated entries marked for future removal */
 +const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
 +    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
 +    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
 +    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
 +    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
 +    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
 +    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
 +    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
 +    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
 +    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
 +    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
 +
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
  Property riscv_cpu_options[] = {
      DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
- }
+-    /* The Zve64f extension depends on the Zve32f extension */
-+static bool cpu_ext_is_deprecated(const char *ext_name)
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
-+{
+     if (cpu->cfg.ext_zve64f) {
-+    return isupper(ext_name[0]);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
-+}
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
-+
+     }
-+/*
-+ * String will be allocated in the heap. Caller is responsible
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-+ * for freeing it.
+-        error_setg(errp, "Zve64d/V extensions require D extension");
-+ */
+-        return;
-+static char *cpu_ext_to_lower(const char *ext_name)
++    /* The Zve64x extension depends on the Zve32x extension */
-+{
++    if (cpu->cfg.ext_zve64x) {
-+    char *ret = g_malloc0(strlen(ext_name) + 1);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
-+
+     }
-+    strcpy(ret, ext_name);
-+    ret[0] = tolower(ret[0]);
+     /* The Zve32f extension depends on the Zve32x extension */
-+
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 +    return ret;
 +}
 +
  static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                    void *opaque, Error **errp)
  {
@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
          return;
      }
-+    if (cpu_ext_is_deprecated(multi_ext_cfg->name)) {
+-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
-+        g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name);
++    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
-+
+         error_setg(
-+        warn_report("CPU property '%s' is deprecated. Please use '%s' instead",
+             errp,
-+                    multi_ext_cfg->name, lower);
+-            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
-+    }
++            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
 +
      g_hash_table_insert(multi_ext_user_opts,
                          GUINT_TO_POINTER(multi_ext_cfg->offset),
                          (gpointer)value);
@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
                                     const RISCVCPUMultiExtConfig *multi_cfg)
  {
      bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
 +    bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name);
      object_property_add(cpu_obj, multi_cfg->name, "bool",
                          cpu_get_multi_ext_cfg,
                          cpu_set_multi_ext_cfg,
                          NULL, (void *)multi_cfg);
 -    if (!generic_cpu) {
 +    if (!generic_cpu || deprecated_ext) {
          return;
      }
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
-     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
-     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
-+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
-+
-     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
-         qdev_property_add_static(DEVICE(obj), prop);
-     }
 --
-.41.0
+.45.1

-[PULL 51/54] target/riscv/tcg: remove RVG warning
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Jason Chien <jason.chien@sifive.com>
-Vendor CPUs that set RVG are displaying user warnings about other
+In current implementation, the gdbstub allows reading vector registers
-extensions that RVG must enable, one warning per CPU. E.g.:
+only if V extension is supported. However, all vector extensions and
 vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+Reviewed-by: Max Chou <max.chou@sifive.com>
-qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
 qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
 qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
 qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
 qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
 qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
 This happens because we decided a while ago that, for simplicity, vendor
 CPUs could set RVG instead of setting each G extension individually in
 their cpu_init(). Our warning isn't taking that into account, and we're
 bugging users with a warning that we're causing ourselves.
 In a closer look we conclude that this warning is not warranted in any
 other circumstance since we're just following the ISA [1], which states
 in chapter 24:
 "One goal of the RISC-V project is that it be used as a stable software
 development target. For this purpose, we define a combination of a base
 ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
 Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for
 the IMAFDZicsr Zifencei combination of instruction-set extensions."
 With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly
 enables 'G' is an expected behavior and the warning is unneeded. Any
 user caught by surprise should refer to the ISA.
 Remove the warning when handling RVG.
 [1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
 Reported-by: Paul A. Clarke <pclarke@ventanamicro.com>
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/tcg/tcg-cpu.c | 1 -
+ target/riscv/gdbstub.c | 2 +-
-file changed, 1 deletion(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/tcg/tcg-cpu.c
+--- a/target/riscv/gdbstub.c
-+++ b/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
-             return;
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
-         }
+);
+     }
--        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+-    if (env->misa_ext & RVV) {
-         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
++    if (cpu->cfg.ext_zve32x) {
-         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+                                  riscv_gdb_set_vector,
                                   ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
 --
-.41.0
+.45.1

-[PULL 48/54] gdbstub: replace exit calls with proper shutdown for softmmu
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
-From: Clément Chigot <chigot@adacore.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-This replaces the exit calls by shutdown requests, ensuring a proper
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
-cleanup of Qemu. Features like net/vhost-vdpa.c are expecting
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
-qemu_cleanup to be called to remove their last residuals.
+agnostic policy.
-Signed-off-by: Clément Chigot <chigot@adacore.com>
+However, this function can't deal the big endian situation. This patch fixes
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+the problem by adding handling of such case.
-Message-ID: <20231003071427.188697-6-chigot@adacore.com>
 Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/gdbstub/syscalls.h | 9 +++++++++
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
- gdbstub/gdbstub.c          | 5 +++--
+file changed, 22 insertions(+)
  gdbstub/system.c           | 6 ++++++
  gdbstub/user.c             | 6 ++++++
 files changed, 24 insertions(+), 2 deletions(-)
-diff --git a/include/gdbstub/syscalls.h b/include/gdbstub/syscalls.h
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/gdbstub/syscalls.h
+--- a/target/riscv/vector_internals.c
-+++ b/include/gdbstub/syscalls.h
++++ b/target/riscv/vector_internals.c
-@@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void);
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
-  */
+     if (tot - cnt == 0) {
- void gdb_exit(int code);
+         return ;
 +/**
 + * gdb_qemu_exit: ask qemu to exit
 + * @code: exit code reported
 + *
 + * This requests qemu to exit. This function is allowed to return as
 + * the exit request might be processed asynchronously by qemu backend.
 + */
 +void gdb_qemu_exit(int code);
 +
  #endif /* _SYSCALLS_H_ */
 diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/gdbstub/gdbstub.c
 +++ b/gdbstub/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void handle_v_kill(GArray *params, void *user_ctx)
      gdb_put_packet("OK");
      error_report("QEMU: Terminated via GDBstub");
      gdb_exit(0);
 -    exit(0);
 +    gdb_qemu_exit(0);
  }
  static const GdbCmdParseEntry gdb_v_commands_table[] = {
@@ -XXX,XX +XXX,XX @@ static int gdb_handle_packet(const char *line_buf)
          /* Kill the target */
          error_report("QEMU: Terminated via GDBstub");
          gdb_exit(0);
 -        exit(0);
 +        gdb_qemu_exit(0);
 +        break;
      case 'D':
          {
              static const GdbCmdParseEntry detach_cmd_desc = {
 diff --git a/gdbstub/system.c b/gdbstub/system.c
 index XXXXXXX..XXXXXXX 100644
 --- a/gdbstub/system.c
 +++ b/gdbstub/system.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
      qemu_chr_fe_deinit(&gdbserver_system_state.chr, true);
  }
 +void gdb_qemu_exit(int code)
 +{
 +    qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN,
 +                                           code);
 +}
 +
  /*
   * Memory access
   */
 diff --git a/gdbstub/user.c b/gdbstub/user.c
 index XXXXXXX..XXXXXXX 100644
 --- a/gdbstub/user.c
 +++ b/gdbstub/user.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
          gdb_put_packet(buf);
          gdbserver_state.allow_stop_reply = false;
      }
 +
-+}
++    if (HOST_BIG_ENDIAN) {
-+
++        /*
-+void gdb_qemu_exit(int code)
++         * Deal the situation when the elements are insdie
-+{
++         * only one uint64 block including setting the
-+    exit(code);
++         * masked-off element.
 +         */
 +        if (((tot - 1) ^ cnt) < 8) {
 +            memset(base + H1(tot - 1), -1, tot - cnt);
 +            return;
 +        }
 +        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
      memset(base + cnt, -1, tot - cnt);
  }
- int gdb_handlesig(CPUState *cpu, int sig)
 --
-.41.0
+.45.1

-[PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Yangyu Chen <cyy@cyyself.name>
-This CPU only exists if we're compiling with KVM so move it to the kvm
+This code has a typo that writes zvkb to zvkg, causing users can't
-specific file.
+enable zvkb through the config. This patch gets this fixed.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-7-dbarboza@ventanamicro.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 15 ---------------
+ target/riscv/cpu.c | 2 +-
- target/riscv/kvm.c | 21 +++++++++++++++++++++
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 21 insertions(+), 15 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
- }
+     /* Vector cryptography extensions */
- #endif
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
--#if defined(CONFIG_KVM)
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
--static void riscv_host_cpu_init(Object *obj)
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
--{
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
--    CPURISCVState *env = &RISCV_CPU(obj)->env;
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
--#if defined(TARGET_RISCV32)
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
 -    set_misa(env, MXL_RV32, 0);
 -#elif defined(TARGET_RISCV64)
 -    set_misa(env, MXL_RV64, 0);
 -#endif
 -}
 -#endif /* CONFIG_KVM */
 -
  static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
  {
      ObjectClass *oc;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
      },
      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
 -#if defined(CONFIG_KVM)
 -    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
 -#endif
  #if defined(TARGET_RISCV32)
      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,   rv32_base_cpu_init),
      DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
      kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
  }
 +
 +static void riscv_host_cpu_init(Object *obj)
 +{
 +    CPURISCVState *env = &RISCV_CPU(obj)->env;
 +
 +#if defined(TARGET_RISCV32)
 +    env->misa_mxl_max = env->misa_mxl = MXL_RV32;
 +#elif defined(TARGET_RISCV64)
 +    env->misa_mxl_max = env->misa_mxl = MXL_RV64;
 +#endif
 +}
 +
 +static const TypeInfo riscv_kvm_cpu_type_infos[] = {
 +    {
 +        .name = TYPE_RISCV_CPU_HOST,
 +        .parent = TYPE_RISCV_CPU,
 +        .instance_init = riscv_host_cpu_init,
 +    }
 +};
 +
 +DEFINE_TYPES(riscv_kvm_cpu_type_infos)
 --
-.41.0
+.45.1

-[PULL 39/54] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-All code related to MISA TCG properties is also moved.
+In this patch, we modify the decoder to be a freely composable data
 structure instead of a hardcoded one. It can be dynamically builded up
 according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
-properties handling is done in kvm-cpu.c.
+Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
+Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-18-dbarboza@ventanamicro.com>
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  1 -
+ target/riscv/cpu.h         |  1 +
- target/riscv/cpu.c         | 90 --------------------------------------
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
- target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
+ target/riscv/cpu.c         |  1 +
-files changed, 90 insertions(+), 91 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
  target/riscv/translate.c   | 31 +++++++++++++++----------------
 files changed, 47 insertions(+), 16 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+     uint32_t pmu_avail_ctrs;
- extern Property riscv_cpu_options[];
+     /* Mapping of events to counters */
+     GHashTable *pmu_event_ctr_map;
--void riscv_cpu_add_misa_properties(Object *cpu_obj);
++    const GPtrArray *decoders;
- void riscv_add_satp_mode_properties(Object *obj);
+ };
- /* CSR function table */
+ /**
 diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.h
 +++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
  void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
  bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 +struct DisasContext;
 +struct RISCVCPUConfig;
 +typedef struct RISCVDecoder {
 +    bool (*guard_func)(const struct RISCVCPUConfig *);
 +    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +} RISCVDecoder;
 +
 +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +
 +extern const size_t decoder_table_size;
 +
 +extern const RISCVDecoder decoder_table[];
 +
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
 +
  #endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
- #endif /* CONFIG_USER_ONLY */
+             error_propagate(errp, local_err);
- }
+             return;
+         }
--typedef struct RISCVCPUMisaExtConfig {
++        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
--    target_ulong misa_bit;
+     } else if (kvm_enabled()) {
--    bool enabled;
+         riscv_kvm_cpu_finalize_features(cpu, &local_err);
--} RISCVCPUMisaExtConfig;
+         if (local_err != NULL) {
 -
 -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 -                                 void *opaque, Error **errp)
 -{
 -    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
 -    target_ulong misa_bit = misa_ext_cfg->misa_bit;
 -    RISCVCPU *cpu = RISCV_CPU(obj);
 -    CPURISCVState *env = &cpu->env;
 -    bool value;
 -
 -    if (!visit_type_bool(v, name, &value, errp)) {
 -        return;
 -    }
 -
 -    if (value) {
 -        env->misa_ext |= misa_bit;
 -        env->misa_ext_mask |= misa_bit;
 -    } else {
 -        env->misa_ext &= ~misa_bit;
 -        env->misa_ext_mask &= ~misa_bit;
 -    }
 -}
 -
 -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 -                                 void *opaque, Error **errp)
 -{
 -    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
 -    target_ulong misa_bit = misa_ext_cfg->misa_bit;
 -    RISCVCPU *cpu = RISCV_CPU(obj);
 -    CPURISCVState *env = &cpu->env;
 -    bool value;
 -
 -    value = env->misa_ext & misa_bit;
 -
 -    visit_type_bool(v, name, &value, errp);
 -}
 -
  typedef struct misa_ext_info {
      const char *name;
      const char *description;
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
      return val;
  }
 -#define MISA_CFG(_bit, _enabled) \
 -    {.misa_bit = _bit, .enabled = _enabled}
 -
 -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
 -    MISA_CFG(RVA, true),
 -    MISA_CFG(RVC, true),
 -    MISA_CFG(RVD, true),
 -    MISA_CFG(RVF, true),
 -    MISA_CFG(RVI, true),
 -    MISA_CFG(RVE, false),
 -    MISA_CFG(RVM, true),
 -    MISA_CFG(RVS, true),
 -    MISA_CFG(RVU, true),
 -    MISA_CFG(RVH, true),
 -    MISA_CFG(RVJ, false),
 -    MISA_CFG(RVV, false),
 -    MISA_CFG(RVG, false),
 -};
 -
 -/*
 - * We do not support user choice tracking for MISA
 - * extensions yet because, so far, we do not silently
 - * change MISA bits during realize() (RVG enables MISA
 - * bits but the user is warned about it).
 - */
 -void riscv_cpu_add_misa_properties(Object *cpu_obj)
 -{
 -    int i;
 -
 -    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
 -        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 -        int bit = misa_cfg->misa_bit;
 -        const char *name = riscv_get_misa_ext_name(bit);
 -        const char *desc = riscv_get_misa_ext_description(bit);
 -
 -        /* Check if KVM already created the property */
 -        if (object_property_find(cpu_obj, name)) {
 -            continue;
 -        }
 -
 -        object_property_add(cpu_obj, name, "bool",
 -                            cpu_get_misa_ext_cfg,
 -                            cpu_set_misa_ext_cfg,
 -                            NULL, (void *)misa_cfg);
 -        object_property_set_description(cpu_obj, name, desc);
 -        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
 -    }
 -}
 -
  #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
      {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
       .enabled = _defval}
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
+@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
-     return true;
+     }
  }
-+typedef struct RISCVCPUMisaExtConfig {
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
 +    target_ulong misa_bit;
 +    bool enabled;
 +} RISCVCPUMisaExtConfig;
 +
 +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 +                                 void *opaque, Error **errp)
 +{
-+    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
++    GPtrArray *dynamic_decoders;
-+    target_ulong misa_bit = misa_ext_cfg->misa_bit;
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
-+    RISCVCPU *cpu = RISCV_CPU(obj);
++    for (size_t i = 0; i < decoder_table_size; ++i) {
-+    CPURISCVState *env = &cpu->env;
++        if (decoder_table[i].guard_func &&
-+    bool value;
++            decoder_table[i].guard_func(&cpu->cfg)) {
-+
++            g_ptr_array_add(dynamic_decoders,
-+    if (!visit_type_bool(v, name, &value, errp)) {
++                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
-+        return;
++        }
 +    }
 +
-+    if (value) {
++    cpu->decoders = dynamic_decoders;
 +        env->misa_ext |= misa_bit;
 +        env->misa_ext_mask |= misa_bit;
 +    } else {
 +        env->misa_ext &= ~misa_bit;
 +        env->misa_ext_mask &= ~misa_bit;
 +    }
 +}
 +
-+static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
-+                                 void *opaque, Error **errp)
+ {
-+{
+     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
-+    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-+    target_ulong misa_bit = misa_ext_cfg->misa_bit;
+index XXXXXXX..XXXXXXX 100644
-+    RISCVCPU *cpu = RISCV_CPU(obj);
+--- a/target/riscv/translate.c
-+    CPURISCVState *env = &cpu->env;
++++ b/target/riscv/translate.c
-+    bool value;
+@@ -XXX,XX +XXX,XX @@
  #include "exec/helper-info.c.inc"
  #undef  HELPER_H
 +#include "tcg/tcg-cpu.h"
 +
-+    value = env->misa_ext & misa_bit;
+ /* global register indices */
-+
+ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
-+    visit_type_bool(v, name, &value, errp);
+ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
-+}
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-+
+     /* FRM is known to contain a valid value. */
-+#define MISA_CFG(_bit, _enabled) \
+     bool frm_valid;
-+    {.misa_bit = _bit, .enabled = _enabled}
+     bool insn_start_updated;
-+
++    const GPtrArray *decoders;
-+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+ } DisasContext;
-+    MISA_CFG(RVA, true),
-+    MISA_CFG(RVC, true),
+ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
-+    MISA_CFG(RVD, true),
+@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
-+    MISA_CFG(RVF, true),
+     return (first_word & 3) == 3 ? 4 : 2;
-+    MISA_CFG(RVI, true),
+ }
-+    MISA_CFG(RVE, false),
-+    MISA_CFG(RVM, true),
++const RISCVDecoder decoder_table[] = {
-+    MISA_CFG(RVS, true),
++    { always_true_p, decode_insn32 },
-+    MISA_CFG(RVU, true),
++    { has_xthead_p, decode_xthead},
-+    MISA_CFG(RVH, true),
++    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
 +    MISA_CFG(RVJ, false),
 +    MISA_CFG(RVV, false),
 +    MISA_CFG(RVG, false),
 +};
 +
-+/*
++const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
 + * We do not support user choice tracking for MISA
 + * extensions yet because, so far, we do not silently
 + * change MISA bits during realize() (RVG enables MISA
 + * bits but the user is warned about it).
 + */
 +static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 +{
 +    int i;
 +
-+    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 +        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 +        int bit = misa_cfg->misa_bit;
 +        const char *name = riscv_get_misa_ext_name(bit);
 +        const char *desc = riscv_get_misa_ext_description(bit);
 +
 +        /* Check if KVM already created the property */
 +        if (object_property_find(cpu_obj, name)) {
 +            continue;
 +        }
 +
 +        object_property_add(cpu_obj, name, "bool",
 +                            cpu_get_misa_ext_cfg,
 +                            cpu_set_misa_ext_cfg,
 +                            NULL, (void *)misa_cfg);
 +        object_property_set_description(cpu_obj, name, desc);
 +        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
 +    }
 +}
 +
  static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                    void *opaque, Error **errp)
  {
+-    /*
+-     * A table with predicate (i.e., guard) functions and decoder functions
+-     * that are tested in-order until a decoder matches onto the opcode.
+-     */
+-    static const struct {
+-        bool (*guard_func)(const RISCVCPUConfig *);
+-        bool (*decode_func)(DisasContext *, uint32_t);
+-    } decoders[] = {
+-        { always_true_p,  decode_insn32 },
+-        { has_xthead_p, decode_xthead },
+-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
+-    };
+-
+     ctx->virt_inst_excp = false;
+     ctx->cur_insn_len = insn_len(opcode);
+     /* Check for compressed insn */
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+                                              ctx->base.pc_next + 2));
+         ctx->opcode = opcode32;
+-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
+-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
+-                decoders[i].decode_func(ctx, opcode32)) {
++        for (guint i = 0; i < ctx->decoders->len; ++i) {
++            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
++            if (func(ctx, opcode32)) {
+                 return;
+             }
+         }
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
+     ctx->zero = tcg_constant_tl(0);
+     ctx->virt_inst_excp = false;
++    ctx->decoders = cpu->decoders;
+ }
+ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 --
-.41.0
+.45.1

-[PULL 23/54] target/riscv: introduce TCG AccelCPUClass
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Christoph Müllner <christoph.muellner@vrull.eu>
-target/riscv/cpu.c needs to handle all possible accelerators (TCG and
+The th.sxstatus CSR can be used to identify available custom extension
-KVM at this moment) during both init() and realize() time. This forces
+on T-Head CPUs. The CSR is documented here:
-us to resort to a lot of "if tcg" and "if kvm" throughout the code,
+  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
 which isn't wrong, but can get cluttered over time. Splitting
 acceleration specific code from cpu.c to its own file will help to
 declutter the existing code and it will also make it easier to support
 KVM/TCG only builds in the future.
-We'll start by adding a new subdir called 'tcg' and a new file called
+An important property of this patch is, that the th.sxstatus MAEE field
-'tcg-cpu.c'. This file will be used to introduce a new accelerator class
+is not set (indicating that XTheadMae is not available).
-for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
+XTheadMae is a memory attribute extension (similar to Svpbmt) which is
-code in its file instead of using 'cpu.c' for everything. This design is
+implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
-inpired by the work Claudio Fontana did in x86 a few years ago in commit
+in PTEs that are marked as reserved. QEMU maintainers prefer to not
-f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
+implement XTheadMae, so we need give kernels a mechanism to identify
-AccelCPUClass").
+if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
-To avoid moving too much code at once we'll start by adding the new file
+Further context can be found on the list:
-and TCG AccelCPUClass declaration. The 'class_init' from the accel class
+https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
 will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
 doing it.
-'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
+Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 to deal with moving code and files around right now. We'll focus on
 decoupling the realize() logic first.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com>
+Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
 Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h           |  4 +++
+ MAINTAINERS              |  1 +
- target/riscv/cpu.c           |  5 +---
+ target/riscv/cpu.h       |  3 ++
- target/riscv/tcg/tcg-cpu.c   | 58 ++++++++++++++++++++++++++++++++++++
+ target/riscv/cpu.c       |  1 +
- target/riscv/meson.build     |  2 ++
+ target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
- target/riscv/tcg/meson.build |  2 ++
+ target/riscv/meson.build |  1 +
-files changed, 67 insertions(+), 4 deletions(-)
+files changed, 85 insertions(+)
- create mode 100644 target/riscv/tcg/tcg-cpu.c
+ create mode 100644 target/riscv/th_csr.c
  create mode 100644 target/riscv/tcg/meson.build
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/insn_trans/trans_xthead.c.inc
+ F: target/riscv/xthead*.decode
++F: target/riscv/th_*
+ F: disas/riscv-xthead*
+ RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
-     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
+ uint8_t satp_mode_max_from_map(uint32_t map);
- };
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-+/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
++/* Implemented in th_csr.c */
-+#include "hw/core/tcg-cpu-ops.h"
++void th_register_custom_csrs(RISCVCPU *cpu);
 +extern const struct TCGCPUOps riscv_tcg_ops;
 +
- /* CSR function table */
+ #endif /* RISCV_CPU_H */
  extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
+@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
- };
+     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_SV39);
 +    th_register_custom_csrs(cpu);
  #endif
--#include "hw/core/tcg-cpu-ops.h"
+     /* inherited from parent obj via riscv_cpu_init() */
--
+diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
 -static const struct TCGCPUOps riscv_tcg_ops = {
 +const struct TCGCPUOps riscv_tcg_ops = {
      .initialize = riscv_translate_init,
      .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
      .restore_state_to_opc = riscv_restore_state_to_opc,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
  #endif
      cc->gdb_arch_name = riscv_gdb_arch_name;
      cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
 -    cc->tcg_ops = &riscv_tcg_ops;
      object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
                                cpu_set_mvendorid, NULL, NULL);
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/th_csr.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * riscv TCG cpu class initialization
++ * T-Head-specific CSRs.
 + *
-+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
++ * Copyright (c) 2024 VRULL GmbH
 + * Copyright (c) 2017-2018 SiFive, Inc.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "cpu.h"
-+#include "qemu/accel.h"
++#include "cpu_vendorid.h"
 +#include "hw/core/accel-cpu.h"
 +
-+static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
++#define CSR_TH_SXSTATUS 0x5c0
 +
 +/* TH_SXSTATUS bits */
 +#define TH_SXSTATUS_UCME        BIT(16)
 +#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
 +typedef struct {
 +    int csrno;
 +    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
 +static RISCVException smode(CPURISCVState *env, int csrno)
 +{
-+    /*
++    if (riscv_has_ext(env, RVS)) {
-+     * All cpus use the same set of operations.
++        return RISCV_EXCP_NONE;
-+     * riscv_tcg_ops is being imported from cpu.c for now.
++    }
-+     */
++
-+    cc->tcg_ops = &riscv_tcg_ops;
++    return RISCV_EXCP_ILLEGAL_INST;
 +}
 +
-+static void tcg_cpu_class_init(CPUClass *cc)
++static int test_thead_mvendorid(RISCVCPU *cpu)
 +{
-+    cc->init_accel_cpu = tcg_cpu_init_ops;
++    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
 +        return -1;
 +    }
 +
 +    return 0;
 +}
 +
-+static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
++static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
 +                                       target_ulong *val)
 +{
-+    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
++    /* We don't set MAEE here, because QEMU does not implement MAEE. */
-+
++    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
-+    acc->cpu_class_init = tcg_cpu_class_init;
++    return RISCV_EXCP_NONE;
 +}
 +
-+static const TypeInfo tcg_cpu_accel_type_info = {
++static riscv_csr th_csr_list[] = {
-+    .name = ACCEL_CPU_NAME("tcg"),
++    {
-+
++        .csrno = CSR_TH_SXSTATUS,
-+    .parent = TYPE_ACCEL_CPU,
++        .insertion_test = test_thead_mvendorid,
-+    .class_init = tcg_cpu_accel_class_init,
++        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
-+    .abstract = true,
++    }
 +};
 +
-+static void tcg_cpu_accel_register_types(void)
++void th_register_custom_csrs(RISCVCPU *cpu)
 +{
-+    type_register_static(&tcg_cpu_accel_type_info);
++    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
 +}
-+type_init(tcg_cpu_accel_register_types);
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
 @@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
+   'monitor.c',
+   'machine.c',
+   'pmu.c',
++  'th_csr.c',
+   'time_helper.c',
    'riscv-qmp-cmds.c',
  ))
-+subdir('tcg')
-+
- target_arch += {'riscv': riscv_ss}
- target_system_arch += {'riscv': riscv_system_ss}
-diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/riscv/tcg/meson.build
-@@ -XXX,XX +XXX,XX @@
-+riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
-+  'tcg-cpu.c'))
 --
-.41.0
+.45.1

-[PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Max Chou <max.chou@sifive.com>
-Priv spec validation is TCG specific. Move it to the TCG accel class.
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
 instructions will be affected by Zvfhmin extension.
 And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
 conversions of
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+* From 1*SEW(16/32) to 2*SEW(32/64)
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+* From 2*SEW(32/64) to 1*SEW(16/32)
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Message-ID: <20230925175709.35696-20-dbarboza@ventanamicro.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  2 --
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
- target/riscv/cpu.c         | 38 --------------------------------------
+file changed, 18 insertions(+), 2 deletions(-)
  target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
 files changed, 38 insertions(+), 40 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
  /* used by tcg/tcg-cpu.c*/
  void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
  bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 -int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
  void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
 -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
  typedef struct RISCVCPUMultiExtConfig {
      const char *name;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
      *ext_enabled = en;
  }
 -int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 -{
 -    const RISCVIsaExtData *edata;
 -
 -    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 -        if (edata->ext_enable_offset != ext_offset) {
 -            continue;
 -        }
 -
 -        return edata->min_version;
 -    }
 -
 -    g_assert_not_reached();
 -}
 -
  const char * const riscv_int_regnames[] = {
      "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
      "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
      }
  }
--void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
++static bool require_rvfmin(DisasContext *s)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    const RISCVIsaExtData *edata;
 -
 -    /* Force disable extensions if priv spec version does not match */
 -    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 -        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
 -            (env->priv_ver < edata->min_version)) {
 -            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 -#ifndef CONFIG_USER_ONLY
 -            warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
 -                        " because privilege spec version does not match",
 -                        edata->name, env->mhartid);
 -#else
 -            warn_report("disabling %s extension because "
 -                        "privilege spec version does not match",
 -                        edata->name);
 -#endif
 -        }
 -    }
 -}
 -
  #ifndef CONFIG_USER_ONLY
  static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
  {
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps riscv_tcg_ops = {
  #endif /* !CONFIG_USER_ONLY */
  };
 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 +{
-+    const RISCVIsaExtData *edata;
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-+
++        return false;
 +    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 +        if (edata->ext_enable_offset != ext_offset) {
 +            continue;
 +        }
 +
 +        return edata->min_version;
 +    }
 +
-+    g_assert_not_reached();
++    switch (s->sew) {
-+}
++    case MO_16:
-+
++        return s->cfg_ptr->ext_zvfhmin;
- static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
++    case MO_32:
-                                     bool value)
++        return s->cfg_ptr->ext_zve32f;
- {
++    default:
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
++        return false;
      }
  }
 +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 +{
 +    CPURISCVState *env = &cpu->env;
 +    const RISCVIsaExtData *edata;
 +
 +    /* Force disable extensions if priv spec version does not match */
 +    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 +        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
 +            (env->priv_ver < edata->min_version)) {
 +            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 +#ifndef CONFIG_USER_ONLY
 +            warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
 +                        " because privilege spec version does not match",
 +                        edata->name, env->mhartid);
 +#else
 +            warn_report("disabling %s extension because "
 +                        "privilege spec version does not match",
 +                        edata->name);
 +#endif
 +        }
 +    }
 +}
 +
- /*
+ static bool require_scale_rvf(DisasContext *s)
-  * Check consistency between chosen extensions while setting
+ {
-  * cpu->cfg accordingly.
+     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
      }
      switch (s->sew) {
 -    case MO_8:
 -        return s->cfg_ptr->ext_zvfhmin;
      case MO_16:
          return s->cfg_ptr->ext_zve32f;
      case MO_32:
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
  static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
 --
-.41.0
+.45.1

-[PULL 54/54] target/riscv: Fix vfwmaccbf16.vf
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
 From: Max Chou <max.chou@sifive.com>
-The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
+The require_scale_rvf function only checks the double width operator for
-replaced by fwmaccbf16.
+the vector floating point widen instructions, so most of the widen
 checking functions need to add require_rvf for single width operator.
-Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
 integer to double width float, so the opfxv_widen_check function doesn’t
 need require_rvf for the single width operator(integer).
 Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-ID: <20231005095734.567575-1-max.chou@sifive.com>
+Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/vector_helper.c | 2 +-
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 5 insertions(+)
-diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/vector_helper.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/vector_helper.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
- RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16)
+ {
- GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
+     return require_rvv(s) &&
--RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
++           require_rvf(s) &&
-+RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16)
+            require_scale_rvf(s) &&
- GEN_VEXT_VF(vfwmaccbf16_vf, 4)
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
- static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
  static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
  static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
 --
-.41.0
+.45.1

-[PULL 03/54] target/riscv/cpu.c: split kvm prop handling to its own helper
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Max Chou <max.chou@sifive.com>
-Future patches will split the existing Property arrays even further, and
+The opfv_narrow_check needs to check the single width float operator by
-the existing code in riscv_cpu_add_user_properties() will start to scale
+require_rvf.
 bad with it because it's dealing with KVM constraints mixed in with TCG
 constraints. We're going to pay a high price to share a couple of common
 lines of code between the two.
-Create a new kvm_riscv_cpu_add_kvm_properties() helper that will be
+Signed-off-by: Max Chou <max.chou@sifive.com>
-forked from riscv_cpu_add_user_properties() if we're running KVM. The
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-helper includes all properties that a KVM CPU will add. The rest of
+Cc: qemu-stable <qemu-stable@nongnu.org>
-riscv_cpu_add_user_properties() body will then be relieved from having
+Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 to deal with KVM constraints.
 The helper was declared in kvm_stubs.h, while being implemented in
 cpu.c, to allow '--enable-debug' builds to work. The compiler won't
 remove the kvm_riscv_cpu_add_kvm_properties() reference when
 'kvm_enabled()' is false if we end up with an unused function. Even
 though being a KVM only helper we can't implement it in kvm.c due to its
 many dependencies inside cpu.c, so make it public in kvm_riscv.h and
 keep its implementation in cpu.c for now. We'll move it to kvm.c in the
 near future.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230912132423.268494-4-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm_riscv.h |  3 ++
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
- target/riscv/cpu.c       | 65 +++++++++++++++++++++++++---------------
+file changed, 1 insertion(+)
 files changed, 44 insertions(+), 24 deletions(-)
-diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm_riscv.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/kvm_riscv.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
- #ifndef QEMU_KVM_RISCV_H
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
- #define QEMU_KVM_RISCV_H
+ {
+     return opfv_narrow_check(s, a) &&
-+/* Temporarily implemented in cpu.c */
++           require_rvf(s) &&
-+void kvm_riscv_cpu_add_kvm_properties(Object *obj);
+            require_scale_rvf(s) &&
-+
+            (s->sew != MO_8);
  void kvm_riscv_init_user_properties(Object *cpu_obj);
  void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
  void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
      DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
  };
 -#ifndef CONFIG_USER_ONLY
 +#ifdef CONFIG_KVM
  static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                                      const char *name,
                                      void *opaque, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                     propname);
      }
  }
 +
 +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 +{
 +    /* Check if KVM created the property already */
 +    if (object_property_find(obj, prop_name)) {
 +        return;
 +    }
 +
 +    /*
 +     * Set the default to disabled for every extension
 +     * unknown to KVM and error out if the user attempts
 +     * to enable any of them.
 +     */
 +    object_property_add(obj, prop_name, "bool",
 +                        NULL, cpu_set_cfg_unavailable,
 +                        NULL, (void *)prop_name);
 +}
 +
 +void kvm_riscv_cpu_add_kvm_properties(Object *obj)
 +{
 +    Property *prop;
 +    DeviceState *dev = DEVICE(obj);
 +
 +    kvm_riscv_init_user_properties(obj);
 +    riscv_cpu_add_misa_properties(obj);
 +
 +    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
 +        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
 +    }
 +
 +    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
 +        /* Check if KVM created the property already */
 +        if (object_property_find(obj, riscv_cpu_options[i].name)) {
 +            continue;
 +        }
 +        qdev_property_add_static(dev, &riscv_cpu_options[i]);
 +    }
 +}
  #endif
  /*
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
      riscv_add_satp_mode_properties(obj);
      if (kvm_enabled()) {
 -        kvm_riscv_init_user_properties(obj);
 +        kvm_riscv_cpu_add_kvm_properties(obj);
 +        return;
      }
  #endif
      riscv_cpu_add_misa_properties(obj);
      for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
 -#ifndef CONFIG_USER_ONLY
 -        if (kvm_enabled()) {
 -            /* Check if KVM created the property already */
 -            if (object_property_find(obj, prop->name)) {
 -                continue;
 -            }
 -
 -            /*
 -             * Set the default to disabled for every extension
 -             * unknown to KVM and error out if the user attempts
 -             * to enable any of them.
 -             */
 -            object_property_add(obj, prop->name, "bool",
 -                                NULL, cpu_set_cfg_unavailable,
 -                                NULL, (void *)prop->name);
 -            continue;
 -        }
 -#endif
          qdev_property_add_static(dev, prop);
      }
      for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
 -        /* Check if KVM created the property already */
 -        if (object_property_find(obj, riscv_cpu_options[i].name)) {
 -            continue;
 -        }
          qdev_property_add_static(dev, &riscv_cpu_options[i]);
      }
  }
 --
-.41.0
+.45.1

-[PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Max Chou <max.chou@sifive.com>
-If we want to make better decisions when auto-enabling extensions during
+If the checking functions check both the single and double width
-realize() we need a way to tell if an user set an extension manually.
+operators at the same time, then the single width operator checking
-The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
+functions (require_rvf[min]) will check whether the SEW is 8.
 that has an 'user_set' flag that is set during the Property set()
 callback. The set() callback also does init() time validations based on
 the current KVM driver capabilities.
-For TCG we would want a 'user_set' mechanic too, but we would look
+Signed-off-by: Max Chou <max.chou@sifive.com>
-ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-or not. If we copy what was made in the KVM side we would look for
+Cc: qemu-stable <qemu-stable@nongnu.org>
-'user_set' for one into 60+ extension structs spreaded in 3 arrays
+Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 (riscv_cpu_extensions, riscv_cpu_experimental_exts,
 riscv_cpu_vendor_exts).
 We'll still need an extension struct but we won't be using the
 'user_set' flag:
 - 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to what
 we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'.
 DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by
 MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct;
 - the 'multi_ext_user_opts' hash will be used to store the offset of each
 extension that the user set via the set() callback, cpu_set_multi_ext_cfg().
 For now we're just initializing and populating it - next patch will use
 it to determine if a certain extension was user set;
 - cpu_add_multi_ext_prop() is a new helper that will replace the
 qdev_property_add_static() calls that our macros are doing to populate
 user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY()
 for clarity. Note that the non-extension properties in
 riscv_cpu_options[] still need to be declared via qdev().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230912132423.268494-18-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 258 ++++++++++++++++++++++++++++-----------------
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
-file changed, 159 insertions(+), 99 deletions(-)
+file changed, 4 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/cpu.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
-     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+     return require_rvv(s) &&
- };
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
-+/* Hash that stores user set extensions */
+-           (s->sew != MO_8) &&
-+static GHashTable *multi_ext_user_opts;
+            vext_check_isa_ill(s) &&
-+
+            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
- static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+ }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_ds(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dd(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
-     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
+     return opfv_widen_check(s, a) &&
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
+            require_rvfmin(s) &&
-     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
+-           require_scale_rvfmin(s) &&
-                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
+-           (s->sew != MO_8);
- #endif /* CONFIG_USER_ONLY */
++           require_scale_rvfmin(s);
 +
 +    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
  }
- typedef struct RISCVCPUMisaExtConfig {
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-     }
+ {
      return opfv_narrow_check(s, a) &&
             require_rvfmin(s) &&
 -           require_scale_rvfmin(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvfmin(s);
  }
--static Property riscv_cpu_extensions[] = {
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 +typedef struct RISCVCPUMultiExtConfig {
 +    const char *name;
 +    uint32_t offset;
 +    bool enabled;
 +} RISCVCPUMultiExtConfig;
 +
 +#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
 +    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
 +     .enabled = _defval}
 +
 +static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      /* Defaults for standard extensions */
 -    DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
 -    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 -    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 -    DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true),
 -    DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
 -    DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
 -    DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true),
 -    DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
 -    DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
 -    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
 -    DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
 -    DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
 -    DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
 -
 -    DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
 -    DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
 -    DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
 -    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
 -    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
 -
 -    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
 -    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
 -    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
 -    DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
 -    DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
 -    DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
 -    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
 -    DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
 -    DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
 -    DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
 -    DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
 -    DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
 -    DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
 -    DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
 -    DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
 -    DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
 -    DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
 -
 -    DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
 -    DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
 -    DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
 -    DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
 -
 -    DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
 -    DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
 -
 -    DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
 -
 -    DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
 -    DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
 -    DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
 -    DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
 -    DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
 -    DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
 -    DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
 -    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
 +    MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
 +    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
 +    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
 +    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
 +    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
 +    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
 +    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
 +    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
 +    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
 +    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
 +    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
 +
 +    MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
 +    MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
 +    MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
 +    MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
 +    MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
 +
 +    MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
 +    MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
 +    MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
 +    MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
 +    MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
 +    MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
 +    MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
 +    MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
 +    MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
 +    MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
 +    MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
 +    MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
 +    MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
 +    MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
 +    MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
 +    MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
 +    MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
 +
 +    MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
 +    MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
 +    MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
 +    MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
 +
 +    MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
 +    MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
 +
 +    MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
 +
 +    MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
 +    MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
 +    MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
 +    MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
 +    MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
 +    MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
 +    MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
 +    MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
      DEFINE_PROP_END_OF_LIST(),
  };
 -static Property riscv_cpu_vendor_exts[] = {
 -    DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
 -    DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
 -    DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
 -    DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
 -    DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
 -    DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
 -    DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
 -    DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
 -    DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
 -    DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
 -    DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
 -    DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 +static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 +    MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
 +    MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
 +    MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
 +    MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
 +    MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
 +    MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
 +    MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
 +    MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
 +    MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
 +    MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
 +    MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
 +    MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
      DEFINE_PROP_END_OF_LIST(),
  };
  /* These are experimental so mark with 'x-' */
 -static Property riscv_cpu_experimental_exts[] = {
 +static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
      /* ePMP 0.9.3 */
 -    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 -    DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
 -    DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
 +    MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
 +    MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
 +    MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
 -    DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
 -    DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
 -    DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
 -    DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
 -    DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
 +    MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
      /* Vector cryptography extensions */
 -    DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
 -    DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
 -    DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
 -    DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
 -    DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
 -    DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
 -    DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
 -    DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
 +    MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
 +    MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
 +    MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
 +    MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
 +    MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
 +    MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
 +    MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
 +    MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 -static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
 +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 +                                  void *opaque, Error **errp)
 +{
 +    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 +    bool value;
 +
 +    if (!visit_type_bool(v, name, &value, errp)) {
 +        return;
 +    }
 +
 +    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
 +
 +    g_hash_table_insert(multi_ext_user_opts,
 +                        GUINT_TO_POINTER(multi_ext_cfg->offset),
 +                        (gpointer)value);
 +}
 +
 +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 +                                  void *opaque, Error **errp)
 +{
 +    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 +    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
 +
 +    visit_type_bool(v, name, &value, errp);
 +}
 +
 +static void cpu_add_multi_ext_prop(Object *cpu_obj,
 +                                   RISCVCPUMultiExtConfig *multi_cfg)
 +{
 +    object_property_add(cpu_obj, multi_cfg->name, "bool",
 +                        cpu_get_multi_ext_cfg,
 +                        cpu_set_multi_ext_cfg,
 +                        NULL, (void *)multi_cfg);
 +
 +    /*
 +     * Set def val directly instead of using
 +     * object_property_set_bool() to save the set()
 +     * callback hash for user inputs.
 +     */
 +    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
 +                           multi_cfg->enabled);
 +}
 +
 +static void riscv_cpu_add_multiext_prop_array(Object *obj,
 +                                              RISCVCPUMultiExtConfig *array)
  {
-     g_assert(array);
+     return opfv_narrow_check(s, a) &&
+            require_rvf(s) &&
--    for (Property *prop = array; prop && prop->name; prop++) {
+-           require_scale_rvf(s) &&
--        qdev_property_add_static(dev, prop);
+-           (s->sew != MO_8);
-+    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
++           require_scale_rvf(s);
 +        cpu_add_multi_ext_prop(obj, prop);
      }
  }
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
- static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 -                                                 Property *array)
 +                                                 RISCVCPUMultiExtConfig *array)
  {
      g_assert(array);
 -    for (Property *prop = array; prop && prop->name; prop++) {
 +    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
          riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
      }
  }
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
   */
  static void riscv_cpu_add_user_properties(Object *obj)
  {
 -    DeviceState *dev = DEVICE(obj);
 -
  #ifndef CONFIG_USER_ONLY
      riscv_add_satp_mode_properties(obj);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
      riscv_cpu_add_misa_properties(obj);
 -    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
 -    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
 -    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
 -    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
 +    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
 +    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
 +    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
 +
 +    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
 +        qdev_property_add_static(DEVICE(obj), prop);
 +    }
  }
  /*
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
  {
      RISCVCPU *cpu = RISCV_CPU(obj);
      CPURISCVState *env = &cpu->env;
 -    Property *prop;
 +    RISCVCPUMultiExtConfig *prop;
      /* Enable RVG, RVJ and RVV that are disabled by default */
      set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 --
-.41.0
+.45.1

-[PULL 32/54] target/riscv: remove kvm-stub.c
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
-and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
+checking first if virt_enabled && !first_stage, and then considering the
-wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
+regular inst/load/store faults.
 in non-KVM builds.
+There's no mention in the spec about guest page fault being a higher
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
+"Attempting to fetch an instruction from a PMP region that does not have
+execute permissions raises an instruction access-fault exception.
+Attempting to execute a load or load-reserved instruction which accesses
+a physical address within a PMP region without read permissions raises a
+load access-fault exception. Attempting to execute a store,
+store-conditional, or AMO instruction which accesses a physical address
+within a PMP region without write permissions raises a store
+access-fault exception."
+So, in fact, we're doing it wrong - PMP faults should always be thrown,
+regardless of also being a first or second stage fault.
+The way riscv_cpu_tlb_fill() and get_physical_address() work is
+adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
+reflected in the 'pmp_violation' flag. What we need is to change
+raise_mmu_exception() to prioritize it.
+Reported-by: Joseph Chan <jchan@ventanamicro.com>
+Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com>
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm-stub.c  | 30 ------------------------------
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
- target/riscv/meson.build |  2 +-
+file changed, 12 insertions(+), 10 deletions(-)
 files changed, 1 insertion(+), 31 deletions(-)
  delete mode 100644 target/riscv/kvm-stub.c
-diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/target/riscv/kvm-stub.c
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -/*
 - * QEMU KVM RISC-V specific function stubs
 - *
 - * Copyright (c) 2020 Huawei Technologies Co., Ltd
 - *
 - * This program is free software; you can redistribute it and/or modify it
 - * under the terms and conditions of the GNU General Public License,
 - * version 2 or later, as published by the Free Software Foundation.
 - *
 - * This program is distributed in the hope it will be useful, but WITHOUT
 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 - * more details.
 - *
 - * You should have received a copy of the GNU General Public License along with
 - * this program.  If not, see <http://www.gnu.org/licenses/>.
 - */
 -#include "qemu/osdep.h"
 -#include "cpu.h"
 -#include "kvm_riscv.h"
 -
 -void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 -{
 -    abort();
 -}
 -
 -void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
 -{
 -    abort();
 -}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/meson.build
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/meson.build
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-   'zce_helper.c',
-   'vcrypto_helper.c'
+     switch (access_type) {
- ))
+     case MMU_INST_FETCH:
--riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
+-        if (env->virt_enabled && !first_stage) {
-+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
++        if (pmp_violation) {
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
- riscv_system_ss = ss.source_set()
++        } else if (env->virt_enabled && !first_stage) {
- riscv_system_ss.add(files(
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
          }
          break;
      case MMU_DATA_LOAD:
 -        if (two_stage && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
          }
          break;
      case MMU_DATA_STORE:
 -        if (two_stage && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
 -                RISCV_EXCP_STORE_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
          }
          break;
      default:
 --
-.41.0
+.45.1

-[PULL 52/54] target/riscv: Use env_archcpu for better performance
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
-From: "Richard W.M. Jones" <rjones@redhat.com>
+From: Alexei Filippov <alexei.filippov@syntacore.com>
-RISCV_CPU(cs) uses a checked cast.  When QOM cast debugging is enabled
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
-this adds about 5% total overhead when emulating RV64 on x86-64 host.
+setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
 translation part, mtval2 will be set in case of successes 2 stage translation but
 failed pmp check.
-Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
-disk.  The guest has a copy of the qemu source tree.  The test
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
-involves compiling the qemu source tree with 'make clean; time make -j16'.
+should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
-Before making this change the compile step took 449 & 447 seconds over
+Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
-two consecutive runs.
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 After making this change: 428 & 421 seconds.
 The saving is over 5%.
 Thanks: Paolo Bonzini
 Thanks: Philippe Mathieu-Daudé
 Signed-off-by: Richard W.M. Jones <rjones@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20231009124859.3373696-2-rjones@redhat.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 3 +--
+ target/riscv/cpu_helper.c | 12 ++++++------
-file changed, 1 insertion(+), 2 deletions(-)
+file changed, 6 insertions(+), 6 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+                               __func__, pa, ret, prot_pmp, tlb_size);
-                           uint64_t *cs_base, uint32_t *pflags)
- {
+                 prot &= prot_pmp;
--    CPUState *cs = env_cpu(env);
+-            }
--    RISCVCPU *cpu = RISCV_CPU(cs);
+-
-+    RISCVCPU *cpu = env_archcpu(env);
+-            if (ret != TRANSLATE_SUCCESS) {
-     RISCVExtStatus fs, vs;
++            } else {
-     uint32_t flags = 0;
+                 /*
+                  * Guest physical address translation failed, this is a HS
                   * level exception
                   */
                  first_stage_error = false;
 -                env->guest_phys_fault_addr = (im_address |
 -                                              (address &
 -                                               (TARGET_PAGE_SIZE - 1))) >> 2;
 +                if (ret != TRANSLATE_PMP_FAIL) {
 +                    env->guest_phys_fault_addr = (im_address |
 +                                                  (address &
 +                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
 +                }
              }
          }
      } else {
 --
-.41.0
+.45.1

-[PULL 36/54] target/riscv/cpu.c: export set_misa()
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Rob Bradford <rbradford@rivosinc.com>
-We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
+This extension has now been ratified:
-patch and set_misa() needs to be usable from there.
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
 removed.
-Rename it to riscv_cpu_set_misa() and make it public.
+Since this is now a ratified extension add it to the list of extensions
 included in the "max" CPU variant.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-15-dbarboza@ventanamicro.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h |  1 +
+ target/riscv/cpu.c         | 2 +-
- target/riscv/cpu.c | 34 ++++++++++++++++++----------------
+ target/riscv/tcg/tcg-cpu.c | 2 +-
-files changed, 19 insertions(+), 16 deletions(-)
+files changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
- bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
- bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
- int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
-+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
- void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
- typedef struct RISCVCPUMultiExtConfig {
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
-     }
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
- }
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
--static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
-+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
- {
+ };
-     env->misa_mxl_max = env->misa_mxl = mxl;
-     env->misa_ext_mask = env->misa_ext = ext;
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
-@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-     RISCVCPU *cpu = RISCV_CPU(obj);
+index XXXXXXX..XXXXXXX 100644
-     CPURISCVState *env = &cpu->env;
+--- a/target/riscv/tcg/tcg-cpu.c
- #if defined(TARGET_RISCV32)
++++ b/target/riscv/tcg/tcg-cpu.c
 -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  #elif defined(TARGET_RISCV64)
 -    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  #endif
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
  #ifdef TARGET_RISCV32
      mlx = MXL_RV32;
  #endif
 -    set_misa(env, mlx, 0);
 +    riscv_cpu_set_misa(env, mlx, 0);
      env->priv_ver = PRIV_VERSION_LATEST;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
 -    set_misa(env, MXL_RV64, 0);
 +    riscv_cpu_set_misa(env, MXL_RV64, 0);
      /* Set latest version of privileged specification */
      env->priv_ver = PRIV_VERSION_LATEST;
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
  {
      RISCVCPU *cpu = RISCV_CPU(obj);
      CPURISCVState *env = &cpu->env;
 -    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV64,
 +                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      env->priv_ver = PRIV_VERSION_1_10_0;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      RISCVCPU *cpu = RISCV_CPU(obj);
 -    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
      env->priv_ver = PRIV_VERSION_1_10_0;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      RISCVCPU *cpu = RISCV_CPU(obj);
 -    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
      env->priv_ver = PRIV_VERSION_1_11_0;
      cpu->cfg.ext_zfa = true;
@@ -XXX,XX +XXX,XX @@ static void rv64_veyron_v1_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      RISCVCPU *cpu = RISCV_CPU(obj);
 -    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
 +    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
      env->priv_ver = PRIV_VERSION_1_12_0;
      /* Enable ISA extensions */
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
      }
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
 -    set_misa(env, MXL_RV128, 0);
 +    riscv_cpu_set_misa(env, MXL_RV128, 0);
      /* Set latest version of privileged specification */
      env->priv_ver = PRIV_VERSION_LATEST;
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
 -    set_misa(env, MXL_RV32, 0);
 +    riscv_cpu_set_misa(env, MXL_RV32, 0);
      /* Set latest version of privileged specification */
      env->priv_ver = PRIV_VERSION_LATEST;
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
  {
      RISCVCPU *cpu = RISCV_CPU(obj);
      CPURISCVState *env = &cpu->env;
 -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV32,
 +                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      env->priv_ver = PRIV_VERSION_1_10_0;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      RISCVCPU *cpu = RISCV_CPU(obj);
 -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
      env->priv_ver = PRIV_VERSION_1_10_0;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      RISCVCPU *cpu = RISCV_CPU(obj);
 -    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
      env->priv_ver = PRIV_VERSION_1_11_0;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      RISCVCPU *cpu = RISCV_CPU(obj);
 -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
 +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
      env->priv_ver = PRIV_VERSION_1_10_0;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
 @@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
      const RISCVCPUMultiExtConfig *prop;
      /* Enable RVG, RVJ and RVV that are disabled by default */
--    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
-+    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
++    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
      for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
          isa_ext_update_enabled(cpu, prop->offset, true);
 --
-.41.0
+.45.1

-[PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Alistair Francis <alistair23@gmail.com>
-Move the remaining of riscv_tcg_ops now that we have a working realize()
+When running the instruction
 implementation.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+```
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+    cbo.flush 0(x0)
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+```
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+QEMU would segfault.
-Message-ID: <20230925175709.35696-5-dbarboza@ventanamicro.com>
 The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  4 ---
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
- target/riscv/cpu.c         | 58 ------------------------------------
+file changed, 12 insertions(+), 4 deletions(-)
  target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++-
 files changed, 59 insertions(+), 63 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
-@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
+@@ -XXX,XX +XXX,XX @@
-     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
- };
+ {
+     REQUIRE_ZICBOM(ctx);
--/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
--#include "hw/core/tcg-cpu-ops.h"
++    TCGv src = get_address(ctx, a->rs1, 0);
--extern const struct TCGCPUOps riscv_tcg_ops;
++
--
++    gen_helper_cbo_clean_flush(tcg_env, src);
- /* used by tcg/tcg-cpu.c*/
+     return true;
  void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
  bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
      return env->pc;
  }
--static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 -                                          const TranslationBlock *tb)
 -{
 -    if (!(tb_cflags(tb) & CF_PCREL)) {
 -        RISCVCPU *cpu = RISCV_CPU(cs);
 -        CPURISCVState *env = &cpu->env;
 -        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 -
 -        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
 -
 -        if (xl == MXL_RV32) {
 -            env->pc = (int32_t) tb->pc;
 -        } else {
 -            env->pc = tb->pc;
 -        }
 -    }
 -}
 -
  static bool riscv_cpu_has_work(CPUState *cs)
  {
- #ifndef CONFIG_USER_ONLY
+     REQUIRE_ZICBOM(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
- #endif
++    TCGv src = get_address(ctx, a->rs1, 0);
 +
 +    gen_helper_cbo_clean_flush(tcg_env, src);
      return true;
  }
--static void riscv_restore_state_to_opc(CPUState *cs,
+ static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 -                                       const TranslationBlock *tb,
 -                                       const uint64_t *data)
 -{
 -    RISCVCPU *cpu = RISCV_CPU(cs);
 -    CPURISCVState *env = &cpu->env;
 -    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 -    target_ulong pc;
 -
 -    if (tb_cflags(tb) & CF_PCREL) {
 -        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
 -    } else {
 -        pc = data[0];
 -    }
 -
 -    if (xl == MXL_RV32) {
 -        env->pc = (int32_t)pc;
 -    } else {
 -        env->pc = pc;
 -    }
 -    env->bins = data[1];
 -}
 -
  static void riscv_cpu_reset_hold(Object *obj)
  {
- #ifndef CONFIG_USER_ONLY
+     REQUIRE_ZICBOM(ctx);
-@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
- };
++    TCGv src = get_address(ctx, a->rs1, 0);
- #endif
++
++    gen_helper_cbo_inval(tcg_env, src);
--const struct TCGCPUOps riscv_tcg_ops = {
+     return true;
--    .initialize = riscv_translate_init,
+ }
--    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
--    .restore_state_to_opc = riscv_restore_state_to_opc,
+ static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 -
 -#ifndef CONFIG_USER_ONLY
 -    .tlb_fill = riscv_cpu_tlb_fill,
 -    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 -    .do_interrupt = riscv_cpu_do_interrupt,
 -    .do_transaction_failed = riscv_cpu_do_transaction_failed,
 -    .do_unaligned_access = riscv_cpu_do_unaligned_access,
 -    .debug_excp_handler = riscv_cpu_debug_excp_handler,
 -    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
 -    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
 -#endif /* !CONFIG_USER_ONLY */
 -};
 -
  static bool riscv_cpu_is_dynamic(Object *cpu_obj)
  {
-     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+     REQUIRE_ZICBOZ(ctx);
-diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
-index XXXXXXX..XXXXXXX 100644
++    TCGv src = get_address(ctx, a->rs1, 0);
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/error-report.h"
  #include "qemu/log.h"
  #include "hw/core/accel-cpu.h"
 +#include "hw/core/tcg-cpu-ops.h"
 +#include "tcg/tcg.h"
 +static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 +                                          const TranslationBlock *tb)
 +{
 +    if (!(tb_cflags(tb) & CF_PCREL)) {
 +        RISCVCPU *cpu = RISCV_CPU(cs);
 +        CPURISCVState *env = &cpu->env;
 +        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 +
-+        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
++    gen_helper_cbo_zero(tcg_env, src);
-+
+     return true;
 +        if (xl == MXL_RV32) {
 +            env->pc = (int32_t) tb->pc;
 +        } else {
 +            env->pc = tb->pc;
 +        }
 +    }
 +}
 +
 +static void riscv_restore_state_to_opc(CPUState *cs,
 +                                       const TranslationBlock *tb,
 +                                       const uint64_t *data)
 +{
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    CPURISCVState *env = &cpu->env;
 +    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 +    target_ulong pc;
 +
 +    if (tb_cflags(tb) & CF_PCREL) {
 +        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
 +    } else {
 +        pc = data[0];
 +    }
 +
 +    if (xl == MXL_RV32) {
 +        env->pc = (int32_t)pc;
 +    } else {
 +        env->pc = pc;
 +    }
 +    env->bins = data[1];
 +}
 +
 +static const struct TCGCPUOps riscv_tcg_ops = {
 +    .initialize = riscv_translate_init,
 +    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
 +    .restore_state_to_opc = riscv_restore_state_to_opc,
 +
 +#ifndef CONFIG_USER_ONLY
 +    .tlb_fill = riscv_cpu_tlb_fill,
 +    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 +    .do_interrupt = riscv_cpu_do_interrupt,
 +    .do_transaction_failed = riscv_cpu_do_transaction_failed,
 +    .do_unaligned_access = riscv_cpu_do_unaligned_access,
 +    .debug_excp_handler = riscv_cpu_debug_excp_handler,
 +    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
 +    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
 +#endif /* !CONFIG_USER_ONLY */
 +};
  static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
                                      bool value)
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
  {
      /*
       * All cpus use the same set of operations.
 -     * riscv_tcg_ops is being imported from cpu.c for now.
       */
      cc->tcg_ops = &riscv_tcg_ops;
  }
 --
-.41.0
+.45.1

-[PULL 50/54] target/riscv/kvm: support KVM_GET_REG_LIST
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It
+In AIA spec, each hart (or each hart within a group) has a unique hart
-consists of a KVM ioctl() that retrieves a list of all available regs
+number to locate the memory pages of interrupt files in the address
-for get_one_reg/set_one_reg. Regs that aren't present in the list aren't
+space. The number of bits required to represent any hart number is equal
-supported in the host.
+to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
-This simplifies our lives when initing the KVM regs since we don't have
+However, if the largest hart number among groups is a power of 2, QEMU
-to always attempt a KVM_GET_ONE_REG for all regs QEMU knows. We'll only
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
-attempt a get_one_reg() if we're sure the reg is supported, i.e. it was
+the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
-retrieved by KVM_GET_REG_LIST. Any error in get_one_reg() will then
+to represent 4 harts, but we passes 3 to Linux. The code needs to be
-always considered fatal, instead of having to handle special error codes
+updated to ensure accurate hart-index-bit settings.
 that might indicate a non-fatal failure.
-Start by moving the current kvm_riscv_init_multiext_cfg() logic into a
+Additionally, a Linux patch[1] is necessary to correctly recover the hart
-new kvm_riscv_read_multiext_legacy() helper. We'll prioritize using
+index when the guest OS has only 1 hart, where the hart-index-bit is 0.
 KVM_GET_REG_LIST, so check if we have it available and, in case we
 don't, use the legacy() logic.
-Otherwise, retrieve the available reg list and use it to check if the
+[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
 host supports our known KVM regs, doing the usual get_one_reg() for
 the supported regs and setting cpu->cfg accordingly.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20231003132148.797921-3-dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm/kvm-cpu.c | 96 +++++++++++++++++++++++++++++++++++++-
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
-file changed, 95 insertions(+), 1 deletion(-)
+file changed, 8 insertions(+), 1 deletion(-)
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
          }
      }
- }
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
 -static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
 +static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
 +                                           KVMScratchCPU *kvmcpu)
  {
      CPURISCVState *env = &cpu->env;
      uint64_t val;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      }
  }
 +static int uint64_cmp(const void *a, const void *b)
 +{
 +    uint64_t val1 = *(const uint64_t *)a;
 +    uint64_t val2 = *(const uint64_t *)b;
 +
-+    if (val1 < val2) {
++    if (max_hart_per_socket > 1) {
-+        return -1;
++        max_hart_per_socket--;
 +        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
 +    } else {
 +        hart_bits = 0;
 +    }
 +
-+    if (val1 > val2) {
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-+        return 1;
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-+    }
+                             &hart_bits, true, NULL);
 +
 +    return 0;
 +}
 +
 +static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
 +{
 +    KVMCPUConfig *multi_ext_cfg;
 +    struct kvm_one_reg reg;
 +    struct kvm_reg_list rl_struct;
 +    struct kvm_reg_list *reglist;
 +    uint64_t val, reg_id, *reg_search;
 +    int i, ret;
 +
 +    rl_struct.n = 0;
 +    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct);
 +
 +    /*
 +     * If KVM_GET_REG_LIST isn't supported we'll get errno 22
 +     * (EINVAL). Use read_legacy() in this case.
 +     */
 +    if (errno == EINVAL) {
 +        return kvm_riscv_read_multiext_legacy(cpu, kvmcpu);
 +    } else if (errno != E2BIG) {
 +        /*
 +         * E2BIG is an expected error message for the API since we
 +         * don't know the number of registers. The right amount will
 +         * be written in rl_struct.n.
 +         *
 +         * Error out if we get any other errno.
 +         */
 +        error_report("Error when accessing get-reg-list, code: %s",
 +                     strerrorname_np(errno));
 +        exit(EXIT_FAILURE);
 +    }
 +
 +    reglist = g_malloc(sizeof(struct kvm_reg_list) +
 +                       rl_struct.n * sizeof(uint64_t));
 +    reglist->n = rl_struct.n;
 +    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist);
 +    if (ret) {
 +        error_report("Error when reading KVM_GET_REG_LIST, code %s ",
 +                     strerrorname_np(errno));
 +        exit(EXIT_FAILURE);
 +    }
 +
 +    /* sort reglist to use bsearch() */
 +    qsort(&reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp);
 +
 +    for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
 +        multi_ext_cfg = &kvm_multi_ext_cfgs[i];
 +        reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT,
 +                                  multi_ext_cfg->kvm_reg_id);
 +        reg_search = bsearch(&reg_id, reglist->reg, reglist->n,
 +                             sizeof(uint64_t), uint64_cmp);
 +        if (!reg_search) {
 +            continue;
 +        }
 +
 +        reg.id = reg_id;
 +        reg.addr = (uint64_t)&val;
 +        ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg);
 +        if (ret != 0) {
 +            error_report("Unable to read ISA_EXT KVM register %s, "
 +                         "error code: %s", multi_ext_cfg->name,
 +                         strerrorname_np(errno));
 +            exit(EXIT_FAILURE);
 +        }
 +
 +        multi_ext_cfg->supported = true;
 +        kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
 +    }
 +
 +    if (cpu->cfg.ext_icbom) {
 +        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
 +    }
 +
 +    if (cpu->cfg.ext_icboz) {
 +        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
 +    }
 +}
 +
  static void riscv_init_kvm_registers(Object *cpu_obj)
  {
      RISCVCPU *cpu = RISCV_CPU(cpu_obj);
 --
-.41.0
+.45.1

-[PULL 04/54] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-iterating in the riscv_cpu_options[] array, making it similar to what
+in bytes, when in this context we want 'reg_width' as the length in
-we already do when working with riscv_cpu_extensions[].
+bits.
-We also have a more sophisticated motivation behind this change. In the
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
-future we might need to export riscv_cpu_options[] to other files, and
+("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
-ARRAY_LIST() doesn't work properly in that case because the array size
+beforehand.
 isn't exposed to the header file. Here's a future sight of what we would
 deal with:
-./target/riscv/kvm.c:1057:5: error: nested extern declaration of 'riscv_cpu_add_misa_properties' [-Werror=nested-externs]
+While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
-n file included from ../target/riscv/kvm.c:19:
+clarity about what the variable represents. 'bitsize' is also used in
-home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
+riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
-| #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
+gdb_feature_builder_append_reg().
      |                               ^
 ./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
 |         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
      |                             ^~~~~~~~~~
 ./target/riscv/kvm.c:1059:5: note: in expansion of macro 'ADD_UNAVAIL_KVM_PROP_ARRAY'
 |     ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions);
      |     ^~~~~~~~~~~~~~~~~~~~~~~~~~
 home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
      |                               ^
 ./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
 |         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
-Homogenize the present and change the future by using
+Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
-DEFINE_PROP_END_OF_LIST() in riscv_cpu_options[].
+Cc: Alex Bennée <alex.bennee@linaro.org>
+Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-ID: <20230912132423.268494-5-dbarboza@ventanamicro.com>
+Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 12 +++++++-----
+ target/riscv/gdbstub.c | 6 +++---
-file changed, 7 insertions(+), 5 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/target/riscv/gdbstub.c
-+++ b/target/riscv/cpu.c
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-     DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
+ {
-     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+     RISCVCPU *cpu = RISCV_CPU(cs);
-+
+-    int reg_width = cpu->cfg.vlenb;
-+    DEFINE_PROP_END_OF_LIST(),
++    int bitsize = cpu->cfg.vlenb << 3;
- };
+     GDBFeatureBuilder builder;
+     int i;
- #ifdef CONFIG_KVM
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
      /* First define types and totals in a whole VL */
      for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 +        int count = bitsize / vec_lanes[i].size;
          gdb_feature_builder_append_tag(
              &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
              vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* Define vector registers */
      for (i = 0; i < 32; i++) {
          gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
 -                                       reg_width, i, "riscv_vector", "vector");
 +                                       bitsize, i, "riscv_vector", "vector");
      }
--    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+     gdb_feature_builder_end(&builder);
 +    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
          /* Check if KVM created the property already */
 -        if (object_property_find(obj, riscv_cpu_options[i].name)) {
 +        if (object_property_find(obj, prop->name)) {
              continue;
          }
 -        qdev_property_add_static(dev, &riscv_cpu_options[i]);
 +        qdev_property_add_static(dev, prop);
      }
  }
  #endif
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
          qdev_property_add_static(dev, prop);
      }
 -    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
 -        qdev_property_add_static(dev, &riscv_cpu_options[i]);
 +    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
 +        qdev_property_add_static(dev, prop);
      }
  }
 --
-.41.0
+.45.1

-[PULL 05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Create a new riscv_cpu_experimental_exts[] to store the non-ratified
-extensions properties. Once they are ratified we'll move them back to
-riscv_cpu_extensions[].
-riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
-changed to keep adding non-ratified properties to users.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-6-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 13 ++++++++++++-
-file changed, 12 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
-     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
--    /* These are experimental so mark with 'x-' */
-+    DEFINE_PROP_END_OF_LIST(),
-+};
-+/* These are experimental so mark with 'x-' */
-+static Property riscv_cpu_experimental_exts[] = {
-     /* ePMP 0.9.3 */
-     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-     DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-     }
-+    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-+    }
-+
-     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
-         /* Check if KVM created the property already */
-         if (object_property_find(obj, prop->name)) {
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
-     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
-         qdev_property_add_static(dev, prop);
-     }
-+
-+    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-+        qdev_property_add_static(dev, prop);
-+    }
- }
- static Property riscv_cpu_properties[] = {
---
-.41.0

-[PULL 06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Our goal is to make riscv_cpu_extensions[] hold only ratified,
-non-vendor extensions.
-Create a new riscv_cpu_vendor_exts[] array for them, changing
-riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
-accordingly.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-7-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 13 ++++++++++++-
-file changed, 12 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
-     DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
--    /* Vendor-specific custom extensions */
-+    DEFINE_PROP_END_OF_LIST(),
-+};
-+
-+static Property riscv_cpu_vendor_exts[] = {
-     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
-     DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
-     DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-     }
-+    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
-+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-+    }
-+
-     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-     }
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
-         qdev_property_add_static(dev, prop);
-     }
-+    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
-+        qdev_property_add_static(dev, prop);
-+    }
-+
-     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-         qdev_property_add_static(dev, prop);
-     }
---
-.41.0

-[PULL 07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The code inside riscv_cpu_add_user_properties() became quite repetitive
-after recent changes. Add a helper to hide the repetition away.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-ID: <20230912132423.268494-8-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 29 +++++++++++++----------------
-file changed, 13 insertions(+), 16 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
-     DEFINE_PROP_END_OF_LIST(),
- };
-+static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
-+{
-+    g_assert(array);
-+
-+    for (Property *prop = array; prop && prop->name; prop++) {
-+        qdev_property_add_static(dev, prop);
-+    }
-+}
-+
- #ifdef CONFIG_KVM
- static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
-                                     const char *name,
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-  */
- static void riscv_cpu_add_user_properties(Object *obj)
- {
--    Property *prop;
-     DeviceState *dev = DEVICE(obj);
- #ifndef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
-     riscv_cpu_add_misa_properties(obj);
--    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
--        qdev_property_add_static(dev, prop);
--    }
--
--    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
--        qdev_property_add_static(dev, prop);
--    }
--
--    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
--        qdev_property_add_static(dev, prop);
--    }
--
--    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
--        qdev_property_add_static(dev, prop);
--    }
-+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
-+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
-+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
-+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
- }
- static Property riscv_cpu_properties[] = {
---
-.41.0

-[PULL 08/54] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
-code repetition.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230912132423.268494-9-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 24 +++++++++++++-----------
-file changed, 13 insertions(+), 11 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
-                         NULL, (void *)prop_name);
- }
-+static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-+                                                 Property *array)
-+{
-+    g_assert(array);
-+
-+    for (Property *prop = array; prop && prop->name; prop++) {
-+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-+    }
-+}
-+
- void kvm_riscv_cpu_add_kvm_properties(Object *obj)
- {
-     Property *prop;
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-     kvm_riscv_init_user_properties(obj);
-     riscv_cpu_add_misa_properties(obj);
--    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
--        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
--    }
--
--    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
--        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
--    }
--
--    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
--        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
--    }
-+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
-+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
-+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
-     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
-         /* Check if KVM created the property already */
---
-.41.0

-[PULL 09/54] target/riscv/cpu.c: limit cfg->vext_spec log message
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Inside riscv_cpu_validate_v() we're always throwing a log message if the
-user didn't set a vector version via 'vext_spec'.
-We're going to include one case with the 'max' CPU where env->vext_ver
-will be set in the cpu_init(). But that alone will not stop the "vector
-version is not specified" message from appearing. The usefulness of this
-log message is debatable for the generic CPUs, but for a 'max' CPU type,
-where we are supposed to deliver a CPU model with all features possible,
-it's strange to force users to set 'vext_spec' to get rid of this
-message.
-Change riscv_cpu_validate_v() to not throw this log message if
-env->vext_ver is already set.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Message-ID: <20230912132423.268494-10-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 9 ++++-----
-file changed, 4 insertions(+), 5 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
- static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
-                                  Error **errp)
- {
--    int vext_version = VEXT_VERSION_1_00_0;
--
-     if (!is_power_of_2(cfg->vlen)) {
-         error_setg(errp, "Vector extension VLEN must be power of 2");
-         return;
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
-     }
-     if (cfg->vext_spec) {
-         if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
--            vext_version = VEXT_VERSION_1_00_0;
-+            env->vext_ver = VEXT_VERSION_1_00_0;
-         } else {
-             error_setg(errp, "Unsupported vector spec version '%s'",
-                        cfg->vext_spec);
-             return;
-         }
--    } else {
-+    } else if (env->vext_ver == 0) {
-         qemu_log("vector version is not specified, "
-                  "use the default value v1.0\n");
-+
-+        env->vext_ver = VEXT_VERSION_1_00_0;
-     }
--    env->vext_ver = vext_version;
- }
- static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
---
-.41.0

-[PULL 10/54] target/riscv: add 'max' CPU type
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The 'max' CPU type is used by tooling to determine what's the most
-capable CPU a current QEMU version implements. Other archs such as ARM
-implements this type. Let's add it to RISC-V.
-What we consider "most capable CPU" in this context are related to
-ratified, non-vendor extensions. This means that we want the 'max' CPU
-to enable all (possible) ratified extensions by default. The reasoning
-behind this design is (1) vendor extensions can conflict with each other
-and we won't play favorities deciding which one is default or not and
-(2) non-ratified extensions are always prone to changes, not being
-stable enough to be enabled by default.
-All this said, we're still not able to enable all ratified extensions
-due to conflicts between them. Zfinx and all its dependencies aren't
-enabled because of a conflict with RVF. zce, zcmp and zcmt are also
-disabled due to RVD conflicts. When running with 64 bits we're also
-disabling zcf.
-MISA bits RVG, RVJ and RVV are also being set manually since they're
-default disabled.
-This is the resulting 'riscv,isa' DT for this new CPU:
-rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
-zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
-zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
-smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-11-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu-qom.h |  1 +
- target/riscv/cpu.c     | 56 ++++++++++++++++++++++++++++++++++++++++++
-files changed, 57 insertions(+)
-diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu-qom.h
-+++ b/target/riscv/cpu-qom.h
-@@ -XXX,XX +XXX,XX @@
- #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
- #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
-+#define TYPE_RISCV_CPU_MAX              RISCV_CPU_TYPE_NAME("max")
- #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
- #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
- #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
- };
- static void riscv_cpu_add_user_properties(Object *obj);
-+static void riscv_init_max_cpu_extensions(Object *obj);
- const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
- {
-@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
-     cpu->cfg.pmp = true;
- }
-+static void riscv_max_cpu_init(Object *obj)
-+{
-+    RISCVCPU *cpu = RISCV_CPU(obj);
-+    CPURISCVState *env = &cpu->env;
-+    RISCVMXL mlx = MXL_RV64;
-+
-+#ifdef TARGET_RISCV32
-+    mlx = MXL_RV32;
-+#endif
-+    set_misa(env, mlx, 0);
-+    riscv_cpu_add_user_properties(obj);
-+    riscv_init_max_cpu_extensions(obj);
-+    env->priv_ver = PRIV_VERSION_LATEST;
-+#ifndef CONFIG_USER_ONLY
-+    set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
-+                                VM_1_10_SV32 : VM_1_10_SV57);
-+#endif
-+}
-+
- #if defined(TARGET_RISCV64)
- static void rv64_base_cpu_init(Object *obj)
- {
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
-     riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
- }
-+/*
-+ * The 'max' type CPU will have all possible ratified
-+ * non-vendor extensions enabled.
-+ */
-+static void riscv_init_max_cpu_extensions(Object *obj)
-+{
-+    RISCVCPU *cpu = RISCV_CPU(obj);
-+    CPURISCVState *env = &cpu->env;
-+    Property *prop;
-+
-+    /* Enable RVG, RVJ and RVV that are disabled by default */
-+    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-+
-+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-+        object_property_set_bool(obj, prop->name, true, NULL);
-+    }
-+
-+    /* set vector version */
-+    env->vext_ver = VEXT_VERSION_1_00_0;
-+
-+    /* Zfinx is not compatible with F. Disable it */
-+    object_property_set_bool(obj, "zfinx", false, NULL);
-+    object_property_set_bool(obj, "zdinx", false, NULL);
-+    object_property_set_bool(obj, "zhinx", false, NULL);
-+    object_property_set_bool(obj, "zhinxmin", false, NULL);
-+
-+    object_property_set_bool(obj, "zce", false, NULL);
-+    object_property_set_bool(obj, "zcmp", false, NULL);
-+    object_property_set_bool(obj, "zcmt", false, NULL);
-+
-+    if (env->misa_mxl != MXL_RV32) {
-+        object_property_set_bool(obj, "zcf", false, NULL);
-+    }
-+}
-+
- static Property riscv_cpu_properties[] = {
-     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
-         .abstract = true,
-     },
-     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
-+    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
- #if defined(CONFIG_KVM)
-     DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
- #endif
---
-.41.0

-[PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Add smoke tests to ensure that we'll not break the 'max' CPU type when
-adding new frozen/ratified RISC-V extensions.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-ID: <20230912132423.268494-12-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- tests/avocado/tuxrun_baselines.py | 32 +++++++++++++++++++++++++++++++
-file changed, 32 insertions(+)
-diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
-index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/tuxrun_baselines.py
-+++ b/tests/avocado/tuxrun_baselines.py
-@@ -XXX,XX +XXX,XX @@ def test_riscv64(self):
-         self.common_tuxrun(csums=sums)
-+    def test_riscv32_maxcpu(self):
-+        """
-+        :avocado: tags=arch:riscv32
-+        :avocado: tags=machine:virt
-+        :avocado: tags=cpu:max
-+        :avocado: tags=tuxboot:riscv32
-+        """
-+        sums = { "Image" :
-+                 "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
-+                 "fw_jump.elf" :
-+                 "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
-+                 "rootfs.ext4.zst" :
-+                 "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
-+
-+        self.common_tuxrun(csums=sums)
-+
-+    def test_riscv64_maxcpu(self):
-+        """
-+        :avocado: tags=arch:riscv64
-+        :avocado: tags=machine:virt
-+        :avocado: tags=cpu:max
-+        :avocado: tags=tuxboot:riscv64
-+        """
-+        sums = { "Image" :
-+                 "cd634badc65e52fb63465ec99e309c0de0369f0841b7d9486f9729e119bac25e",
-+                 "fw_jump.elf" :
-+                 "6e3373abcab4305fe151b564a4c71110d833c21f2c0a1753b7935459e36aedcf",
-+                 "rootfs.ext4.zst" :
-+                 "b18e3a3bdf27be03da0b285e84cb71bf09eca071c3a087b42884b6982ed679eb" }
-+
-+        self.common_tuxrun(csums=sums)
-+
-     def test_s390(self):
-         """
-         :avocado: tags=arch:s390x
---
-.41.0

-[PULL 12/54] target/riscv: deprecate the 'any' CPU type
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
-Core Definition"), being around since the beginning. It's not an easy
-CPU to use: it's undocumented and its name doesn't tell users much about
-what the CPU is supposed to bring. 'git log' doesn't help us either in
-knowing what was the original design of this CPU type.
-The closest we have is a comment from Alistair [1] where he recalls from
-memory that the 'any' CPU is supposed to behave like the newly added
-'max' CPU. He also suggested that the 'any' CPU should be removed.
-The default CPUs are rv32 and rv64, so removing the 'any' CPU will have
-impact only on users that might have a script that uses '-cpu any'.
-And those users are better off using the default CPUs or the new 'max'
-CPU.
-We would love to just remove the code and be done with it, but one does
-not simply remove a feature in QEMU. We'll put the CPU in quarantine
-first, letting users know that we have the intent of removing it in the
-future.
-[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-ID: <20230912132423.268494-13-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- docs/about/deprecated.rst | 12 ++++++++++++
- target/riscv/cpu.c        |  5 +++++
-files changed, 17 insertions(+)
-diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/about/deprecated.rst
-+++ b/docs/about/deprecated.rst
-@@ -XXX,XX +XXX,XX @@ QEMU's ``vhost`` feature, which would eliminate the high latency costs under
- which the 9p ``proxy`` backend currently suffers. However as of to date nobody
- has indicated plans for such kind of reimplementation unfortunately.
-+RISC-V 'any' CPU type ``-cpu any`` (since 8.2)
-+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-+
-+The 'any' CPU type was introduced back in 2018 and has been around since the
-+initial RISC-V QEMU port. Its usage has always been unclear: users don't know
-+what to expect from a CPU called 'any', and in fact the CPU does not do anything
-+special that isn't already done by the default CPUs rv32/rv64.
-+
-+After the introduction of the 'max' CPU type, RISC-V now has a good coverage
-+of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
-+CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
-+CPU type starting in 8.2.
- Block device options
- ''''''''''''''''''''
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-     Error *local_err = NULL;
-+    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
-+        warn_report("The 'any' CPU is deprecated and will be "
-+                    "removed in the future.");
-+    }
-+
-     cpu_exec_realizefn(cs, &local_err);
-     if (local_err != NULL) {
-         error_propagate(errp, local_err);
---
-.41.0

-[PULL 13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We'll have future usage for a function where, given an offset of the
-struct RISCVCPUConfig, the flag is updated to a certain val.
-Change all existing callers to use edata->ext_enable_offset instead of
-'edata'.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-14-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 18 +++++++++---------
-file changed, 9 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
- };
--static bool isa_ext_is_enabled(RISCVCPU *cpu,
--                               const struct isa_ext_data *edata)
-+static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
- {
--    bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
-+    bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
-     return *ext_enabled;
- }
--static void isa_ext_update_enabled(RISCVCPU *cpu,
--                                   const struct isa_ext_data *edata, bool en)
-+static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
-+                                   bool en)
- {
--    bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
-+    bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
-     *ext_enabled = en;
- }
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
-     /* Force disable extensions if priv spec version does not match */
-     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
--        if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
-+        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
-             (env->priv_ver < isa_edata_arr[i].min_version)) {
--            isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
-+            isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
-+                                   false);
- #ifndef CONFIG_USER_ONLY
-             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
-                         " because privilege spec version does not match",
-@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
-     int i;
-     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
--        if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
-+        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
-             new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
-             g_free(old);
-             old = new;
---
-.41.0

-[PULL 14/54] target/riscv: make CPUCFG() macro public
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
-of a certain field in the struct RISCVCPUConfig. We're going to use this
-macro in target/riscv/cpu.c as well in the next patches. Make it public.
-Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-ID: <20230912132423.268494-15-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h | 2 ++
- target/riscv/cpu.c | 2 +-
- target/riscv/kvm.c | 8 +++-----
-files changed, 6 insertions(+), 6 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
- const char *riscv_get_misa_ext_name(uint32_t bit);
- const char *riscv_get_misa_ext_description(uint32_t bit);
-+#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
-+
- /* Privileged specification version */
- enum {
-     PRIV_VERSION_1_10_0 = 0,
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
- };
- #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
--    {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
-+    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
- /*
-  * From vector_helper.c
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
-     }
- }
--#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
--
- #define KVM_EXT_CFG(_name, _prop, _reg_id) \
--    {.name = _name, .offset = CPUCFG(_prop), \
-+    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
-      .kvm_reg_id = _reg_id}
- static KVMCPUConfig kvm_multi_ext_cfgs[] = {
-@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v,
- static KVMCPUConfig kvm_cbom_blocksize = {
-     .name = "cbom_blocksize",
--    .offset = CPUCFG(cbom_blocksize),
-+    .offset = CPU_CFG_OFFSET(cbom_blocksize),
-     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)
- };
- static KVMCPUConfig kvm_cboz_blocksize = {
-     .name = "cboz_blocksize",
--    .offset = CPUCFG(cboz_blocksize),
-+    .offset = CPU_CFG_OFFSET(cboz_blocksize),
-     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
- };
---
-.41.0

-[PULL 15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-During realize() time we're activating a lot of extensions based on some
-criteria, e.g.:
-    if (cpu->cfg.ext_zk) {
-        cpu->cfg.ext_zkn = true;
-        cpu->cfg.ext_zkr = true;
-        cpu->cfg.ext_zkt = true;
-    }
-This practice resulted in at least one case where we ended up enabling
-something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that
-has priv_spec older than 1.12.0.
-We're also not considering user choice. There's no way of doing it now
-but this is about to change in the next few patches.
-cpu_cfg_ext_auto_update() will check for priv version mismatches before
-enabling extensions. If we have a mismatch between the current priv
-version and the extension we want to enable, do not enable it. In the
-near future, this same function will also consider user choice when
-deciding if we're going to enable/disable an extension or not.
-For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-16-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++++++++++---
-file changed, 40 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
-     *ext_enabled = en;
- }
-+static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
-+{
-+    int i;
-+
-+    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-+        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
-+            continue;
-+        }
-+
-+        return isa_edata_arr[i].min_version;
-+    }
-+
-+    g_assert_not_reached();
-+}
-+
-+static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
-+                                    bool value)
-+{
-+    CPURISCVState *env = &cpu->env;
-+    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
-+    int min_version;
-+
-+    if (prev_val == value) {
-+        return;
-+    }
-+
-+    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
-+        /* Do not enable it if priv_ver is older than min_version */
-+        min_version = cpu_cfg_ext_get_min_version(ext_offset);
-+        if (env->priv_ver < min_version) {
-+            return;
-+        }
-+    }
-+
-+    isa_ext_update_enabled(cpu, ext_offset, value);
-+}
-+
- const char * const riscv_int_regnames[] = {
-     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
-     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
-     if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
--        cpu->cfg.ext_zca = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
--            cpu->cfg.ext_zcf = true;
-+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
-         }
-         if (riscv_has_ext(env, RVD)) {
--            cpu->cfg.ext_zcd = true;
-+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
-         }
-     }
---
-.41.0

-[PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Before adding support to detect if an extension was user set we need to
-handle how we're enabling extensions in riscv_init_max_cpu_extensions().
-object_property_set_bool() calls the set() callback for the property,
-and we're going to use this callback to set the 'multi_ext_user_opts'
-hash.
-This means that, as is today, all extensions we're setting for the 'max'
-CPU will be seen as user set in the future. Let's change set_bool() to
-isa_ext_update_enabled() that will just enable/disable the flag on a
-certain offset.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-19-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 18 +++++++++---------
-file changed, 9 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
-     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
--        object_property_set_bool(obj, prop->name, true, NULL);
-+        isa_ext_update_enabled(cpu, prop->offset, true);
-     }
-     /* set vector version */
-     env->vext_ver = VEXT_VERSION_1_00_0;
-     /* Zfinx is not compatible with F. Disable it */
--    object_property_set_bool(obj, "zfinx", false, NULL);
--    object_property_set_bool(obj, "zdinx", false, NULL);
--    object_property_set_bool(obj, "zhinx", false, NULL);
--    object_property_set_bool(obj, "zhinxmin", false, NULL);
-+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
-+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
-+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
-+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
--    object_property_set_bool(obj, "zce", false, NULL);
--    object_property_set_bool(obj, "zcmp", false, NULL);
--    object_property_set_bool(obj, "zcmt", false, NULL);
-+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
-+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
-+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
-     if (env->misa_mxl != MXL_RV32) {
--        object_property_set_bool(obj, "zcf", false, NULL);
-+        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
-     }
- }
---
-.41.0

-[PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
-set by the user in the command line. Use it inside
-cpu_cfg_ext_auto_update() to verify if the user set a certain extension
-and, if that's the case, do not change its value.
-This will make us honor user choice instead of overwriting the values.
-Users will then be informed whether they're using an incompatible set of
-extensions instead of QEMU setting a magic value that works.
-The reason why we're not implementing user choice for MISA extensions
-right now is because, today, we do not silently change any MISA bit
-during realize() time (we do warn when enabling bits if RVG is enabled).
-We do that - a lot - with multi-letter extensions though, so we're
-handling the most immediate concern first.
-After this patch, we'll now error out if the user explicitly set 'zce' to true
-and 'zca' to false:
-$ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=true,zca=false -nographic
-qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension
-This didn't happen before because we were enabling 'zca' if 'zce' was enabled
-regardless if the user set 'zca' to false.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-20-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 16 ++++++++++++++++
-file changed, 16 insertions(+)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
-     g_assert_not_reached();
- }
-+static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
-+{
-+    return g_hash_table_contains(multi_ext_user_opts,
-+                                 GUINT_TO_POINTER(ext_offset));
-+}
-+
- static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
-                                     bool value)
- {
-@@ -XXX,XX +XXX,XX @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
-         return;
-     }
-+    if (cpu_cfg_ext_is_user_set(ext_offset)) {
-+        return;
-+    }
-+
-     if (value && env->priv_ver != PRIV_VERSION_LATEST) {
-         /* Do not enable it if priv_ver is older than min_version */
-         min_version = cpu_cfg_ext_get_min_version(ext_offset);
-@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
-     MISA_CFG(RVG, false),
- };
-+/*
-+ * We do not support user choice tracking for MISA
-+ * extensions yet because, so far, we do not silently
-+ * change MISA bits during realize() (RVG enables MISA
-+ * bits but the user is warned about it).
-+ */
- static void riscv_cpu_add_misa_properties(Object *cpu_obj)
- {
-     int i;
---
-.41.0

-[PULL 20/54] target/riscv/cpu.c: consider user option with RVG
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Enabling RVG will enable a set of extensions that we're not checking if
-the user was okay enabling or not. And in this case we want to error
-out, instead of ignoring, otherwise we will be inconsistent enabling RVG
-without all its extensions.
-After this patch, disabling ifencei or icsr while enabling RVG will
-result in error:
-$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false --nographic
-qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-ID: <20230912132423.268494-21-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 18 ++++++++++++++++--
-file changed, 16 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
-           riscv_has_ext(env, RVD) &&
-           cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
-+
-+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
-+            !cpu->cfg.ext_icsr) {
-+            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
-+            return;
-+        }
-+
-+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
-+            !cpu->cfg.ext_ifencei) {
-+            error_setg(errp, "RVG requires Zifencei but user set "
-+                       "Zifencei to false");
-+            return;
-+        }
-+
-         warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
--        cpu->cfg.ext_icsr = true;
--        cpu->cfg.ext_ifencei = true;
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
-         env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
-         env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
---
-.41.0

-[PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host
+Deleted patch
-From: "liguang.zhang" <liguang.zhang@hexintek.com>
-This patch fixes guest reboot errors when using KVM.
-There are two issues when rebooting a guest using KVM
-. When the guest initiates a reboot the host is unable to stop the vcpu
-. When running a SMP guest the qemu monitor system_reset causes a vcpu crash
-This can be fixed by clearing the CSR values at reset and syncing the
-MPSTATE with the host.
-Signed-off-by: liguang.zhang <liguang.zhang@hexintek.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230913091332.17355-1-18622748025@163.com>
-[ Changes by AF
- - Fixup commit message
- - Fixup patch style
-]
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/kvm_riscv.h |  1 +
- target/riscv/kvm.c       | 44 ++++++++++++++++++++++++++++++++++++++++
-files changed, 45 insertions(+)
-diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm_riscv.h
-+++ b/target/riscv/kvm_riscv.h
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-                           uint64_t aplic_base, uint64_t imsic_base,
-                           uint64_t guest_num);
- void riscv_kvm_aplic_request(void *opaque, int irq, int level);
-+int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state);
- #endif
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ void riscv_kvm_aplic_request(void *opaque, int irq, int level)
-     kvm_set_irq(kvm_state, irq, !!level);
- }
-+static bool cap_has_mp_state;
-+
- static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-                                  uint64_t idx)
- {
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
-     return ret;
- }
-+int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state)
-+{
-+    if (cap_has_mp_state) {
-+        struct kvm_mp_state mp_state = {
-+            .mp_state = state
-+        };
-+
-+        int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
-+        if (ret) {
-+            fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n",
-+                    __func__, ret, strerror(-ret));
-+            return -1;
-+        }
-+    }
-+
-+    return 0;
-+}
-+
- int kvm_arch_put_registers(CPUState *cs, int level)
- {
-     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
-         return ret;
-     }
-+    if (KVM_PUT_RESET_STATE == level) {
-+        RISCVCPU *cpu = RISCV_CPU(cs);
-+        if (cs->cpu_index == 0) {
-+            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE);
-+        } else {
-+            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED);
-+        }
-+        if (ret) {
-+            return ret;
-+        }
-+    }
-+
-     return ret;
- }
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_default_type(MachineState *ms)
- int kvm_arch_init(MachineState *ms, KVMState *s)
- {
-+    cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
-     return 0;
- }
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
- void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
- {
-     CPURISCVState *env = &cpu->env;
-+    int i;
-     if (!kvm_enabled()) {
-         return;
-     }
-+    for (i = 0; i < 32; i++) {
-+        env->gpr[i] = 0;
-+    }
-     env->pc = cpu->env.kernel_addr;
-     env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
-     env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
-     env->satp = 0;
-+    env->mie = 0;
-+    env->stvec = 0;
-+    env->sscratch = 0;
-+    env->sepc = 0;
-+    env->scause = 0;
-+    env->stval = 0;
-+    env->mip = 0;
- }
- void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
---
-.41.0

-[PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: Alvin Chang <vivahavey@gmail.com>
+From: Alistair Francis <alistair23@gmail.com>
-Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name().
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
 CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
 CSRs are part of the disassembly.
-Signed-off-by: Alvin Chang <alvinga@andestech.com>
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230907084500.328-1-alvinga@andestech.com>
+Fixes: ea10325917 ("RISC-V Disassembler")
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- disas/riscv.c | 4 ++--
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 64 insertions(+), 1 deletion(-)
 diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
 --- a/disas/riscv.c
 +++ b/disas/riscv.c
 @@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-     case 0x03ba: return "pmpaddr10";
+     case 0x0383: return "mibound";
-     case 0x03bb: return "pmpaddr11";
+     case 0x0384: return "mdbase";
-     case 0x03bc: return "pmpaddr12";
+     case 0x0385: return "mdbound";
--    case 0x03bd: return "pmpaddr14";
+-    case 0x03a0: return "pmpcfg3";
--    case 0x03be: return "pmpaddr13";
++    case 0x03a0: return "pmpcfg0";
-+    case 0x03bd: return "pmpaddr13";
++    case 0x03a1: return "pmpcfg1";
-+    case 0x03be: return "pmpaddr14";
++    case 0x03a2: return "pmpcfg2";
 +    case 0x03a3: return "pmpcfg3";
 +    case 0x03a4: return "pmpcfg4";
 +    case 0x03a5: return "pmpcfg5";
 +    case 0x03a6: return "pmpcfg6";
 +    case 0x03a7: return "pmpcfg7";
 +    case 0x03a8: return "pmpcfg8";
 +    case 0x03a9: return "pmpcfg9";
 +    case 0x03aa: return "pmpcfg10";
 +    case 0x03ab: return "pmpcfg11";
 +    case 0x03ac: return "pmpcfg12";
 +    case 0x03ad: return "pmpcfg13";
 +    case 0x03ae: return "pmpcfg14";
 +    case 0x03af: return "pmpcfg15";
      case 0x03b0: return "pmpaddr0";
      case 0x03b1: return "pmpaddr1";
      case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
      case 0x03bd: return "pmpaddr13";
      case 0x03be: return "pmpaddr14";
      case 0x03bf: return "pmpaddr15";
++    case 0x03c0: return "pmpaddr16";
++    case 0x03c1: return "pmpaddr17";
++    case 0x03c2: return "pmpaddr18";
++    case 0x03c3: return "pmpaddr19";
++    case 0x03c4: return "pmpaddr20";
++    case 0x03c5: return "pmpaddr21";
++    case 0x03c6: return "pmpaddr22";
++    case 0x03c7: return "pmpaddr23";
++    case 0x03c8: return "pmpaddr24";
++    case 0x03c9: return "pmpaddr25";
++    case 0x03ca: return "pmpaddr26";
++    case 0x03cb: return "pmpaddr27";
++    case 0x03cc: return "pmpaddr28";
++    case 0x03cd: return "pmpaddr29";
++    case 0x03ce: return "pmpaddr30";
++    case 0x03cf: return "pmpaddr31";
++    case 0x03d0: return "pmpaddr32";
++    case 0x03d1: return "pmpaddr33";
++    case 0x03d2: return "pmpaddr34";
++    case 0x03d3: return "pmpaddr35";
++    case 0x03d4: return "pmpaddr36";
++    case 0x03d5: return "pmpaddr37";
++    case 0x03d6: return "pmpaddr38";
++    case 0x03d7: return "pmpaddr39";
++    case 0x03d8: return "pmpaddr40";
++    case 0x03d9: return "pmpaddr41";
++    case 0x03da: return "pmpaddr42";
++    case 0x03db: return "pmpaddr43";
++    case 0x03dc: return "pmpaddr44";
++    case 0x03dd: return "pmpaddr45";
++    case 0x03de: return "pmpaddr46";
++    case 0x03df: return "pmpaddr47";
++    case 0x03e0: return "pmpaddr48";
++    case 0x03e1: return "pmpaddr49";
++    case 0x03e2: return "pmpaddr50";
++    case 0x03e3: return "pmpaddr51";
++    case 0x03e4: return "pmpaddr52";
++    case 0x03e5: return "pmpaddr53";
++    case 0x03e6: return "pmpaddr54";
++    case 0x03e7: return "pmpaddr55";
++    case 0x03e8: return "pmpaddr56";
++    case 0x03e9: return "pmpaddr57";
++    case 0x03ea: return "pmpaddr58";
++    case 0x03eb: return "pmpaddr59";
++    case 0x03ec: return "pmpaddr60";
++    case 0x03ed: return "pmpaddr61";
++    case 0x03ee: return "pmpaddr62";
++    case 0x03ef: return "pmpaddr63";
      case 0x0780: return "mtohost";
      case 0x0781: return "mfromhost";
+     case 0x0782: return "mreset";
 --
-.41.0
+.45.1

-[PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Yu-Ming Chang <yumin686@andestech.com>
-This function is the core of the RISC-V validations for TCG CPUs, and it
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
-has a lot going on.
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
 holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-Functions in cpu.c were made public to allow them to be used by the KVM
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
-accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
+a register holding a zero value, an illegal instruction exception should be
-hard to move it to another file due to its dependency with isa_edata_arr[]
+raised.
 array, thus make it public and use it as is for now.
-riscv_cpu_validate_set_extensions() is kept public because it's used by
+Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 csr.c in write_misa().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-4-dbarboza@ventanamicro.com>
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |   8 +-
+ target/riscv/cpu.h       |  4 ++++
- target/riscv/tcg/tcg-cpu.h |  27 +++
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
- target/riscv/cpu.c         | 361 +------------------------------------
+ target/riscv/op_helper.c |  6 ++---
- target/riscv/csr.c         |   1 +
+files changed, 53 insertions(+), 8 deletions(-)
  target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++
 files changed, 397 insertions(+), 357 deletions(-)
  create mode 100644 target/riscv/tcg/tcg-cpu.h
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-                         bool probe, uintptr_t retaddr);
+ void riscv_cpu_update_mask(CPURISCVState *env);
- char *riscv_isa_string(RISCVCPU *cpu);
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
- void riscv_cpu_list(void);
--void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
++                          target_ulong *ret_value);
- #define cpu_list riscv_cpu_list
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
- #define cpu_mmu_index riscv_cpu_mmu_index
+                            target_ulong *ret_value,
-@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
+                            target_ulong new_value, target_ulong write_mask);
- #include "hw/core/tcg-cpu-ops.h"
+@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
- extern const struct TCGCPUOps riscv_tcg_ops;
+                                           target_ulong new_value,
+                                           target_ulong write_mask);
-+/* used by tcg/tcg-cpu.c*/
-+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
++RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
-+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
++                               Int128 *ret_value);
-+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-+int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+                                 Int128 *ret_value,
-+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
+                                 Int128 new_value, Int128 write_mask);
 +
  /* CSR function table */
  extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * riscv TCG cpu class initialization
 + *
 + * Copyright (c) 2023 Ventana Micro Systems Inc.
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef RISCV_TCG_CPU_H
 +#define RISCV_TCG_CPU_H
 +
 +#include "cpu.h"
 +
 +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 +
 +#endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
  /* Hash that stores user set extensions */
  static GHashTable *multi_ext_user_opts;
 -static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
  {
      bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
      return *ext_enabled;
  }
 -static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
 -                                   bool en)
 +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
  {
      bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
      *ext_enabled = en;
  }
 -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 +int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
  {
      int i;
@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
      g_assert_not_reached();
  }
 -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
 +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
  {
      return g_hash_table_contains(multi_ext_user_opts,
                                   GUINT_TO_POINTER(ext_offset));
  }
 -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
 -                                    bool value)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
 -    int min_version;
 -
 -    if (prev_val == value) {
 -        return;
 -    }
 -
 -    if (cpu_cfg_ext_is_user_set(ext_offset)) {
 -        return;
 -    }
 -
 -    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
 -        /* Do not enable it if priv_ver is older than min_version */
 -        min_version = cpu_cfg_ext_get_min_version(ext_offset);
 -        if (env->priv_ver < min_version) {
 -            return;
 -        }
 -    }
 -
 -    isa_ext_update_enabled(cpu, ext_offset, value);
 -}
 -
  const char * const riscv_int_regnames[] = {
      "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
      "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
      }
  }
 -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
 -                                 Error **errp)
 -{
 -    if (!is_power_of_2(cfg->vlen)) {
 -        error_setg(errp, "Vector extension VLEN must be power of 2");
 -        return;
 -    }
 -    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
 -        error_setg(errp,
 -                   "Vector extension implementation only supports VLEN "
 -                   "in the range [128, %d]", RV_VLEN_MAX);
 -        return;
 -    }
 -    if (!is_power_of_2(cfg->elen)) {
 -        error_setg(errp, "Vector extension ELEN must be power of 2");
 -        return;
 -    }
 -    if (cfg->elen > 64 || cfg->elen < 8) {
 -        error_setg(errp,
 -                   "Vector extension implementation only supports ELEN "
 -                   "in the range [8, 64]");
 -        return;
 -    }
 -    if (cfg->vext_spec) {
 -        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
 -            env->vext_ver = VEXT_VERSION_1_00_0;
 -        } else {
 -            error_setg(errp, "Unsupported vector spec version '%s'",
 -                       cfg->vext_spec);
 -            return;
 -        }
 -    } else if (env->vext_ver == 0) {
 -        qemu_log("vector version is not specified, "
 -                 "use the default value v1.0\n");
 -
 -        env->vext_ver = VEXT_VERSION_1_00_0;
 -    }
 -}
 -
 -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
  {
      CPURISCVState *env = &cpu->env;
      int i;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
      }
  }
 -/*
 - * Check consistency between chosen extensions while setting
 - * cpu->cfg accordingly.
 - */
 -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    Error *local_err = NULL;
 -
 -    /* Do some ISA extension error checking */
 -    if (riscv_has_ext(env, RVG) &&
 -        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
 -          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
 -          riscv_has_ext(env, RVD) &&
 -          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
 -
 -        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
 -            !cpu->cfg.ext_icsr) {
 -            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
 -            return;
 -        }
 -
 -        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
 -            !cpu->cfg.ext_ifencei) {
 -            error_setg(errp, "RVG requires Zifencei but user set "
 -                       "Zifencei to false");
 -            return;
 -        }
 -
 -        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
 -
 -        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
 -        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
 -    }
 -
 -    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
 -        error_setg(errp,
 -                   "I and E extensions are incompatible");
 -        return;
 -    }
 -
 -    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
 -        error_setg(errp,
 -                   "Either I or E extension must be set");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
 -        error_setg(errp,
 -                   "Setting S extension without U extension is illegal");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
 -        error_setg(errp,
 -                   "H depends on an I base integer ISA with 32 x registers");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
 -        error_setg(errp, "H extension implicitly requires S-mode");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
 -        error_setg(errp, "F extension requires Zicsr");
 -        return;
 -    }
 -
 -    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
 -        error_setg(errp, "Zawrs extension requires A extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zfa extension requires F extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfh) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
 -    }
 -
 -    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zfbfmin extension depends on F extension");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "D extension requires F extension");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVV)) {
 -        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
 -        if (local_err != NULL) {
 -            error_propagate(errp, local_err);
 -            return;
 -        }
 -
 -        /* The V vector extension depends on the Zve64d extension */
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
 -    }
 -
 -    /* The Zve64d extension depends on the Zve64f extension */
 -    if (cpu->cfg.ext_zve64d) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
 -    }
 -
 -    /* The Zve64f extension depends on the Zve32f extension */
 -    if (cpu->cfg.ext_zve64f) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 -    }
 -
 -    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 -        error_setg(errp, "Zve64d/V extensions require D extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfh) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
 -    }
 -
 -    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
 -        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
 -        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
 -        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
 -        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
 -        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
 -        return;
 -    }
 -
 -    /* Set the ISA extensions, checks should have happened above */
 -    if (cpu->cfg.ext_zhinx) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 -    }
 -
 -    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
 -        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfinx) {
 -        if (!cpu->cfg.ext_icsr) {
 -            error_setg(errp, "Zfinx extension requires Zicsr");
 -            return;
 -        }
 -        if (riscv_has_ext(env, RVF)) {
 -            error_setg(errp,
 -                       "Zfinx cannot be supported together with F extension");
 -            return;
 -        }
 -    }
 -
 -    if (cpu->cfg.ext_zce) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
 -        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 -            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 -        }
 -    }
 -
 -    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
 -    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 -        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 -            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 -        }
 -        if (riscv_has_ext(env, RVD)) {
 -            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
 -        }
 -    }
 -
 -    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
 -        error_setg(errp, "Zcf extension is only relevant to RV32");
 -        return;
 -    }
 -
 -    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
 -        error_setg(errp, "Zcf extension requires F extension");
 -        return;
 -    }
 -
 -    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
 -        error_setg(errp, "Zcd extension requires D extension");
 -        return;
 -    }
 -
 -    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
 -         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
 -        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
 -                         "extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
 -        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
 -                         "Zcd extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
 -        error_setg(errp, "Zcmt extension requires Zicsr extension");
 -        return;
 -    }
 -
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
 -    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
 -         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
 -        !cpu->cfg.ext_zve32f) {
 -        error_setg(errp,
 -                   "Vector crypto extensions require V or Zve* extensions");
 -        return;
 -    }
 -
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 -        error_setg(
 -            errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zk) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
 -    }
 -
 -    if (cpu->cfg.ext_zkn) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
 -    }
 -
 -    if (cpu->cfg.ext_zks) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
 -    }
 -
 -    /*
 -     * Disable isa extensions based on priv spec after we
 -     * validated and set everything we need.
 -     */
 -    riscv_cpu_disable_priv_spec_isa_exts(cpu);
 -}
 -
  #ifndef CONFIG_USER_ONLY
  static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
  {
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- #include "qemu/log.h"
- #include "qemu/timer.h"
+ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
- #include "cpu.h"
+                                                int csrno,
-+#include "tcg/tcg-cpu.h"
+-                                               bool write_mask)
- #include "pmu.h"
++                                               bool write)
- #include "time_helper.h"
+ {
- #include "exec/exec-all.h"
+     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
-diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+     bool read_only = get_field(csrno, 0xC00) == 3;
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
---- a/target/riscv/tcg/tcg-cpu.c
+     }
-+++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@
+     /* read / write check */
+-    if (write_mask && read_only) {
- #include "qemu/osdep.h"
++    if (write && read_only) {
- #include "exec/exec-all.h"
+         return RISCV_EXCP_ILLEGAL_INST;
-+#include "tcg-cpu.h"
+     }
- #include "cpu.h"
- #include "pmu.h"
+@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
- #include "time_helper.h"
+     return RISCV_EXCP_NONE;
- #include "qapi/error.h"
+ }
- #include "qemu/accel.h"
-+#include "qemu/error-report.h"
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-+#include "qemu/log.h"
++                           target_ulong *ret_value)
  #include "hw/core/accel-cpu.h"
 +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
 +                                    bool value)
 +{
-+    CPURISCVState *env = &cpu->env;
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
-+    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
++    if (ret != RISCV_EXCP_NONE) {
-+    int min_version;
++        return ret;
 +
 +    if (prev_val == value) {
 +        return;
 +    }
 +
-+    if (cpu_cfg_ext_is_user_set(ext_offset)) {
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
-+        return;
++}
 +
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value)
 +{
 +    RISCVException ret;
 +
 +    ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
++    if (csr_ops[csrno].read128) {
-+        /* Do not enable it if priv_ver is older than min_version */
++        return riscv_csrrw_do128(env, csrno, ret_value,
-+        min_version = cpu_cfg_ext_get_min_version(ext_offset);
++                                 int128_zero(), int128_zero());
 +        if (env->priv_ver < min_version) {
 +            return;
 +        }
 +    }
 +
 +    isa_ext_update_enabled(cpu, ext_offset, value);
 +}
 +
  static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
  {
      if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
      }
  }
 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
 +                                 Error **errp)
 +{
 +    if (!is_power_of_2(cfg->vlen)) {
 +        error_setg(errp, "Vector extension VLEN must be power of 2");
 +        return;
 +    }
 +
 +    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
 +        error_setg(errp,
 +                   "Vector extension implementation only supports VLEN "
 +                   "in the range [128, %d]", RV_VLEN_MAX);
 +        return;
 +    }
 +
 +    if (!is_power_of_2(cfg->elen)) {
 +        error_setg(errp, "Vector extension ELEN must be power of 2");
 +        return;
 +    }
 +
 +    if (cfg->elen > 64 || cfg->elen < 8) {
 +        error_setg(errp,
 +                   "Vector extension implementation only supports ELEN "
 +                   "in the range [8, 64]");
 +        return;
 +    }
 +
 +    if (cfg->vext_spec) {
 +        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
 +            env->vext_ver = VEXT_VERSION_1_00_0;
 +        } else {
 +            error_setg(errp, "Unsupported vector spec version '%s'",
 +                       cfg->vext_spec);
 +            return;
 +        }
 +    } else if (env->vext_ver == 0) {
 +        qemu_log("vector version is not specified, "
 +                 "use the default value v1.0\n");
 +
 +        env->vext_ver = VEXT_VERSION_1_00_0;
 +    }
 +}
 +
 +/*
 + * Check consistency between chosen extensions while setting
 + * cpu->cfg accordingly.
 + */
 +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 +{
 +    CPURISCVState *env = &cpu->env;
 +    Error *local_err = NULL;
 +
 +    /* Do some ISA extension error checking */
 +    if (riscv_has_ext(env, RVG) &&
 +        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
 +          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
 +          riscv_has_ext(env, RVD) &&
 +          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
 +
 +        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
 +            !cpu->cfg.ext_icsr) {
 +            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
 +            return;
 +        }
 +
 +        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
 +            !cpu->cfg.ext_ifencei) {
 +            error_setg(errp, "RVG requires Zifencei but user set "
 +                       "Zifencei to false");
 +            return;
 +        }
 +
 +        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
 +
 +        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
 +        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
 +    }
 +
 +    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
 +        error_setg(errp,
 +                   "I and E extensions are incompatible");
 +        return;
 +    }
 +
 +    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
 +        error_setg(errp,
 +                   "Either I or E extension must be set");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
 +        error_setg(errp,
 +                   "Setting S extension without U extension is illegal");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
 +        error_setg(errp,
 +                   "H depends on an I base integer ISA with 32 x registers");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
 +        error_setg(errp, "H extension implicitly requires S-mode");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
 +        error_setg(errp, "F extension requires Zicsr");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
 +        error_setg(errp, "Zawrs extension requires A extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zfa extension requires F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfh) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
 +    }
 +
 +    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zfbfmin extension depends on F extension");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "D extension requires F extension");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVV)) {
 +        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
 +        if (local_err != NULL) {
 +            error_propagate(errp, local_err);
 +            return;
 +        }
 +
 +        /* The V vector extension depends on the Zve64d extension */
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
 +    }
 +
 +    /* The Zve64d extension depends on the Zve64f extension */
 +    if (cpu->cfg.ext_zve64d) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
 +    }
 +
 +    /* The Zve64f extension depends on the Zve32f extension */
 +    if (cpu->cfg.ext_zve64f) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 +    }
 +
 +    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 +        error_setg(errp, "Zve64d/V extensions require D extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfh) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
 +    }
 +
 +    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
 +        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
 +        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
 +        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
 +        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
 +        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
 +        return;
 +    }
 +
 +    /* Set the ISA extensions, checks should have happened above */
 +    if (cpu->cfg.ext_zhinx) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 +    }
 +
 +    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
 +        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfinx) {
 +        if (!cpu->cfg.ext_icsr) {
 +            error_setg(errp, "Zfinx extension requires Zicsr");
 +            return;
 +        }
 +        if (riscv_has_ext(env, RVF)) {
 +            error_setg(errp,
 +                       "Zfinx cannot be supported together with F extension");
 +            return;
 +        }
 +    }
 +
 +    if (cpu->cfg.ext_zce) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
 +        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 +            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 +        }
 +    }
 +
 +    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
 +    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 +        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 +            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 +        }
 +        if (riscv_has_ext(env, RVD)) {
 +            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
 +        }
 +    }
 +
 +    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
 +        error_setg(errp, "Zcf extension is only relevant to RV32");
 +        return;
 +    }
 +
 +    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
 +        error_setg(errp, "Zcf extension requires F extension");
 +        return;
 +    }
 +
 +    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
 +        error_setg(errp, "Zcd extension requires D extension");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
 +         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
 +        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
 +                         "extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
 +        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
 +                         "Zcd extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
 +        error_setg(errp, "Zcmt extension requires Zicsr extension");
 +        return;
 +    }
 +
 +    /*
-+     * In principle Zve*x would also suffice here, were they supported
++     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
-+     * in qemu
++     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
-+    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
++    target_ulong old_value;
-+         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
++    ret = riscv_csrrw_do64(env, csrno, &old_value,
-+        !cpu->cfg.ext_zve32f) {
++                           (target_ulong)0,
-+        error_setg(errp,
++                           (target_ulong)0);
-+                   "Vector crypto extensions require V or Zve* extensions");
++    if (ret == RISCV_EXCP_NONE && ret_value) {
-+        return;
++        *ret_value = int128_make64(old_value);
 +    }
-+
++    return ret;
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +        error_setg(
 +            errp,
 +            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zk) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
 +    }
 +
 +    if (cpu->cfg.ext_zkn) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
 +    }
 +
 +    if (cpu->cfg.ext_zks) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
 +    }
 +
 +    /*
 +     * Disable isa extensions based on priv spec after we
 +     * validated and set everything we need.
 +     */
 +    riscv_cpu_disable_priv_spec_isa_exts(cpu);
 +}
 +
- /*
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-  * We'll get here via the following path:
+                                 Int128 *ret_value,
-  *
+                                 Int128 new_value, Int128 write_mask)
  {
      RISCVException ret;
 -    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
 +    ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
      }
      target_ulong val = 0;
 -    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
 +    RISCVException ret = riscv_csrr(env, csr, &val);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
      Int128 rv = int128_zero();
 -    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
 -                                          int128_zero(),
 -                                          int128_zero());
 +    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
 --
-.41.0
+.45.1

-[PULL 27/54] target/riscv/cpu.c: add .instance_post_init()
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
-calls riscv_init_max_cpu_extensions(). Both can be moved to a common
-instance_post_init() callback, implemented in riscv_cpu_post_init(),
-called by all CPUs. The call order then becomes:
-riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()
-In the near future riscv_cpu_post_init() will call the init() function
-of the current accelerator, providing a hook for KVM and TCG accel
-classes to change the init() process of the CPU.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-6-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
-file changed, 32 insertions(+), 11 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
-     mlx = MXL_RV32;
- #endif
-     set_misa(env, mlx, 0);
--    riscv_cpu_add_user_properties(obj);
--    riscv_init_max_cpu_extensions(obj);
-     env->priv_ver = PRIV_VERSION_LATEST;
- #ifndef CONFIG_USER_ONLY
-     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
-@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
-     CPURISCVState *env = &RISCV_CPU(obj)->env;
-     /* We set this in the realise function */
-     set_misa(env, MXL_RV64, 0);
--    riscv_cpu_add_user_properties(obj);
-     /* Set latest version of privileged specification */
-     env->priv_ver = PRIV_VERSION_LATEST;
- #ifndef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
-     CPURISCVState *env = &RISCV_CPU(obj)->env;
-     /* We set this in the realise function */
-     set_misa(env, MXL_RV128, 0);
--    riscv_cpu_add_user_properties(obj);
-     /* Set latest version of privileged specification */
-     env->priv_ver = PRIV_VERSION_LATEST;
- #ifndef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
-     CPURISCVState *env = &RISCV_CPU(obj)->env;
-     /* We set this in the realise function */
-     set_misa(env, MXL_RV32, 0);
--    riscv_cpu_add_user_properties(obj);
-     /* Set latest version of privileged specification */
-     env->priv_ver = PRIV_VERSION_LATEST;
- #ifndef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@ static void riscv_host_cpu_init(Object *obj)
- #elif defined(TARGET_RISCV64)
-     set_misa(env, MXL_RV64, 0);
- #endif
--    riscv_cpu_add_user_properties(obj);
- }
- #endif /* CONFIG_KVM */
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
- }
- #endif /* CONFIG_USER_ONLY */
-+static bool riscv_cpu_is_dynamic(Object *cpu_obj)
-+{
-+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-+}
-+
-+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
-+{
-+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
-+}
-+
-+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
-+{
-+    if (kvm_enabled() &&
-+        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
-+        return true;
-+    }
-+
-+    return riscv_cpu_is_dynamic(cpu_obj);
-+}
-+
-+static void riscv_cpu_post_init(Object *obj)
-+{
-+    if (riscv_cpu_has_user_properties(obj)) {
-+        riscv_cpu_add_user_properties(obj);
-+    }
-+
-+    if (riscv_cpu_has_max_extensions(obj)) {
-+        riscv_init_max_cpu_extensions(obj);
-+    }
-+}
-+
- static void riscv_cpu_init(Object *obj)
- {
- #ifndef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
- };
- #endif
--static bool riscv_cpu_is_dynamic(Object *cpu_obj)
--{
--    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
--}
--
- static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
-                               void *opaque, Error **errp)
- {
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
-         .instance_size = sizeof(RISCVCPU),
-         .instance_align = __alignof(RISCVCPU),
-         .instance_init = riscv_cpu_init,
-+        .instance_post_init = riscv_cpu_post_init,
-         .abstract = true,
-         .class_size = sizeof(RISCVCPUClass),
-         .class_init = riscv_cpu_class_init,
---
-.41.0

-[PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const'
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We'll need to export these arrays to the accelerator classes in the next
-patches. Mark them as 'const' now because they should not be modified at
-runtime.
-Note that 'riscv_cpu_options' will also be exported, but can't be marked
-as 'const', because the properties are changed via
-qdev_property_add_static().
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-8-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 22 +++++++++++++---------
-file changed, 13 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
-     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
-      .enabled = _defval}
--static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-+static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-     /* Defaults for standard extensions */
-     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
-     MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
-@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-     DEFINE_PROP_END_OF_LIST(),
- };
--static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
-+static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
-     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
-     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
-     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
-@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
- };
- /* These are experimental so mark with 'x-' */
--static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
-+static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
-     /* ePMP 0.9.3 */
-     MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
-     MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
-@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
- }
- static void cpu_add_multi_ext_prop(Object *cpu_obj,
--                                   RISCVCPUMultiExtConfig *multi_cfg)
-+                                   const RISCVCPUMultiExtConfig *multi_cfg)
- {
-     object_property_add(cpu_obj, multi_cfg->name, "bool",
-                         cpu_get_multi_ext_cfg,
-@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
- }
- static void riscv_cpu_add_multiext_prop_array(Object *obj,
--                                              RISCVCPUMultiExtConfig *array)
-+                                        const RISCVCPUMultiExtConfig *array)
- {
-+    const RISCVCPUMultiExtConfig *prop;
-+
-     g_assert(array);
--    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
-+    for (prop = array; prop && prop->name; prop++) {
-         cpu_add_multi_ext_prop(obj, prop);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
- }
- static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
--                                                 RISCVCPUMultiExtConfig *array)
-+                                        const RISCVCPUMultiExtConfig *array)
- {
-+    const RISCVCPUMultiExtConfig *prop;
-+
-     g_assert(array);
--    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
-+    for (prop = array; prop && prop->name; prop++) {
-         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
- {
-     RISCVCPU *cpu = RISCV_CPU(obj);
-     CPURISCVState *env = &cpu->env;
--    RISCVCPUMultiExtConfig *prop;
-+    const RISCVCPUMultiExtConfig *prop;
-     /* Enable RVG, RVJ and RVV that are disabled by default */
-     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
---
-.41.0

-[PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This function is used for both accelerators. Make it public, and call it
-from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
-split KVM specific code for the KVM accelerator class in the next patch.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-10-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h | 1 +
- target/riscv/cpu.c | 5 ++---
- target/riscv/kvm.c | 1 +
-files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
- extern Property riscv_cpu_options[];
- void riscv_cpu_add_misa_properties(Object *cpu_obj);
-+void riscv_add_satp_mode_properties(Object *obj);
- /* CSR function table */
- extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
-     satp_map->init |= 1 << satp;
- }
--static void riscv_add_satp_mode_properties(Object *obj)
-+void riscv_add_satp_mode_properties(Object *obj)
- {
-     RISCVCPU *cpu = RISCV_CPU(obj);
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
- static void riscv_cpu_add_user_properties(Object *obj)
- {
- #ifndef CONFIG_USER_ONLY
--    riscv_add_satp_mode_properties(obj);
--
-     if (kvm_enabled()) {
-         kvm_riscv_cpu_add_kvm_properties(obj);
-         return;
-     }
-+    riscv_add_satp_mode_properties(obj);
- #endif
-     riscv_cpu_add_misa_properties(obj);
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-     DeviceState *dev = DEVICE(obj);
-     riscv_init_user_properties(obj);
-+    riscv_add_satp_mode_properties(obj);
-     riscv_cpu_add_misa_properties(obj);
-     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
---
-.41.0

-[PULL 33/54] target/riscv: introduce KVM AccelCPUClass
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Add a KVM accelerator class like we did with TCG. The difference is
-that, at least for now, we won't be using a realize() implementation for
-this accelerator.
-We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
-kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
-riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
-through the 'cpu_instance_init' impl of the current acceleration (if
-available) and execute it. The end result is that the KVM initial setup,
-i.e. starting registers and adding its specific properties, will be done
-via this hook.
-Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
-calling riscv_cpu_add_user_properties() when running KVM. We'll remove
-this condition when the TCG accel class get its own 'cpu_instance_init'
-implementation.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-12-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/kvm_riscv.h |  1 -
- target/riscv/cpu.c       |  8 +++-----
- target/riscv/kvm.c       | 26 ++++++++++++++++++++++++--
-files changed, 27 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm_riscv.h
-+++ b/target/riscv/kvm_riscv.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef QEMU_KVM_RISCV_H
- #define QEMU_KVM_RISCV_H
--void kvm_riscv_cpu_add_kvm_properties(Object *obj);
- void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
- void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
- void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_user_properties(Object *cpu_obj)
- static void riscv_cpu_post_init(Object *obj)
- {
--    if (riscv_cpu_has_user_properties(obj)) {
-+    accel_cpu_instance_init(CPU(obj));
-+
-+    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
-         riscv_cpu_add_user_properties(obj);
-     }
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
- static void riscv_cpu_add_user_properties(Object *obj)
- {
- #ifndef CONFIG_USER_ONLY
--    if (kvm_enabled()) {
--        kvm_riscv_cpu_add_kvm_properties(obj);
--        return;
--    }
-     riscv_add_satp_mode_properties(obj);
- #endif
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/kvm_int.h"
- #include "cpu.h"
- #include "trace.h"
-+#include "hw/core/accel-cpu.h"
- #include "hw/pci/pci.h"
- #include "exec/memattrs.h"
- #include "exec/address-spaces.h"
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
- }
--void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-+static void kvm_cpu_instance_init(CPUState *cs)
- {
-+    Object *obj = OBJECT(RISCV_CPU(cs));
-     DeviceState *dev = DEVICE(obj);
-     riscv_init_user_properties(obj);
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
-     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
--        /* Check if KVM created the property already */
-+        /* Check if we have a specific KVM handler for the option */
-         if (object_property_find(obj, prop->name)) {
-             continue;
-         }
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-     }
- }
-+static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
-+{
-+    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
-+
-+    acc->cpu_instance_init = kvm_cpu_instance_init;
-+}
-+
-+static const TypeInfo kvm_cpu_accel_type_info = {
-+    .name = ACCEL_CPU_NAME("kvm"),
-+
-+    .parent = TYPE_ACCEL_CPU,
-+    .class_init = kvm_cpu_accel_class_init,
-+    .abstract = true,
-+};
-+static void kvm_cpu_accel_register_types(void)
-+{
-+    type_register_static(&kvm_cpu_accel_type_info);
-+}
-+type_init(kvm_cpu_accel_register_types);
-+
- static void riscv_host_cpu_init(Object *obj)
- {
-     CPURISCVState *env = &RISCV_CPU(obj)->env;
---
-.41.0

-[PULL 40/54] target/riscv/cpu.c: export isa_edata_arr[]
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This array will be read by the TCG accel class, allowing it to handle
-priv spec verifications on its own. The array will remain here in cpu.c
-because it's also used by the riscv,isa string function.
-To export it we'll finish it with an empty element since ARRAY_SIZE()
-won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
-alleviate the changes for the next patch.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20230925175709.35696-19-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h |  7 +++++++
- target/riscv/cpu.c | 47 +++++++++++++++++++++-------------------------
-files changed, 28 insertions(+), 26 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
- extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
- extern Property riscv_cpu_options[];
-+typedef struct isa_ext_data {
-+    const char *name;
-+    int min_version;
-+    int ext_enable_offset;
-+} RISCVIsaExtData;
-+extern const RISCVIsaExtData isa_edata_arr[];
-+
- void riscv_add_satp_mode_properties(Object *obj);
- /* CSR function table */
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
- const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
-                               RVC, RVS, RVU, RVH, RVJ, RVG, 0};
--struct isa_ext_data {
--    const char *name;
--    int min_version;
--    int ext_enable_offset;
--};
--
--#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
--    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
--
- /*
-  * From vector_helper.c
-  * Note that vector data is stored in host-endian 64-bit chunks,
-@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
- #define BYTE(x)   (x)
- #endif
-+#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
-+    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
-+
- /*
-  * Here are the ordering rules of extension naming defined by RISC-V
-  * specification :
-@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
-  * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
-  * instead.
-  */
--static const struct isa_ext_data isa_edata_arr[] = {
-+const RISCVIsaExtData isa_edata_arr[] = {
-     ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
-     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
-     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
-     ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
-     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
-+
-+    DEFINE_PROP_END_OF_LIST(),
- };
- bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
-@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
- int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
- {
--    int i;
-+    const RISCVIsaExtData *edata;
--    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
--        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
-+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
-+        if (edata->ext_enable_offset != ext_offset) {
-             continue;
-         }
--        return isa_edata_arr[i].min_version;
-+        return edata->min_version;
-     }
-     g_assert_not_reached();
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
- void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
- {
-     CPURISCVState *env = &cpu->env;
--    int i;
-+    const RISCVIsaExtData *edata;
-     /* Force disable extensions if priv spec version does not match */
--    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
--        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
--            (env->priv_ver < isa_edata_arr[i].min_version)) {
--            isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
--                                   false);
-+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
-+        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
-+            (env->priv_ver < edata->min_version)) {
-+            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
- #ifndef CONFIG_USER_ONLY
-             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
-                         " because privilege spec version does not match",
--                        isa_edata_arr[i].name, env->mhartid);
-+                        edata->name, env->mhartid);
- #else
-             warn_report("disabling %s extension because "
-                         "privilege spec version does not match",
--                        isa_edata_arr[i].name);
-+                        edata->name);
- #endif
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
- static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
-                                  int max_str_len)
- {
-+    const RISCVIsaExtData *edata;
-     char *old = *isa_str;
-     char *new = *isa_str;
--    int i;
--    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
--        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
--            new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
-+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
-+        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
-+            new = g_strconcat(old, "_", edata->name, NULL);
-             g_free(old);
-             old = new;
-         }
---
-.41.0

-[PULL 44/54] softmmu: add means to pass an exit code when requesting a shutdown
+Deleted patch
-From: Clément Chigot <chigot@adacore.com>
-As of now, the exit code was either EXIT_FAILURE when a panic shutdown
-was requested or EXIT_SUCCESS otherwise.
-However, some hardware could want to pass more complex exit codes. Thus,
-introduce a new shutdown request function allowing that.
-Signed-off-by: Clément Chigot <chigot@adacore.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20231003071427.188697-2-chigot@adacore.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/sysemu/runstate.h |  2 ++
- system/runstate.c         | 12 +++++++++++-
-files changed, 13 insertions(+), 1 deletion(-)
-diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/runstate.h
-+++ b/include/sysemu/runstate.h
-@@ -XXX,XX +XXX,XX @@ void qemu_system_wakeup_request(WakeupReason reason, Error **errp);
- void qemu_system_wakeup_enable(WakeupReason reason, bool enabled);
- void qemu_register_wakeup_notifier(Notifier *notifier);
- void qemu_register_wakeup_support(void);
-+void qemu_system_shutdown_request_with_code(ShutdownCause reason,
-+                                            int exit_code);
- void qemu_system_shutdown_request(ShutdownCause reason);
- void qemu_system_powerdown_request(void);
- void qemu_register_powerdown_notifier(Notifier *notifier);
-diff --git a/system/runstate.c b/system/runstate.c
-index XXXXXXX..XXXXXXX 100644
---- a/system/runstate.c
-+++ b/system/runstate.c
-@@ -XXX,XX +XXX,XX @@ void vm_state_notify(bool running, RunState state)
- static ShutdownCause reset_requested;
- static ShutdownCause shutdown_requested;
-+static int shutdown_exit_code = EXIT_SUCCESS;
- static int shutdown_signal;
- static pid_t shutdown_pid;
- static int powerdown_requested;
-@@ -XXX,XX +XXX,XX @@ void qemu_system_killed(int signal, pid_t pid)
-     qemu_notify_event();
- }
-+void qemu_system_shutdown_request_with_code(ShutdownCause reason,
-+                                            int exit_code)
-+{
-+    shutdown_exit_code = exit_code;
-+    qemu_system_shutdown_request(reason);
-+}
-+
- void qemu_system_shutdown_request(ShutdownCause reason)
- {
-     trace_qemu_system_shutdown_request(reason);
-@@ -XXX,XX +XXX,XX @@ static bool main_loop_should_exit(int *status)
-         if (shutdown_action == SHUTDOWN_ACTION_PAUSE) {
-             vm_stop(RUN_STATE_SHUTDOWN);
-         } else {
--            if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
-+            if (shutdown_exit_code != EXIT_SUCCESS) {
-+                *status = shutdown_exit_code;
-+            } else if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
-                 panic_action == PANIC_ACTION_EXIT_FAILURE) {
-                 *status = EXIT_FAILURE;
-             }
---
-.41.0

-[PULL 45/54] softmmu: pass the main loop status to gdb "Wxx" packet
+Deleted patch
-From: Clément Chigot <chigot@adacore.com>
-gdb_exit function aims to close gdb sessions and sends the exit code of
-the current execution. It's being called by qemu_cleanup once the main
-loop is over.
-Until now, the exit code sent was always 0. Now that hardware can
-shutdown this main loop with custom exit codes, these codes must be
-transfered to gdb as well.
-Signed-off-by: Clément Chigot <chigot@adacore.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20231003071427.188697-3-chigot@adacore.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/sysemu/sysemu.h | 2 +-
- system/main.c           | 2 +-
- system/runstate.c       | 4 ++--
-files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/sysemu.h
-+++ b/include/sysemu/sysemu.h
-@@ -XXX,XX +XXX,XX @@ bool defaults_enabled(void);
- void qemu_init(int argc, char **argv);
- int qemu_main_loop(void);
--void qemu_cleanup(void);
-+void qemu_cleanup(int);
- extern QemuOptsList qemu_legacy_drive_opts;
- extern QemuOptsList qemu_common_drive_opts;
-diff --git a/system/main.c b/system/main.c
-index XXXXXXX..XXXXXXX 100644
---- a/system/main.c
-+++ b/system/main.c
-@@ -XXX,XX +XXX,XX @@ int qemu_default_main(void)
-     int status;
-     status = qemu_main_loop();
--    qemu_cleanup();
-+    qemu_cleanup(status);
-     return status;
- }
-diff --git a/system/runstate.c b/system/runstate.c
-index XXXXXXX..XXXXXXX 100644
---- a/system/runstate.c
-+++ b/system/runstate.c
-@@ -XXX,XX +XXX,XX @@ void qemu_init_subsystems(void)
- }
--void qemu_cleanup(void)
-+void qemu_cleanup(int status)
- {
--    gdb_exit(0);
-+    gdb_exit(status);
-     /*
-      * cleaning up the migration object cancels any existing migration
---
-.41.0

-[PULL 46/54] hw/misc/sifive_test.c: replace exit calls with proper shutdown
+Deleted patch
-From: Clément Chigot <chigot@adacore.com>
-This replaces the exit calls by shutdown requests, ensuring a proper
-cleanup of Qemu. Otherwise, some connections like gdb could be broken
-before its final packet ("Wxx") is being sent. This part, being done
-inside qemu_cleanup function, can be reached only when the main loop
-exits after a shutdown request.
-Signed-off-by: Clément Chigot <chigot@adacore.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20231003071427.188697-4-chigot@adacore.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/misc/sifive_test.c | 9 +++++++--
-file changed, 7 insertions(+), 2 deletions(-)
-diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/sifive_test.c
-+++ b/hw/misc/sifive_test.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/module.h"
- #include "sysemu/runstate.h"
- #include "hw/misc/sifive_test.h"
-+#include "sysemu/sysemu.h"
- static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
- {
-@@ -XXX,XX +XXX,XX @@ static void sifive_test_write(void *opaque, hwaddr addr,
-         int code = (val64 >> 16) & 0xffff;
-         switch (status) {
-         case FINISHER_FAIL:
--            exit(code);
-+            qemu_system_shutdown_request_with_code(
-+                SHUTDOWN_CAUSE_GUEST_PANIC, code);
-+            return;
-         case FINISHER_PASS:
--            exit(0);
-+            qemu_system_shutdown_request_with_code(
-+                SHUTDOWN_CAUSE_GUEST_SHUTDOWN, code);
-+            return;
-         case FINISHER_RESET:
-             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-             return;
---
-.41.0

-[PULL 47/54] hw/char: riscv_htif: replace exit calls with proper shutdown
+Deleted patch
-From: Clément Chigot <chigot@adacore.com>
-This replaces the exit calls by shutdown requests, ensuring a proper
-cleanup of Qemu. Otherwise, some connections like gdb could be broken
-before its final packet ("Wxx") is being sent. This part, being done
-inside qemu_cleanup function, can be reached only when the main loop
-exits after a shutdown request.
-Signed-off-by: Clément Chigot <chigot@adacore.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20231003071427.188697-5-chigot@adacore.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/char/riscv_htif.c | 5 ++++-
-file changed, 4 insertions(+), 1 deletion(-)
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/riscv_htif.c
-+++ b/hw/char/riscv_htif.c
-@@ -XXX,XX +XXX,XX @@
- #include "exec/address-spaces.h"
- #include "exec/tswap.h"
- #include "sysemu/dma.h"
-+#include "sysemu/runstate.h"
- #define RISCV_DEBUG_HTIF 0
- #define HTIF_DEBUG(fmt, ...)                                                   \
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
-                     g_free(sig_data);
-                 }
--                exit(exit_code);
-+                qemu_system_shutdown_request_with_code(
-+                    SHUTDOWN_CAUSE_GUEST_SHUTDOWN, exit_code);
-+                return;
-             } else {
-                 uint64_t syscall[8];
-                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
---
-.41.0

The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2:

Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into staging (2023-10-11 09:43:10 -0400)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231012-1

for you to fetch changes up to 837570cef237b634eb4c245363470deebea7089d:

target/riscv: Fix vfwmaccbf16.vf (2023-10-12 12:50:13 +1000)

----------------------------------------------------------------
Second RISC-V PR for 8.2

* Add support for the max CPU
 * Detect user choice in TCG
 * Clear CSR values at reset and sync MPSTATE with host
 * Fix the typo of inverted order of pmpaddr13 and pmpaddr14
 * Split TCG/KVM accelerators from cpu.c
 * Add extension properties for all cpus
 * Replace GDB exit calls with proper shutdown
 * Support KVM_GET_REG_LIST
 * Remove RVG warning
 * Use env_archcpu for better performance
 * Deprecate capital 'Z' CPU properties
 * Fix vfwmaccbf16.vf

----------------------------------------------------------------
Alvin Chang (1):
      disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14

Clément Chigot (5):
      softmmu: add means to pass an exit code when requesting a shutdown
      softmmu: pass the main loop status to gdb "Wxx" packet
      hw/misc/sifive_test.c: replace exit calls with proper shutdown
      hw/char: riscv_htif: replace exit calls with proper shutdown
      gdbstub: replace exit calls with proper shutdown for softmmu

Daniel Henrique Barboza (45):
      target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
      target/riscv/cpu.c: skip 'bool' check when filtering KVM props
      target/riscv/cpu.c: split kvm prop handling to its own helper
      target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
      target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
      target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
      target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
      target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
      target/riscv/cpu.c: limit cfg->vext_spec log message
      target/riscv: add 'max' CPU type
      avocado, risc-v: add tuxboot tests for 'max' CPU
      target/riscv: deprecate the 'any' CPU type
      target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
      target/riscv: make CPUCFG() macro public
      target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
      target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
      target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
      target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
      target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
      target/riscv/cpu.c: consider user option with RVG
      target/riscv: introduce TCG AccelCPUClass
      target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
      target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
      target/riscv: move riscv_tcg_ops to tcg-cpu.c
      target/riscv/cpu.c: add .instance_post_init()
      target/riscv: move 'host' CPU declaration to kvm.c
      target/riscv/cpu.c: mark extensions arrays as 'const'
      target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
      target/riscv: make riscv_add_satp_mode_properties() public
      target/riscv: remove kvm-stub.c
      target/riscv: introduce KVM AccelCPUClass
      target/riscv: move KVM only files to kvm subdir
      target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
      target/riscv/cpu.c: export set_misa()
      target/riscv/tcg: introduce tcg_cpu_instance_init()
      target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
      target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
      target/riscv/cpu.c: export isa_edata_arr[]
      target/riscv/cpu: move priv spec functions to tcg-cpu.c
      target/riscv: add riscv_cpu_get_name()
      target/riscv/tcg-cpu.c: add extension properties for all cpus
      target/riscv/kvm: improve 'init_multiext_cfg' error msg
      target/riscv/kvm: support KVM_GET_REG_LIST
      target/riscv/tcg: remove RVG warning
      target/riscv: deprecate capital 'Z' CPU properties

Max Chou (1):
      target/riscv: Fix vfwmaccbf16.vf

Richard W.M. Jones (1):
      target/riscv: Use env_archcpu for better performance

liguang.zhang (1):
      target/riscv: Clear CSR values at reset and sync MPSTATE with host

docs/about/deprecated.rst             |   35 ++
 include/gdbstub/syscalls.h            |    9 +
 include/sysemu/runstate.h             |    2 +
 include/sysemu/sysemu.h               |    2 +-
 target/riscv/cpu-qom.h                |    1 +
 target/riscv/cpu.h                    |   34 +-
 target/riscv/{ => kvm}/kvm_riscv.h    |    2 +-
 target/riscv/tcg/tcg-cpu.h            |   27 +
 disas/riscv.c                         |    4 +-
 gdbstub/gdbstub.c                     |    5 +-
 gdbstub/system.c                      |    6 +
 gdbstub/user.c                        |    6 +
 hw/char/riscv_htif.c                  |    5 +-
 hw/intc/riscv_aplic.c                 |    2 +-
 hw/misc/sifive_test.c                 |    9 +-
 hw/riscv/virt.c                       |    2 +-
 system/main.c                         |    2 +-
 system/runstate.c                     |   16 +-
 target/riscv/cpu.c                    | 1030 +++++++--------------------------
 target/riscv/cpu_helper.c             |    3 +-
 target/riscv/csr.c                    |    1 +
 target/riscv/kvm-stub.c               |   30 -
 target/riscv/{kvm.c => kvm/kvm-cpu.c} |  272 ++++++++-
 target/riscv/tcg/tcg-cpu.c            |  949 ++++++++++++++++++++++++++++++
 target/riscv/vector_helper.c          |    2 +-
 target/riscv/kvm/meson.build          |    1 +
 target/riscv/meson.build              |    4 +-
 target/riscv/tcg/meson.build          |    2 +
 tests/avocado/tuxrun_baselines.py     |   32 +
 29 files changed, 1604 insertions(+), 891 deletions(-)
 rename target/riscv/{ => kvm}/kvm_riscv.h (95%)
 create mode 100644 target/riscv/tcg/tcg-cpu.h
 delete mode 100644 target/riscv/kvm-stub.c
 rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (81%)
 create mode 100644 target/riscv/tcg/tcg-cpu.c
 create mode 100644 target/riscv/kvm/meson.build
 create mode 100644 target/riscv/tcg/meson.build

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.

Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] array for them. Add all these properties in
riscv_cpu_add_user_properties() as it is already being done today.

'mmu' and 'pmp' aren't really extensions in the usual way we think about
RISC-V extensions. These are closer to CPU features/options, so move
both to riscv_cpu_options[] too. In the near future we'll need to match
all extensions with all entries in isa_edata_arr[], and so it happens
that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv
spec version restriction). This further emphasizes the point that these
are more a CPU option than an extension.

No functional changes made.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 
 static Property riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
-    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
     DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
     DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
-    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
-    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
     DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
 
-    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
-    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
-    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-
     DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
     DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
 
     DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
-    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
     DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
-    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
 
     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
 
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static Property riscv_cpu_options[] = {
+    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
+
+    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+
+    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+
+    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+
+    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
+    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+};
 
 #ifndef CONFIG_USER_ONLY
 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
 #endif
         qdev_property_add_static(dev, prop);
     }
+
+    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+        /* Check if KVM created the property already */
+        if (object_property_find(obj, riscv_cpu_options[i].name)) {
+            continue;
+        }
+        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+    }
 }
 
 static Property riscv_cpu_properties[] = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
              * Set the default to disabled for every extension
              * unknown to KVM and error out if the user attempts
              * to enable any of them.
-             *
-             * We're giving a pass for non-bool properties since they're
-             * not related to the availability of extensions and can be
-             * safely ignored as is.
              */
-            if (prop->info == &qdev_prop_bool) {
-                object_property_add(obj, prop->name, "bool",
-                                    NULL, cpu_set_cfg_unavailable,
-                                    NULL, (void *)prop->name);
-                continue;
-            }
+            object_property_add(obj, prop->name, "bool",
+                                NULL, cpu_set_cfg_unavailable,
+                                NULL, (void *)prop->name);
+            continue;
         }
 #endif
         qdev_property_add_static(dev, prop);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to share a couple of common
lines of code between the two.

Create a new kvm_riscv_cpu_add_kvm_properties() helper that will be
forked from riscv_cpu_add_user_properties() if we're running KVM. The
helper includes all properties that a KVM CPU will add. The rest of
riscv_cpu_add_user_properties() body will then be relieved from having
to deal with KVM constraints.

The helper was declared in kvm_stubs.h, while being implemented in
cpu.c, to allow '--enable-debug' builds to work. The compiler won't
remove the kvm_riscv_cpu_add_kvm_properties() reference when
'kvm_enabled()' is false if we end up with an unused function. Even
though being a KVM only helper we can't implement it in kvm.c due to its
many dependencies inside cpu.c, so make it public in kvm_riscv.h and
keep its implementation in cpu.c for now. We'll move it to kvm.c in the
near future.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm_riscv.h |  3 ++
 target/riscv/cpu.c       | 65 +++++++++++++++++++++++++---------------
 2 files changed, 44 insertions(+), 24 deletions(-)

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #ifndef QEMU_KVM_RISCV_H
 #define QEMU_KVM_RISCV_H
 
+/* Temporarily implemented in cpu.c */
+void kvm_riscv_cpu_add_kvm_properties(Object *obj);
+
 void kvm_riscv_init_user_properties(Object *cpu_obj);
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
 };
 
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_KVM
 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                                     const char *name,
                                     void *opaque, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                    propname);
     }
 }
+
+static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+{
+    /* Check if KVM created the property already */
+    if (object_property_find(obj, prop_name)) {
+        return;
+    }
+
+    /*
+     * Set the default to disabled for every extension
+     * unknown to KVM and error out if the user attempts
+     * to enable any of them.
+     */
+    object_property_add(obj, prop_name, "bool",
+                        NULL, cpu_set_cfg_unavailable,
+                        NULL, (void *)prop_name);
+}
+
+void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+{
+    Property *prop;
+    DeviceState *dev = DEVICE(obj);
+
+    kvm_riscv_init_user_properties(obj);
+    riscv_cpu_add_misa_properties(obj);
+
+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+
+    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+        /* Check if KVM created the property already */
+        if (object_property_find(obj, riscv_cpu_options[i].name)) {
+            continue;
+        }
+        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+    }
+}
 #endif
 
 /*
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     riscv_add_satp_mode_properties(obj);
 
     if (kvm_enabled()) {
-        kvm_riscv_init_user_properties(obj);
+        kvm_riscv_cpu_add_kvm_properties(obj);
+        return;
     }
 #endif
 
     riscv_cpu_add_misa_properties(obj);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-#ifndef CONFIG_USER_ONLY
-        if (kvm_enabled()) {
-            /* Check if KVM created the property already */
-            if (object_property_find(obj, prop->name)) {
-                continue;
-            }
-
-            /*
-             * Set the default to disabled for every extension
-             * unknown to KVM and error out if the user attempts
-             * to enable any of them.
-             */
-            object_property_add(obj, prop->name, "bool",
-                                NULL, cpu_set_cfg_unavailable,
-                                NULL, (void *)prop->name);
-            continue;
-        }
-#endif
         qdev_property_add_static(dev, prop);
     }
 
     for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
-        /* Check if KVM created the property already */
-        if (object_property_find(obj, riscv_cpu_options[i].name)) {
-            continue;
-        }
         qdev_property_add_static(dev, &riscv_cpu_options[i]);
     }
 }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].

We also have a more sophisticated motivation behind this change. In the
future we might need to export riscv_cpu_options[] to other files, and
ARRAY_LIST() doesn't work properly in that case because the array size
isn't exposed to the header file. Here's a future sight of what we would
deal with:

./target/riscv/kvm.c:1057:5: error: nested extern declaration of 'riscv_cpu_add_misa_properties' [-Werror=nested-externs]
n file included from ../target/riscv/kvm.c:19:
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
 473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
     |                               ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 |         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
     |                             ^~~~~~~~~~
./target/riscv/kvm.c:1059:5: note: in expansion of macro 'ADD_UNAVAIL_KVM_PROP_ARRAY'
1059 |     ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions);
     |     ^~~~~~~~~~~~~~~~~~~~~~~~~~
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
 473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
     |                               ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 |         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \

Homogenize the present and change the future by using
DEFINE_PROP_END_OF_LIST() in riscv_cpu_options[].

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
 
     DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+
+    DEFINE_PROP_END_OF_LIST(),
 };
 
 #ifdef CONFIG_KVM
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 
-    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if KVM created the property already */
-        if (object_property_find(obj, riscv_cpu_options[i].name)) {
+        if (object_property_find(obj, prop->name)) {
             continue;
         }
-        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+        qdev_property_add_static(dev, prop);
     }
 }
 #endif
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
         qdev_property_add_static(dev, prop);
     }
 
-    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
-        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
     }
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].

riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratified properties to users.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 
-    /* These are experimental so mark with 'x-' */
+    DEFINE_PROP_END_OF_LIST(),
+};
 
+/* These are experimental so mark with 'x-' */
+static Property riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
     DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 
+    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+
     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if KVM created the property already */
         if (object_property_find(obj, prop->name)) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         qdev_property_add_static(dev, prop);
     }
+
+    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
+    }
 }
 
 static Property riscv_cpu_properties[] = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.

Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
     DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
 
-    /* Vendor-specific custom extensions */
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static Property riscv_cpu_vendor_exts[] = {
     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
     DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
     DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 
+    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+
     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
         qdev_property_add_static(dev, prop);
     }
 
+    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
+    }
+
     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
         qdev_property_add_static(dev, prop);
     }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a helper to hide the repetition away.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 29 +++++++++++++----------------
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
+{
+    g_assert(array);
+
+    for (Property *prop = array; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
+    }
+}
+
 #ifdef CONFIG_KVM
 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                                     const char *name,
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
  */
 static void riscv_cpu_add_user_properties(Object *obj)
 {
-    Property *prop;
     DeviceState *dev = DEVICE(obj);
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
 
     riscv_cpu_add_misa_properties(obj);
 
-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
-
-    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
-
-    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
-
-    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
 }
 
 static Property riscv_cpu_properties[] = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230912132423.268494-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
                         NULL, (void *)prop_name);
 }
 
+static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
+                                                 Property *array)
+{
+    g_assert(array);
+
+    for (Property *prop = array; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+}
+
 void kvm_riscv_cpu_add_kvm_properties(Object *obj)
 {
     Property *prop;
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     kvm_riscv_init_user_properties(obj);
     riscv_cpu_add_misa_properties(obj);
 
-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
-
-    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
-
-    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 
     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if KVM created the property already */
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.

We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
version is not specified" message from appearing. The usefulness of this
log message is debatable for the generic CPUs, but for a 'max' CPU type,
where we are supposed to deliver a CPU model with all features possible,
it's strange to force users to set 'vext_spec' to get rid of this
message.

Change riscv_cpu_validate_v() to not throw this log message if
env->vext_ver is already set.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230912132423.268494-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
                                  Error **errp)
 {
-    int vext_version = VEXT_VERSION_1_00_0;
-
     if (!is_power_of_2(cfg->vlen)) {
         error_setg(errp, "Vector extension VLEN must be power of 2");
         return;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
     }
     if (cfg->vext_spec) {
         if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
-            vext_version = VEXT_VERSION_1_00_0;
+            env->vext_ver = VEXT_VERSION_1_00_0;
         } else {
             error_setg(errp, "Unsupported vector spec version '%s'",
                        cfg->vext_spec);
             return;
         }
-    } else {
+    } else if (env->vext_ver == 0) {
         qemu_log("vector version is not specified, "
                  "use the default value v1.0\n");
+
+        env->vext_ver = VEXT_VERSION_1_00_0;
     }
-    env->vext_ver = vext_version;
 }
 
 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.

What we consider "most capable CPU" in this context are related to
ratified, non-vendor extensions. This means that we want the 'max' CPU
to enable all (possible) ratified extensions by default. The reasoning
behind this design is (1) vendor extensions can conflict with each other
and we won't play favorities deciding which one is default or not and
(2) non-ratified extensions are always prone to changes, not being
stable enough to be enabled by default.

All this said, we're still not able to enable all ratified extensions
due to conflicts between them. Zfinx and all its dependencies aren't
enabled because of a conflict with RVF. zce, zcmp and zcmt are also
disabled due to RVD conflicts. When running with 64 bits we're also
disabling zcf.

MISA bits RVG, RVJ and RVV are also being set manually since they're
default disabled.

This is the resulting 'riscv,isa' DT for this new CPU:

rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu-qom.h |  1 +
 target/riscv/cpu.c     | 56 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -XXX,XX +XXX,XX @@
 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
 
 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
+#define TYPE_RISCV_CPU_MAX              RISCV_CPU_TYPE_NAME("max")
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
 #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
 };
 
 static void riscv_cpu_add_user_properties(Object *obj);
+static void riscv_init_max_cpu_extensions(Object *obj);
 
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 {
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
     cpu->cfg.pmp = true;
 }
 
+static void riscv_max_cpu_init(Object *obj)
+{
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    RISCVMXL mlx = MXL_RV64;
+
+#ifdef TARGET_RISCV32
+    mlx = MXL_RV32;
+#endif
+    set_misa(env, mlx, 0);
+    riscv_cpu_add_user_properties(obj);
+    riscv_init_max_cpu_extensions(obj);
+    env->priv_ver = PRIV_VERSION_LATEST;
+#ifndef CONFIG_USER_ONLY
+    set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
+                                VM_1_10_SV32 : VM_1_10_SV57);
+#endif
+}
+
 #if defined(TARGET_RISCV64)
 static void rv64_base_cpu_init(Object *obj)
 {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
 }
 
+/*
+ * The 'max' type CPU will have all possible ratified
+ * non-vendor extensions enabled.
+ */
+static void riscv_init_max_cpu_extensions(Object *obj)
+{
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    Property *prop;
+
+    /* Enable RVG, RVJ and RVV that are disabled by default */
+    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+
+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+        object_property_set_bool(obj, prop->name, true, NULL);
+    }
+
+    /* set vector version */
+    env->vext_ver = VEXT_VERSION_1_00_0;
+
+    /* Zfinx is not compatible with F. Disable it */
+    object_property_set_bool(obj, "zfinx", false, NULL);
+    object_property_set_bool(obj, "zdinx", false, NULL);
+    object_property_set_bool(obj, "zhinx", false, NULL);
+    object_property_set_bool(obj, "zhinxmin", false, NULL);
+
+    object_property_set_bool(obj, "zce", false, NULL);
+    object_property_set_bool(obj, "zcmp", false, NULL);
+    object_property_set_bool(obj, "zcmt", false, NULL);
+
+    if (env->misa_mxl != MXL_RV32) {
+        object_property_set_bool(obj, "zcf", false, NULL);
+    }
+}
+
 static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .abstract = true,
     },
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
+    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
 #if defined(CONFIG_KVM)
     DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
 #endif
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new frozen/ratified RISC-V extensions.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tests/avocado/tuxrun_baselines.py | 32 +++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/tuxrun_baselines.py
+++ b/tests/avocado/tuxrun_baselines.py
@@ -XXX,XX +XXX,XX @@ def test_riscv64(self):
 
         self.common_tuxrun(csums=sums)
 
+    def test_riscv32_maxcpu(self):
+        """
+        :avocado: tags=arch:riscv32
+        :avocado: tags=machine:virt
+        :avocado: tags=cpu:max
+        :avocado: tags=tuxboot:riscv32
+        """
+        sums = { "Image" :
+                 "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
+                 "fw_jump.elf" :
+                 "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
+                 "rootfs.ext4.zst" :
+                 "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
+
+        self.common_tuxrun(csums=sums)
+
+    def test_riscv64_maxcpu(self):
+        """
+        :avocado: tags=arch:riscv64
+        :avocado: tags=machine:virt
+        :avocado: tags=cpu:max
+        :avocado: tags=tuxboot:riscv64
+        """
+        sums = { "Image" :
+                 "cd634badc65e52fb63465ec99e309c0de0369f0841b7d9486f9729e119bac25e",
+                 "fw_jump.elf" :
+                 "6e3373abcab4305fe151b564a4c71110d833c21f2c0a1753b7935459e36aedcf",
+                 "rootfs.ext4.zst" :
+                 "b18e3a3bdf27be03da0b285e84cb71bf09eca071c3a087b42884b6982ed679eb" }
+
+        self.common_tuxrun(csums=sums)
+
     def test_s390(self):
         """
         :avocado: tags=arch:s390x
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't help us either in
knowing what was the original design of this CPU type.

The closest we have is a comment from Alistair [1] where he recalls from
memory that the 'any' CPU is supposed to behave like the newly added
'max' CPU. He also suggested that the 'any' CPU should be removed.

The default CPUs are rv32 and rv64, so removing the 'any' CPU will have
impact only on users that might have a script that uses '-cpu any'.
And those users are better off using the default CPUs or the new 'max'
CPU.

We would love to just remove the code and be done with it, but one does
not simply remove a feature in QEMU. We'll put the CPU in quarantine
first, letting users know that we have the intent of removing it in the
future.

[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst | 12 ++++++++++++
 target/riscv/cpu.c        |  5 +++++
 2 files changed, 17 insertions(+)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ QEMU's ``vhost`` feature, which would eliminate the high latency costs under
 which the 9p ``proxy`` backend currently suffers. However as of to date nobody
 has indicated plans for such kind of reimplementation unfortunately.
 
+RISC-V 'any' CPU type ``-cpu any`` (since 8.2)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The 'any' CPU type was introduced back in 2018 and has been around since the
+initial RISC-V QEMU port. Its usage has always been unclear: users don't know
+what to expect from a CPU called 'any', and in fact the CPU does not do anything
+special that isn't already done by the default CPUs rv32/rv64.
+
+After the introduction of the 'max' CPU type, RISC-V now has a good coverage
+of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
+CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
+CPU type starting in 8.2.
 
 Block device options
 ''''''''''''''''''''
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
     Error *local_err = NULL;
 
+    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
+        warn_report("The 'any' CPU is deprecated and will be "
+                    "removed in the future.");
+    }
+
     cpu_exec_realizefn(cs, &local_err);
     if (local_err != NULL) {
         error_propagate(errp, local_err);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.

Change all existing callers to use edata->ext_enable_offset instead of
'edata'.

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.

Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 ++
 target/riscv/cpu.c | 2 +-
 target/riscv/kvm.c | 8 +++-----
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 const char *riscv_get_misa_ext_name(uint32_t bit);
 const char *riscv_get_misa_ext_description(uint32_t bit);
 
+#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
+
 /* Privileged specification version */
 enum {
     PRIV_VERSION_1_10_0 = 0,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
 };
 
 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
-    {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
 
 /*
  * From vector_helper.c
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
     }
 }
 
-#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
-
 #define KVM_EXT_CFG(_name, _prop, _reg_id) \
-    {.name = _name, .offset = CPUCFG(_prop), \
+    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .kvm_reg_id = _reg_id}
 
 static KVMCPUConfig kvm_multi_ext_cfgs[] = {
@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v,
 
 static KVMCPUConfig kvm_cbom_blocksize = {
     .name = "cbom_blocksize",
-    .offset = CPUCFG(cbom_blocksize),
+    .offset = CPU_CFG_OFFSET(cbom_blocksize),
     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)
 };
 
 static KVMCPUConfig kvm_cboz_blocksize = {
     .name = "cboz_blocksize",
-    .offset = CPUCFG(cboz_blocksize),
+    .offset = CPU_CFG_OFFSET(cboz_blocksize),
     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
 };
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

During realize() time we're activating a lot of extensions based on some
criteria, e.g.:

if (cpu->cfg.ext_zk) {
        cpu->cfg.ext_zkn = true;
        cpu->cfg.ext_zkr = true;
        cpu->cfg.ext_zkt = true;
    }

This practice resulted in at least one case where we ended up enabling
something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that
has priv_spec older than 1.12.0.

We're also not considering user choice. There's no way of doing it now
but this is about to change in the next few patches.

cpu_cfg_ext_auto_update() will check for priv version mismatches before
enabling extensions. If we have a mismatch between the current priv
version and the extension we want to enable, do not enable it. In the
near future, this same function will also consider user choice when
deciding if we're going to enable/disable an extension or not.

For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
     *ext_enabled = en;
 }
 
+static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
+            continue;
+        }
+
+        return isa_edata_arr[i].min_version;
+    }
+
+    g_assert_not_reached();
+}
+
+static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
+                                    bool value)
+{
+    CPURISCVState *env = &cpu->env;
+    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
+    int min_version;
+
+    if (prev_val == value) {
+        return;
+    }
+
+    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
+        /* Do not enable it if priv_ver is older than min_version */
+        min_version = cpu_cfg_ext_get_min_version(ext_offset);
+        if (env->priv_ver < min_version) {
+            return;
+        }
+    }
+
+    isa_ext_update_enabled(cpu, ext_offset, value);
+}
+
 const char * const riscv_int_regnames[] = {
     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 
     /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
     if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
-        cpu->cfg.ext_zca = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu->cfg.ext_zcf = true;
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
         }
         if (riscv_has_ext(env, RVD)) {
-            cpu->cfg.ext_zcd = true;
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
         }
     }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).

We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every other extension enablement
during realize is now done via cpu_cfg_ext_auto_update().

The end goal is that only cpu init() functions will handle extension
flags directly via "cpu->cfg.ext_N = true|false".

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 50 +++++++++++++++++++++++-----------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zfh) {
-        cpu->cfg.ext_zfhmin = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
     }
 
     if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         }
 
         /* The V vector extension depends on the Zve64d extension */
-        cpu->cfg.ext_zve64d = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
     }
 
     /* The Zve64d extension depends on the Zve64f extension */
     if (cpu->cfg.ext_zve64d) {
-        cpu->cfg.ext_zve64f = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
     }
 
     /* The Zve64f extension depends on the Zve32f extension */
     if (cpu->cfg.ext_zve64f) {
-        cpu->cfg.ext_zve32f = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
     }
 
     if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zvfh) {
-        cpu->cfg.ext_zvfhmin = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
     }
 
     if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 
     /* Set the ISA extensions, checks should have happened above */
     if (cpu->cfg.ext_zhinx) {
-        cpu->cfg.ext_zhinxmin = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
     }
 
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zce) {
-        cpu->cfg.ext_zca = true;
-        cpu->cfg.ext_zcb = true;
-        cpu->cfg.ext_zcmp = true;
-        cpu->cfg.ext_zcmt = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu->cfg.ext_zcf = true;
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zk) {
-        cpu->cfg.ext_zkn = true;
-        cpu->cfg.ext_zkr = true;
-        cpu->cfg.ext_zkt = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
     }
 
     if (cpu->cfg.ext_zkn) {
-        cpu->cfg.ext_zbkb = true;
-        cpu->cfg.ext_zbkc = true;
-        cpu->cfg.ext_zbkx = true;
-        cpu->cfg.ext_zkne = true;
-        cpu->cfg.ext_zknd = true;
-        cpu->cfg.ext_zknh = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
     }
 
     if (cpu->cfg.ext_zks) {
-        cpu->cfg.ext_zbkb = true;
-        cpu->cfg.ext_zbkc = true;
-        cpu->cfg.ext_zbkx = true;
-        cpu->cfg.ext_zksed = true;
-        cpu->cfg.ext_zksh = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
     }
 
     /*
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Property set()
callback. The set() callback also does init() time validations based on
the current KVM driver capabilities.

For TCG we would want a 'user_set' mechanic too, but we would look
ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set
or not. If we copy what was made in the KVM side we would look for
'user_set' for one into 60+ extension structs spreaded in 3 arrays
(riscv_cpu_extensions, riscv_cpu_experimental_exts,
riscv_cpu_vendor_exts).

We'll still need an extension struct but we won't be using the
'user_set' flag:

- 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to what
we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'.
DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by
MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct;

- the 'multi_ext_user_opts' hash will be used to store the offset of each
extension that the user set via the set() callback, cpu_set_multi_ext_cfg().
For now we're just initializing and populating it - next patch will use
it to determine if a certain extension was user set;

- cpu_add_multi_ext_prop() is a new helper that will replace the
qdev_property_add_static() calls that our macros are doing to populate
user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY()
for clarity. Note that the non-extension properties in
riscv_cpu_options[] still need to be declared via qdev().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 258 ++++++++++++++++++++++++++++-----------------
 1 file changed, 159 insertions(+), 99 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
 };
 
+/* Hash that stores user set extensions */
+static GHashTable *multi_ext_user_opts;
+
 static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
 #endif /* CONFIG_USER_ONLY */
+
+    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 }
 
 typedef struct RISCVCPUMisaExtConfig {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
     }
 }
 
-static Property riscv_cpu_extensions[] = {
+typedef struct RISCVCPUMultiExtConfig {
+    const char *name;
+    uint32_t offset;
+    bool enabled;
+} RISCVCPUMultiExtConfig;
+
+#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
+    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
+     .enabled = _defval}
+
+static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
-    DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
-    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-    DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true),
-    DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
-    DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
-    DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true),
-    DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
-    DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
-    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
-    DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
-    DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
-    DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
-
-    DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
-    DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
-    DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
-    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
-    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
-
-    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
-    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
-    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
-    DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
-    DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
-    DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
-    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
-    DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
-    DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
-    DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
-    DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
-    DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
-    DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
-    DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
-    DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
-    DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
-    DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
-
-    DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
-    DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
-    DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
-    DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
-
-    DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
-    DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
-
-    DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
-
-    DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
-    DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
-    DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
-    DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
-    DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
-    DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
-    DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
-    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
+    MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
+    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
+    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
+    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
+    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
+    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
+    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
+    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
+    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
+    MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
+
+    MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
+    MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
+    MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
+    MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
+    MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
+
+    MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
+    MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
+    MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
+    MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
+    MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
+    MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
+    MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
+    MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
+    MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
+    MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
+    MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
+    MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
+    MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
+    MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
+    MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
+    MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
+    MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
+
+    MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
+    MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
+    MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
+    MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
+
+    MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
+    MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
+
+    MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
+
+    MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
+    MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
+    MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
+    MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
+    MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
+    MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
+    MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
+    MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static Property riscv_cpu_vendor_exts[] = {
-    DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
-    DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
-    DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
-    DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
-    DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
-    DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
-    DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
-    DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
-    DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
-    DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
-    DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
-    DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
+static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+    MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
+    MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
+    MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
+    MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
+    MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
+    MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
+    MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
+    MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
+    MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
+    MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
+    MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
+    MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
 
 /* These are experimental so mark with 'x-' */
-static Property riscv_cpu_experimental_exts[] = {
+static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
-    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-    DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
-    DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
+    MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
+    MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
+    MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
 
-    DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
-    DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
+    MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
+    MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
 
-    DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
-    DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
-    DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
+    MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
+    MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
+    MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
 
     /* Vector cryptography extensions */
-    DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
-    DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
-    DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
-    DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
-    DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
-    DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
-    DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
-    DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
+    MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
+    MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
+    MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
+    MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
+    MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
+    MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
+    MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
+static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
+
+    g_hash_table_insert(multi_ext_user_opts,
+                        GUINT_TO_POINTER(multi_ext_cfg->offset),
+                        (gpointer)value);
+}
+
+static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_add_multi_ext_prop(Object *cpu_obj,
+                                   RISCVCPUMultiExtConfig *multi_cfg)
+{
+    object_property_add(cpu_obj, multi_cfg->name, "bool",
+                        cpu_get_multi_ext_cfg,
+                        cpu_set_multi_ext_cfg,
+                        NULL, (void *)multi_cfg);
+
+    /*
+     * Set def val directly instead of using
+     * object_property_set_bool() to save the set()
+     * callback hash for user inputs.
+     */
+    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
+                           multi_cfg->enabled);
+}
+
+static void riscv_cpu_add_multiext_prop_array(Object *obj,
+                                              RISCVCPUMultiExtConfig *array)
 {
     g_assert(array);
 
-    for (Property *prop = array; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
+    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+        cpu_add_multi_ext_prop(obj, prop);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 }
 
 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-                                                 Property *array)
+                                                 RISCVCPUMultiExtConfig *array)
 {
     g_assert(array);
 
-    for (Property *prop = array; prop && prop->name; prop++) {
+    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 }
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
  */
 static void riscv_cpu_add_user_properties(Object *obj)
 {
-    DeviceState *dev = DEVICE(obj);
-
 #ifndef CONFIG_USER_ONLY
     riscv_add_satp_mode_properties(obj);
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
 
     riscv_cpu_add_misa_properties(obj);
 
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
+
+    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+        qdev_property_add_static(DEVICE(obj), prop);
+    }
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    Property *prop;
+    RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.

This means that, as is today, all extensions we're setting for the 'max'
CPU will be seen as user set in the future. Let's change set_bool() to
isa_ext_update_enabled() that will just enable/disable the flag on a
certain offset.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        object_property_set_bool(obj, prop->name, true, NULL);
+        isa_ext_update_enabled(cpu, prop->offset, true);
     }
 
     /* set vector version */
     env->vext_ver = VEXT_VERSION_1_00_0;
 
     /* Zfinx is not compatible with F. Disable it */
-    object_property_set_bool(obj, "zfinx", false, NULL);
-    object_property_set_bool(obj, "zdinx", false, NULL);
-    object_property_set_bool(obj, "zhinx", false, NULL);
-    object_property_set_bool(obj, "zhinxmin", false, NULL);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
 
-    object_property_set_bool(obj, "zce", false, NULL);
-    object_property_set_bool(obj, "zcmp", false, NULL);
-    object_property_set_bool(obj, "zcmt", false, NULL);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
 
     if (env->misa_mxl != MXL_RV32) {
-        object_property_set_bool(obj, "zcf", false, NULL);
+        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
     }
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.

This will make us honor user choice instead of overwriting the values.
Users will then be informed whether they're using an incompatible set of
extensions instead of QEMU setting a magic value that works.

The reason why we're not implementing user choice for MISA extensions
right now is because, today, we do not silently change any MISA bit
during realize() time (we do warn when enabling bits if RVG is enabled).
We do that - a lot - with multi-letter extensions though, so we're
handling the most immediate concern first.

After this patch, we'll now error out if the user explicitly set 'zce' to true
and 'zca' to false:

$ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=true,zca=false -nographic
qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension

This didn't happen before because we were enabling 'zca' if 'zce' was enabled
regardless if the user set 'zca' to false.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
     g_assert_not_reached();
 }
 
+static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+{
+    return g_hash_table_contains(multi_ext_user_opts,
+                                 GUINT_TO_POINTER(ext_offset));
+}
+
 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
                                     bool value)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
         return;
     }
 
+    if (cpu_cfg_ext_is_user_set(ext_offset)) {
+        return;
+    }
+
     if (value && env->priv_ver != PRIV_VERSION_LATEST) {
         /* Do not enable it if priv_ver is older than min_version */
         min_version = cpu_cfg_ext_get_min_version(ext_offset);
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
     MISA_CFG(RVG, false),
 };
 
+/*
+ * We do not support user choice tracking for MISA
+ * extensions yet because, so far, we do not silently
+ * change MISA bits during realize() (RVG enables MISA
+ * bits but the user is warned about it).
+ */
 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 {
     int i;
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.

After this patch, disabling ifencei or icsr while enabling RVG will
result in error:

$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false --nographic
qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
           riscv_has_ext(env, RVD) &&
           cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
+            !cpu->cfg.ext_icsr) {
+            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
+            return;
+        }
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
+            !cpu->cfg.ext_ifencei) {
+            error_setg(errp, "RVG requires Zifencei but user set "
+                       "Zifencei to false");
+            return;
+        }
+
         warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
-        cpu->cfg.ext_icsr = true;
-        cpu->cfg.ext_ifencei = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
 
         env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
         env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
-- 
2.41.0

From: "liguang.zhang" <liguang.zhang@hexintek.com>

This patch fixes guest reboot errors when using KVM.

There are two issues when rebooting a guest using KVM
1. When the guest initiates a reboot the host is unable to stop the vcpu
2. When running a SMP guest the qemu monitor system_reset causes a vcpu crash

This can be fixed by clearing the CSR values at reset and syncing the
MPSTATE with the host.

Signed-off-by: liguang.zhang <liguang.zhang@hexintek.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230913091332.17355-1-18622748025@163.com>
[ Changes by AF
 - Fixup commit message
 - Fixup patch style
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm_riscv.h |  1 +
 target/riscv/kvm.c       | 44 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
                           uint64_t aplic_base, uint64_t imsic_base,
                           uint64_t guest_num);
 void riscv_kvm_aplic_request(void *opaque, int irq, int level);
+int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state);
 
 #endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void riscv_kvm_aplic_request(void *opaque, int irq, int level)
     kvm_set_irq(kvm_state, irq, !!level);
 }
 
+static bool cap_has_mp_state;
+
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
 {
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
     return ret;
 }
 
+int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state)
+{
+    if (cap_has_mp_state) {
+        struct kvm_mp_state mp_state = {
+            .mp_state = state
+        };
+
+        int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
+        if (ret) {
+            fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n",
+                    __func__, ret, strerror(-ret));
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
+    if (KVM_PUT_RESET_STATE == level) {
+        RISCVCPU *cpu = RISCV_CPU(cs);
+        if (cs->cpu_index == 0) {
+            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE);
+        } else {
+            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED);
+        }
+        if (ret) {
+            return ret;
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_default_type(MachineState *ms)
 
 int kvm_arch_init(MachineState *ms, KVMState *s)
 {
+    cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
+    int i;
 
     if (!kvm_enabled()) {
         return;
     }
+    for (i = 0; i < 32; i++) {
+        env->gpr[i] = 0;
+    }
     env->pc = cpu->env.kernel_addr;
     env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
     env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
     env->satp = 0;
+    env->mie = 0;
+    env->stvec = 0;
+    env->sscratch = 0;
+    env->sepc = 0;
+    env->scause = 0;
+    env->stval = 0;
+    env->mip = 0;
 }
 
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get cluttered over time. Splitting
acceleration specific code from cpu.c to its own file will help to
declutter the existing code and it will also make it easier to support
KVM/TCG only builds in the future.

We'll start by adding a new subdir called 'tcg' and a new file called
'tcg-cpu.c'. This file will be used to introduce a new accelerator class
for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
code in its file instead of using 'cpu.c' for everything. This design is
inpired by the work Claudio Fontana did in x86 a few years ago in commit
f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
AccelCPUClass").

To avoid moving too much code at once we'll start by adding the new file
and TCG AccelCPUClass declaration. The 'class_init' from the accel class
will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
doing it.

'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
to deal with moving code and files around right now. We'll focus on
decoupling the realize() logic first.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h           |  4 +++
 target/riscv/cpu.c           |  5 +---
 target/riscv/tcg/tcg-cpu.c   | 58 ++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build     |  2 ++
 target/riscv/tcg/meson.build |  2 ++
 5 files changed, 67 insertions(+), 4 deletions(-)
 create mode 100644 target/riscv/tcg/tcg-cpu.c
 create mode 100644 target/riscv/tcg/meson.build

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
 };
 
+/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
+#include "hw/core/tcg-cpu-ops.h"
+extern const struct TCGCPUOps riscv_tcg_ops;
+
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-#include "hw/core/tcg-cpu-ops.h"
-
-static const struct TCGCPUOps riscv_tcg_ops = {
+const struct TCGCPUOps riscv_tcg_ops = {
     .initialize = riscv_translate_init,
     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
     .restore_state_to_opc = riscv_restore_state_to_opc,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
 #endif
     cc->gdb_arch_name = riscv_gdb_arch_name;
     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
-    cc->tcg_ops = &riscv_tcg_ops;
 
     object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
                               cpu_set_mvendorid, NULL, NULL);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * riscv TCG cpu class initialization
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/accel.h"
+#include "hw/core/accel-cpu.h"
+
+static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
+{
+    /*
+     * All cpus use the same set of operations.
+     * riscv_tcg_ops is being imported from cpu.c for now.
+     */
+    cc->tcg_ops = &riscv_tcg_ops;
+}
+
+static void tcg_cpu_class_init(CPUClass *cc)
+{
+    cc->init_accel_cpu = tcg_cpu_init_ops;
+}
+
+static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+    acc->cpu_class_init = tcg_cpu_class_init;
+}
+
+static const TypeInfo tcg_cpu_accel_type_info = {
+    .name = ACCEL_CPU_NAME("tcg"),
+
+    .parent = TYPE_ACCEL_CPU,
+    .class_init = tcg_cpu_accel_class_init,
+    .abstract = true,
+};
+
+static void tcg_cpu_accel_register_types(void)
+{
+    type_register_static(&tcg_cpu_accel_type_info);
+}
+type_init(tcg_cpu_accel_register_types);
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'riscv-qmp-cmds.c',
 ))
 
+subdir('tcg')
+
 target_arch += {'riscv': riscv_ss}
 target_system_arch += {'riscv': riscv_system_ss}
diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/tcg/meson.build
@@ -XXX,XX +XXX,XX @@
+riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
+  'tcg-cpu.c'))
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
realize() path during the common riscv_cpu_realize(), making it a good
choice to start moving TCG exclusive code to tcg-cpu.c.

Rename it to tcg_cpu_realizefn() and assign it as a implementation of
accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
approach with KVM in the near future.

riscv_cpu_validate_set_extensions() is too big and with too many
dependencies to be moved in this same patch. We'll do that next.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230925175709.35696-3-dbarboza@ventanamicro.com>
[ Changes by AF:
 - Renames to fix build failures after rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 128 -----------------------------------
 target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
 2 files changed, 133 insertions(+), 128 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "cpu.h"
 #include "cpu_vendorid.h"
-#include "pmu.h"
 #include "internals.h"
-#include "time_helper.h"
 #include "exec/exec-all.h"
 #include "qapi/error.h"
 #include "qapi/visitor.h"
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
     }
 }
 
-static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
-{
-    CPURISCVState *env = &cpu->env;
-    int priv_version = -1;
-
-    if (cpu->cfg.priv_spec) {
-        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
-            priv_version = PRIV_VERSION_1_12_0;
-        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
-            priv_version = PRIV_VERSION_1_11_0;
-        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
-            priv_version = PRIV_VERSION_1_10_0;
-        } else {
-            error_setg(errp,
-                       "Unsupported privilege spec version '%s'",
-                       cpu->cfg.priv_spec);
-            return;
-        }
-
-        env->priv_ver = priv_version;
-    }
-}
-
 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
     }
 }
 
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
-{
-    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-    CPUClass *cc = CPU_CLASS(mcc);
-    CPURISCVState *env = &cpu->env;
-
-    /* Validate that MISA_MXL is set properly. */
-    switch (env->misa_mxl_max) {
-#ifdef TARGET_RISCV64
-    case MXL_RV64:
-    case MXL_RV128:
-        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
-        break;
-#endif
-    case MXL_RV32:
-        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (env->misa_mxl_max != env->misa_mxl) {
-        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
-        return;
-    }
-}
-
 /*
  * Check consistency between chosen extensions while setting
  * cpu->cfg accordingly.
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
 #endif
 }
 
-static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
-{
-    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
-        error_setg(errp, "H extension requires priv spec 1.12.0");
-        return;
-    }
-}
-
-static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
-{
-    RISCVCPU *cpu = RISCV_CPU(dev);
-    CPURISCVState *env = &cpu->env;
-    Error *local_err = NULL;
-
-    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
-        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
-        return;
-    }
-
-    riscv_cpu_validate_misa_mxl(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    riscv_cpu_validate_priv_spec(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    riscv_cpu_validate_misa_priv(env, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
-        /*
-         * Enhanced PMP should only be available
-         * on harts with PMP support
-         */
-        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
-        return;
-    }
-
-    riscv_cpu_validate_set_extensions(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-#ifndef CONFIG_USER_ONLY
-    CPU(dev)->tcg_cflags |= CF_PCREL;
-
-    if (cpu->cfg.ext_sstc) {
-        riscv_timer_init(cpu);
-    }
-
-    if (cpu->cfg.pmu_num) {
-        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
-            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
-                                          riscv_pmu_timer_cb, cpu);
-        }
-     }
-#endif
-}
-
 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    if (tcg_enabled()) {
-        riscv_cpu_realize_tcg(dev, &local_err);
-        if (local_err != NULL) {
-            error_propagate(errp, local_err);
-            return;
-        }
-    }
-
     riscv_cpu_finalize_features(cpu, &local_err);
     if (local_err != NULL) {
         error_propagate(errp, local_err);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "exec/exec-all.h"
 #include "cpu.h"
+#include "pmu.h"
+#include "time_helper.h"
+#include "qapi/error.h"
 #include "qemu/accel.h"
 #include "hw/core/accel-cpu.h"
 
+
+static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
+{
+    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
+        error_setg(errp, "H extension requires priv spec 1.12.0");
+        return;
+    }
+}
+
+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+{
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+    CPUClass *cc = CPU_CLASS(mcc);
+    CPURISCVState *env = &cpu->env;
+
+    /* Validate that MISA_MXL is set properly. */
+    switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+    case MXL_RV64:
+    case MXL_RV128:
+        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+        break;
+#endif
+    case MXL_RV32:
+        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    if (env->misa_mxl_max != env->misa_mxl) {
+        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
+        return;
+    }
+}
+
+static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
+{
+    CPURISCVState *env = &cpu->env;
+    int priv_version = -1;
+
+    if (cpu->cfg.priv_spec) {
+        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+            priv_version = PRIV_VERSION_1_12_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+            priv_version = PRIV_VERSION_1_11_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+            priv_version = PRIV_VERSION_1_10_0;
+        } else {
+            error_setg(errp,
+                       "Unsupported privilege spec version '%s'",
+                       cpu->cfg.priv_spec);
+            return;
+        }
+
+        env->priv_ver = priv_version;
+    }
+}
+
+/*
+ * We'll get here via the following path:
+ *
+ * riscv_cpu_realize()
+ *   -> cpu_exec_realizefn()
+ *      -> tcg_cpu_realize() (via accel_cpu_common_realize())
+ */
+static bool tcg_cpu_realize(CPUState *cs, Error **errp)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    Error *local_err = NULL;
+
+    if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
+        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
+        return false;
+    }
+
+    riscv_cpu_validate_misa_mxl(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+    riscv_cpu_validate_priv_spec(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+    riscv_cpu_validate_misa_priv(env, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
+        /*
+         * Enhanced PMP should only be available
+         * on harts with PMP support
+         */
+        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+        return false;
+    }
+
+    riscv_cpu_validate_set_extensions(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+#ifndef CONFIG_USER_ONLY
+    CPU(cs)->tcg_cflags |= CF_PCREL;
+
+    if (cpu->cfg.ext_sstc) {
+        riscv_timer_init(cpu);
+    }
+
+    if (cpu->cfg.pmu_num) {
+        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
+            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+                                          riscv_pmu_timer_cb, cpu);
+        }
+     }
+#endif
+
+    return true;
+}
+
 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 
     acc->cpu_class_init = tcg_cpu_class_init;
+    acc->cpu_target_realize = tcg_cpu_realize;
 }
 
 static const TypeInfo tcg_cpu_accel_type_info = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This function is the core of the RISC-V validations for TCG CPUs, and it
has a lot going on.

Functions in cpu.c were made public to allow them to be used by the KVM
accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
hard to move it to another file due to its dependency with isa_edata_arr[]
array, thus make it public and use it as is for now.

riscv_cpu_validate_set_extensions() is kept public because it's used by
csr.c in write_misa().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |   8 +-
 target/riscv/tcg/tcg-cpu.h |  27 +++
 target/riscv/cpu.c         | 361 +------------------------------------
 target/riscv/csr.c         |   1 +
 target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++
 5 files changed, 397 insertions(+), 357 deletions(-)
 create mode 100644 target/riscv/tcg/tcg-cpu.h

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         bool probe, uintptr_t retaddr);
 char *riscv_isa_string(RISCVCPU *cpu);
 void riscv_cpu_list(void);
-void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 
 #define cpu_list riscv_cpu_list
 #define cpu_mmu_index riscv_cpu_mmu_index
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
 #include "hw/core/tcg-cpu-ops.h"
 extern const struct TCGCPUOps riscv_tcg_ops;
 
+/* used by tcg/tcg-cpu.c*/
+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
+int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
+
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * riscv TCG cpu class initialization
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_TCG_CPU_H
+#define RISCV_TCG_CPU_H
+
+#include "cpu.h"
+
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+
+#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
 /* Hash that stores user set extensions */
 static GHashTable *multi_ext_user_opts;
 
-static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
 
     return *ext_enabled;
 }
 
-static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
-                                   bool en)
+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
 
     *ext_enabled = en;
 }
 
-static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 {
     int i;
 
@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
     g_assert_not_reached();
 }
 
-static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
 {
     return g_hash_table_contains(multi_ext_user_opts,
                                  GUINT_TO_POINTER(ext_offset));
 }
 
-static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
-                                    bool value)
-{
-    CPURISCVState *env = &cpu->env;
-    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
-    int min_version;
-
-    if (prev_val == value) {
-        return;
-    }
-
-    if (cpu_cfg_ext_is_user_set(ext_offset)) {
-        return;
-    }
-
-    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
-        /* Do not enable it if priv_ver is older than min_version */
-        min_version = cpu_cfg_ext_get_min_version(ext_offset);
-        if (env->priv_ver < min_version) {
-            return;
-        }
-    }
-
-    isa_ext_update_enabled(cpu, ext_offset, value);
-}
-
 const char * const riscv_int_regnames[] = {
     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
     }
 }
 
-static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
-                                 Error **errp)
-{
-    if (!is_power_of_2(cfg->vlen)) {
-        error_setg(errp, "Vector extension VLEN must be power of 2");
-        return;
-    }
-    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
-        error_setg(errp,
-                   "Vector extension implementation only supports VLEN "
-                   "in the range [128, %d]", RV_VLEN_MAX);
-        return;
-    }
-    if (!is_power_of_2(cfg->elen)) {
-        error_setg(errp, "Vector extension ELEN must be power of 2");
-        return;
-    }
-    if (cfg->elen > 64 || cfg->elen < 8) {
-        error_setg(errp,
-                   "Vector extension implementation only supports ELEN "
-                   "in the range [8, 64]");
-        return;
-    }
-    if (cfg->vext_spec) {
-        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
-            env->vext_ver = VEXT_VERSION_1_00_0;
-        } else {
-            error_setg(errp, "Unsupported vector spec version '%s'",
-                       cfg->vext_spec);
-            return;
-        }
-    } else if (env->vext_ver == 0) {
-        qemu_log("vector version is not specified, "
-                 "use the default value v1.0\n");
-
-        env->vext_ver = VEXT_VERSION_1_00_0;
-    }
-}
-
-static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
     int i;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
     }
 }
 
-/*
- * Check consistency between chosen extensions while setting
- * cpu->cfg accordingly.
- */
-void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-{
-    CPURISCVState *env = &cpu->env;
-    Error *local_err = NULL;
-
-    /* Do some ISA extension error checking */
-    if (riscv_has_ext(env, RVG) &&
-        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
-          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
-          riscv_has_ext(env, RVD) &&
-          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
-
-        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
-            !cpu->cfg.ext_icsr) {
-            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
-            return;
-        }
-
-        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
-            !cpu->cfg.ext_ifencei) {
-            error_setg(errp, "RVG requires Zifencei but user set "
-                       "Zifencei to false");
-            return;
-        }
-
-        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
-
-        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
-        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
-    }
-
-    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
-        error_setg(errp,
-                   "I and E extensions are incompatible");
-        return;
-    }
-
-    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
-        error_setg(errp,
-                   "Either I or E extension must be set");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
-        error_setg(errp,
-                   "Setting S extension without U extension is illegal");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
-        error_setg(errp,
-                   "H depends on an I base integer ISA with 32 x registers");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
-        error_setg(errp, "H extension implicitly requires S-mode");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
-        error_setg(errp, "F extension requires Zicsr");
-        return;
-    }
-
-    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
-        error_setg(errp, "Zawrs extension requires A extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zfa extension requires F extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfh) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
-    }
-
-    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zfbfmin extension depends on F extension");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "D extension requires F extension");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVV)) {
-        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
-        if (local_err != NULL) {
-            error_propagate(errp, local_err);
-            return;
-        }
-
-        /* The V vector extension depends on the Zve64d extension */
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
-    }
-
-    /* The Zve64d extension depends on the Zve64f extension */
-    if (cpu->cfg.ext_zve64d) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
-    }
-
-    /* The Zve64f extension depends on the Zve32f extension */
-    if (cpu->cfg.ext_zve64f) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
-    }
-
-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-        error_setg(errp, "Zve64d/V extensions require D extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfh) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
-    }
-
-    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
-        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
-        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
-        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
-        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
-        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
-        return;
-    }
-
-    /* Set the ISA extensions, checks should have happened above */
-    if (cpu->cfg.ext_zhinx) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-    }
-
-    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
-        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfinx) {
-        if (!cpu->cfg.ext_icsr) {
-            error_setg(errp, "Zfinx extension requires Zicsr");
-            return;
-        }
-        if (riscv_has_ext(env, RVF)) {
-            error_setg(errp,
-                       "Zfinx cannot be supported together with F extension");
-            return;
-        }
-    }
-
-    if (cpu->cfg.ext_zce) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
-        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
-        }
-    }
-
-    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
-    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
-        }
-        if (riscv_has_ext(env, RVD)) {
-            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
-        }
-    }
-
-    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
-        error_setg(errp, "Zcf extension is only relevant to RV32");
-        return;
-    }
-
-    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
-        error_setg(errp, "Zcf extension requires F extension");
-        return;
-    }
-
-    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
-        error_setg(errp, "Zcd extension requires D extension");
-        return;
-    }
-
-    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
-         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
-        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
-                         "extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
-        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
-                         "Zcd extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
-        error_setg(errp, "Zcmt extension requires Zicsr extension");
-        return;
-    }
-
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
-    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
-         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
-        !cpu->cfg.ext_zve32f) {
-        error_setg(errp,
-                   "Vector crypto extensions require V or Zve* extensions");
-        return;
-    }
-
-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
-        error_setg(
-            errp,
-            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
-        return;
-    }
-
-    if (cpu->cfg.ext_zk) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
-    }
-
-    if (cpu->cfg.ext_zkn) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
-    }
-
-    if (cpu->cfg.ext_zks) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
-    }
-
-    /*
-     * Disable isa extensions based on priv spec after we
-     * validated and set everything we need.
-     */
-    riscv_cpu_disable_priv_spec_isa_exts(cpu);
-}
-
 #ifndef CONFIG_USER_ONLY
 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
 {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/timer.h"
 #include "cpu.h"
+#include "tcg/tcg-cpu.h"
 #include "pmu.h"
 #include "time_helper.h"
 #include "exec/exec-all.h"
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "exec/exec-all.h"
+#include "tcg-cpu.h"
 #include "cpu.h"
 #include "pmu.h"
 #include "time_helper.h"
 #include "qapi/error.h"
 #include "qemu/accel.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
 #include "hw/core/accel-cpu.h"
 
 
+static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
+                                    bool value)
+{
+    CPURISCVState *env = &cpu->env;
+    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
+    int min_version;
+
+    if (prev_val == value) {
+        return;
+    }
+
+    if (cpu_cfg_ext_is_user_set(ext_offset)) {
+        return;
+    }
+
+    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
+        /* Do not enable it if priv_ver is older than min_version */
+        min_version = cpu_cfg_ext_get_min_version(ext_offset);
+        if (env->priv_ver < min_version) {
+            return;
+        }
+    }
+
+    isa_ext_update_enabled(cpu, ext_offset, value);
+}
+
 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
 {
     if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
     }
 }
 
+static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+                                 Error **errp)
+{
+    if (!is_power_of_2(cfg->vlen)) {
+        error_setg(errp, "Vector extension VLEN must be power of 2");
+        return;
+    }
+
+    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
+        error_setg(errp,
+                   "Vector extension implementation only supports VLEN "
+                   "in the range [128, %d]", RV_VLEN_MAX);
+        return;
+    }
+
+    if (!is_power_of_2(cfg->elen)) {
+        error_setg(errp, "Vector extension ELEN must be power of 2");
+        return;
+    }
+
+    if (cfg->elen > 64 || cfg->elen < 8) {
+        error_setg(errp,
+                   "Vector extension implementation only supports ELEN "
+                   "in the range [8, 64]");
+        return;
+    }
+
+    if (cfg->vext_spec) {
+        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
+            env->vext_ver = VEXT_VERSION_1_00_0;
+        } else {
+            error_setg(errp, "Unsupported vector spec version '%s'",
+                       cfg->vext_spec);
+            return;
+        }
+    } else if (env->vext_ver == 0) {
+        qemu_log("vector version is not specified, "
+                 "use the default value v1.0\n");
+
+        env->vext_ver = VEXT_VERSION_1_00_0;
+    }
+}
+
+/*
+ * Check consistency between chosen extensions while setting
+ * cpu->cfg accordingly.
+ */
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+{
+    CPURISCVState *env = &cpu->env;
+    Error *local_err = NULL;
+
+    /* Do some ISA extension error checking */
+    if (riscv_has_ext(env, RVG) &&
+        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
+          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
+          riscv_has_ext(env, RVD) &&
+          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
+            !cpu->cfg.ext_icsr) {
+            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
+            return;
+        }
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
+            !cpu->cfg.ext_ifencei) {
+            error_setg(errp, "RVG requires Zifencei but user set "
+                       "Zifencei to false");
+            return;
+        }
+
+        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
+
+        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
+        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
+    }
+
+    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
+        error_setg(errp,
+                   "I and E extensions are incompatible");
+        return;
+    }
+
+    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
+        error_setg(errp,
+                   "Either I or E extension must be set");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
+        error_setg(errp,
+                   "Setting S extension without U extension is illegal");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
+        error_setg(errp,
+                   "H depends on an I base integer ISA with 32 x registers");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
+        error_setg(errp, "H extension implicitly requires S-mode");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
+        error_setg(errp, "F extension requires Zicsr");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
+        error_setg(errp, "Zawrs extension requires A extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zfa extension requires F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfh) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
+    }
+
+    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zfbfmin extension depends on F extension");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "D extension requires F extension");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVV)) {
+        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
+            return;
+        }
+
+        /* The V vector extension depends on the Zve64d extension */
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
+    }
+
+    /* The Zve64d extension depends on the Zve64f extension */
+    if (cpu->cfg.ext_zve64d) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
+    }
+
+    /* The Zve64f extension depends on the Zve32f extension */
+    if (cpu->cfg.ext_zve64f) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
+    }
+
+    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
+        error_setg(errp, "Zve64d/V extensions require D extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfh) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
+    }
+
+    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
+        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
+        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
+        return;
+    }
+
+    /* Set the ISA extensions, checks should have happened above */
+    if (cpu->cfg.ext_zhinx) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+    }
+
+    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
+        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfinx) {
+        if (!cpu->cfg.ext_icsr) {
+            error_setg(errp, "Zfinx extension requires Zicsr");
+            return;
+        }
+        if (riscv_has_ext(env, RVF)) {
+            error_setg(errp,
+                       "Zfinx cannot be supported together with F extension");
+            return;
+        }
+    }
+
+    if (cpu->cfg.ext_zce) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
+        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+        }
+    }
+
+    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
+    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+        }
+        if (riscv_has_ext(env, RVD)) {
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
+        }
+    }
+
+    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+        error_setg(errp, "Zcf extension is only relevant to RV32");
+        return;
+    }
+
+    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
+        error_setg(errp, "Zcf extension requires F extension");
+        return;
+    }
+
+    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
+        error_setg(errp, "Zcd extension requires D extension");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
+         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
+        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
+                         "extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
+        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
+                         "Zcd extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
+        error_setg(errp, "Zcmt extension requires Zicsr extension");
+        return;
+    }
+
+    /*
+     * In principle Zve*x would also suffice here, were they supported
+     * in qemu
+     */
+    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
+         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
+        !cpu->cfg.ext_zve32f) {
+        error_setg(errp,
+                   "Vector crypto extensions require V or Zve* extensions");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
+        error_setg(
+            errp,
+            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
+        return;
+    }
+
+    if (cpu->cfg.ext_zk) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
+    }
+
+    if (cpu->cfg.ext_zkn) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
+    }
+
+    if (cpu->cfg.ext_zks) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
+    }
+
+    /*
+     * Disable isa extensions based on priv spec after we
+     * validated and set everything we need.
+     */
+    riscv_cpu_disable_priv_spec_isa_exts(cpu);
+}
+
 /*
  * We'll get here via the following path:
  *
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  4 ---
 target/riscv/cpu.c         | 58 ------------------------------------
 target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++-
 3 files changed, 59 insertions(+), 63 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
 };
 
-/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
-#include "hw/core/tcg-cpu-ops.h"
-extern const struct TCGCPUOps riscv_tcg_ops;
-
 /* used by tcg/tcg-cpu.c*/
 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
 bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
     return env->pc;
 }
 
-static void riscv_cpu_synchronize_from_tb(CPUState *cs,
-                                          const TranslationBlock *tb)
-{
-    if (!(tb_cflags(tb) & CF_PCREL)) {
-        RISCVCPU *cpu = RISCV_CPU(cs);
-        CPURISCVState *env = &cpu->env;
-        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-
-        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
-
-        if (xl == MXL_RV32) {
-            env->pc = (int32_t) tb->pc;
-        } else {
-            env->pc = tb->pc;
-        }
-    }
-}
-
 static bool riscv_cpu_has_work(CPUState *cs)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
 #endif
 }
 
-static void riscv_restore_state_to_opc(CPUState *cs,
-                                       const TranslationBlock *tb,
-                                       const uint64_t *data)
-{
-    RISCVCPU *cpu = RISCV_CPU(cs);
-    CPURISCVState *env = &cpu->env;
-    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-    target_ulong pc;
-
-    if (tb_cflags(tb) & CF_PCREL) {
-        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
-    } else {
-        pc = data[0];
-    }
-
-    if (xl == MXL_RV32) {
-        env->pc = (int32_t)pc;
-    } else {
-        env->pc = pc;
-    }
-    env->bins = data[1];
-}
-
 static void riscv_cpu_reset_hold(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-const struct TCGCPUOps riscv_tcg_ops = {
-    .initialize = riscv_translate_init,
-    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
-    .restore_state_to_opc = riscv_restore_state_to_opc,
-
-#ifndef CONFIG_USER_ONLY
-    .tlb_fill = riscv_cpu_tlb_fill,
-    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
-    .do_interrupt = riscv_cpu_do_interrupt,
-    .do_transaction_failed = riscv_cpu_do_transaction_failed,
-    .do_unaligned_access = riscv_cpu_do_unaligned_access,
-    .debug_excp_handler = riscv_cpu_debug_excp_handler,
-    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
-    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
-#endif /* !CONFIG_USER_ONLY */
-};
-
 static bool riscv_cpu_is_dynamic(Object *cpu_obj)
 {
     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/error-report.h"
 #include "qemu/log.h"
 #include "hw/core/accel-cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "tcg/tcg.h"
 
+static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+                                          const TranslationBlock *tb)
+{
+    if (!(tb_cflags(tb) & CF_PCREL)) {
+        RISCVCPU *cpu = RISCV_CPU(cs);
+        CPURISCVState *env = &cpu->env;
+        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+
+        if (xl == MXL_RV32) {
+            env->pc = (int32_t) tb->pc;
+        } else {
+            env->pc = tb->pc;
+        }
+    }
+}
+
+static void riscv_restore_state_to_opc(CPUState *cs,
+                                       const TranslationBlock *tb,
+                                       const uint64_t *data)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+    target_ulong pc;
+
+    if (tb_cflags(tb) & CF_PCREL) {
+        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+    } else {
+        pc = data[0];
+    }
+
+    if (xl == MXL_RV32) {
+        env->pc = (int32_t)pc;
+    } else {
+        env->pc = pc;
+    }
+    env->bins = data[1];
+}
+
+static const struct TCGCPUOps riscv_tcg_ops = {
+    .initialize = riscv_translate_init,
+    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+    .restore_state_to_opc = riscv_restore_state_to_opc,
+
+#ifndef CONFIG_USER_ONLY
+    .tlb_fill = riscv_cpu_tlb_fill,
+    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+    .do_interrupt = riscv_cpu_do_interrupt,
+    .do_transaction_failed = riscv_cpu_do_transaction_failed,
+    .do_unaligned_access = riscv_cpu_do_unaligned_access,
+    .debug_excp_handler = riscv_cpu_debug_excp_handler,
+    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
 
 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
                                     bool value)
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 {
     /*
      * All cpus use the same set of operations.
-     * riscv_tcg_ops is being imported from cpu.c for now.
      */
     cc->tcg_ops = &riscv_tcg_ops;
 }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:

riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()

In the near future riscv_cpu_post_init() will call the init() function
of the current accelerator, providing a hook for KVM and TCG accel
classes to change the init() process of the CPU.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
     mlx = MXL_RV32;
 #endif
     set_misa(env, mlx, 0);
-    riscv_cpu_add_user_properties(obj);
-    riscv_init_max_cpu_extensions(obj);
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV64, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV128, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV32, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_host_cpu_init(Object *obj)
 #elif defined(TARGET_RISCV64)
     set_misa(env, MXL_RV64, 0);
 #endif
-    riscv_cpu_add_user_properties(obj);
 }
 #endif /* CONFIG_KVM */
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 }
 #endif /* CONFIG_USER_ONLY */
 
+static bool riscv_cpu_is_dynamic(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+    if (kvm_enabled() &&
+        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
+        return true;
+    }
+
+    return riscv_cpu_is_dynamic(cpu_obj);
+}
+
+static void riscv_cpu_post_init(Object *obj)
+{
+    if (riscv_cpu_has_user_properties(obj)) {
+        riscv_cpu_add_user_properties(obj);
+    }
+
+    if (riscv_cpu_has_max_extensions(obj)) {
+        riscv_init_max_cpu_extensions(obj);
+    }
+}
+
 static void riscv_cpu_init(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-static bool riscv_cpu_is_dynamic(Object *cpu_obj)
-{
-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-}
-
 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
                               void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .instance_size = sizeof(RISCVCPU),
         .instance_align = __alignof(RISCVCPU),
         .instance_init = riscv_cpu_init,
+        .instance_post_init = riscv_cpu_post_init,
         .abstract = true,
         .class_size = sizeof(RISCVCPUClass),
         .class_init = riscv_cpu_class_init,
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This CPU only exists if we're compiling with KVM so move it to the kvm
specific file.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 15 ---------------
 target/riscv/kvm.c | 21 +++++++++++++++++++++
 2 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
 }
 #endif
 
-#if defined(CONFIG_KVM)
-static void riscv_host_cpu_init(Object *obj)
-{
-    CPURISCVState *env = &RISCV_CPU(obj)->env;
-#if defined(TARGET_RISCV32)
-    set_misa(env, MXL_RV32, 0);
-#elif defined(TARGET_RISCV64)
-    set_misa(env, MXL_RV64, 0);
-#endif
-}
-#endif /* CONFIG_KVM */
-
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
     },
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
-#if defined(CONFIG_KVM)
-    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
-#endif
 #if defined(TARGET_RISCV32)
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,   rv32_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
 
     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 }
+
+static void riscv_host_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+
+#if defined(TARGET_RISCV32)
+    env->misa_mxl_max = env->misa_mxl = MXL_RV32;
+#elif defined(TARGET_RISCV64)
+    env->misa_mxl_max = env->misa_mxl = MXL_RV64;
+#endif
+}
+
+static const TypeInfo riscv_kvm_cpu_type_infos[] = {
+    {
+        .name = TYPE_RISCV_CPU_HOST,
+        .parent = TYPE_RISCV_CPU,
+        .instance_init = riscv_host_cpu_init,
+    }
+};
+
+DEFINE_TYPES(riscv_kvm_cpu_type_infos)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now because they should not be modified at
runtime.

Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are changed via
qdev_property_add_static().

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .enabled = _defval}
 
-static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
     MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 };
 
 /* These are experimental so mark with 'x-' */
-static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
     MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
     MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 }
 
 static void cpu_add_multi_ext_prop(Object *cpu_obj,
-                                   RISCVCPUMultiExtConfig *multi_cfg)
+                                   const RISCVCPUMultiExtConfig *multi_cfg)
 {
     object_property_add(cpu_obj, multi_cfg->name, "bool",
                         cpu_get_multi_ext_cfg,
@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
 }
 
 static void riscv_cpu_add_multiext_prop_array(Object *obj,
-                                              RISCVCPUMultiExtConfig *array)
+                                        const RISCVCPUMultiExtConfig *array)
 {
+    const RISCVCPUMultiExtConfig *prop;
+
     g_assert(array);
 
-    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+    for (prop = array; prop && prop->name; prop++) {
         cpu_add_multi_ext_prop(obj, prop);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 }
 
 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-                                                 RISCVCPUMultiExtConfig *array)
+                                        const RISCVCPUMultiExtConfig *array)
 {
+    const RISCVCPUMultiExtConfig *prop;
+
     g_assert(array);
 
-    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+    for (prop = array; prop && prop->name; prop++) {
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    RISCVCPUMultiExtConfig *prop;
+    const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll introduce the KVM accelerator class with a 'cpu_instance_init'
implementation that is going to be invoked during the common
riscv_cpu_post_init() (via accel_cpu_instance_init()). This
instance_init will execute KVM exclusive code that TCG doesn't care
about, such as adding KVM specific properties, initing registers using a
KVM scratch CPU and so on.

The core of the forementioned cpu_instance_init impl is the current
riscv_cpu_add_kvm_properties() that is being used by the common code via
riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
will all the relevant artifacts, exporting and renaming it to
kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.

To make this work we'll need to export riscv_cpu_extensions,
riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
well. The TCG accelerator will also need to access those in the near
future so this export will benefit us in the long run.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       | 14 +++++++
 target/riscv/kvm_riscv.h |  3 --
 target/riscv/cpu.c       | 85 +++-------------------------------------
 target/riscv/kvm.c       | 68 +++++++++++++++++++++++++++++++-
 4 files changed, 86 insertions(+), 84 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/core/cpu.h"
 #include "hw/registerfields.h"
+#include "hw/qdev-properties.h"
 #include "exec/cpu-defs.h"
 #include "qemu/cpu-float.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
 
+typedef struct RISCVCPUMultiExtConfig {
+    const char *name;
+    uint32_t offset;
+    bool enabled;
+} RISCVCPUMultiExtConfig;
+
+extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern Property riscv_cpu_options[];
+
+void riscv_cpu_add_misa_properties(Object *cpu_obj);
+
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #ifndef QEMU_KVM_RISCV_H
 #define QEMU_KVM_RISCV_H
 
-/* Temporarily implemented in cpu.c */
 void kvm_riscv_cpu_add_kvm_properties(Object *obj);
-
-void kvm_riscv_init_user_properties(Object *cpu_obj);
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
  * change MISA bits during realize() (RVG enables MISA
  * bits but the user is warned about it).
  */
-static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+void riscv_cpu_add_misa_properties(Object *cpu_obj)
 {
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
     }
 }
 
-typedef struct RISCVCPUMultiExtConfig {
-    const char *name;
-    uint32_t offset;
-    bool enabled;
-} RISCVCPUMultiExtConfig;
-
 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .enabled = _defval}
 
-static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
     MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 };
 
 /* These are experimental so mark with 'x-' */
-static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
     MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
     MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static Property riscv_cpu_options[] = {
+Property riscv_cpu_options[] = {
     DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
 
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
     }
 }
 
-#ifdef CONFIG_KVM
-static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
-                                    const char *name,
-                                    void *opaque, Error **errp)
-{
-    const char *propname = opaque;
-    bool value;
-
-    if (!visit_type_bool(v, name, &value, errp)) {
-        return;
-    }
-
-    if (value) {
-        error_setg(errp, "extension %s is not available with KVM",
-                   propname);
-    }
-}
-
-static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
-{
-    /* Check if KVM created the property already */
-    if (object_property_find(obj, prop_name)) {
-        return;
-    }
-
-    /*
-     * Set the default to disabled for every extension
-     * unknown to KVM and error out if the user attempts
-     * to enable any of them.
-     */
-    object_property_add(obj, prop_name, "bool",
-                        NULL, cpu_set_cfg_unavailable,
-                        NULL, (void *)prop_name);
-}
-
-static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-                                        const RISCVCPUMultiExtConfig *array)
-{
-    const RISCVCPUMultiExtConfig *prop;
-
-    g_assert(array);
-
-    for (prop = array; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
-}
-
-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-{
-    Property *prop;
-    DeviceState *dev = DEVICE(obj);
-
-    kvm_riscv_init_user_properties(obj);
-    riscv_cpu_add_misa_properties(obj);
-
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
-
-    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
-        /* Check if KVM created the property already */
-        if (object_property_find(obj, prop->name)) {
-            continue;
-        }
-        qdev_property_add_static(dev, prop);
-    }
-}
-#endif
-
 /*
  * Add CPU properties with user-facing flags.
  *
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
     }
 }
 
+static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
+                                    const char *name,
+                                    void *opaque, Error **errp)
+{
+    const char *propname = opaque;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    if (value) {
+        error_setg(errp, "extension %s is not available with KVM",
+                   propname);
+    }
+}
+
+static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+{
+    /* Check if KVM created the property already */
+    if (object_property_find(obj, prop_name)) {
+        return;
+    }
+
+    /*
+     * Set the default to disabled for every extension
+     * unknown to KVM and error out if the user attempts
+     * to enable any of them.
+     */
+    object_property_add(obj, prop_name, "bool",
+                        NULL, cpu_set_cfg_unavailable,
+                        NULL, (void *)prop_name);
+}
+
+static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
+                                        const RISCVCPUMultiExtConfig *array)
+{
+    const RISCVCPUMultiExtConfig *prop;
+
+    g_assert(array);
+
+    for (prop = array; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+}
+
 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
 {
     int i;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     }
 }
 
-void kvm_riscv_init_user_properties(Object *cpu_obj)
+static void riscv_init_user_properties(Object *cpu_obj)
 {
     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
     KVMScratchCPU kvmcpu;
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 }
 
+void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+{
+    DeviceState *dev = DEVICE(obj);
+
+    riscv_init_user_properties(obj);
+    riscv_cpu_add_misa_properties(obj);
+
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+
+    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+        /* Check if KVM created the property already */
+        if (object_property_find(obj, prop->name)) {
+            continue;
+        }
+        qdev_property_add_static(dev, prop);
+    }
+}
+
 static void riscv_host_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This function is used for both accelerators. Make it public, and call it
from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
split KVM specific code for the KVM accelerator class in the next patch.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 extern Property riscv_cpu_options[];
 
 void riscv_cpu_add_misa_properties(Object *cpu_obj);
+void riscv_add_satp_mode_properties(Object *obj);
 
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
     satp_map->init |= 1 << satp;
 }
 
-static void riscv_add_satp_mode_properties(Object *obj)
+void riscv_add_satp_mode_properties(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
 static void riscv_cpu_add_user_properties(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
-    riscv_add_satp_mode_properties(obj);
-
     if (kvm_enabled()) {
         kvm_riscv_cpu_add_kvm_properties(obj);
         return;
     }
+    riscv_add_satp_mode_properties(obj);
 #endif
 
     riscv_cpu_add_misa_properties(obj);
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     DeviceState *dev = DEVICE(obj);
 
     riscv_init_user_properties(obj);
+    riscv_add_satp_mode_properties(obj);
     riscv_cpu_add_misa_properties(obj);
 
     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
in non-KVM builds.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm-stub.c  | 30 ------------------------------
 target/riscv/meson.build |  2 +-
 2 files changed, 1 insertion(+), 31 deletions(-)
 delete mode 100644 target/riscv/kvm-stub.c

diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/kvm-stub.c
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-/*
- * QEMU KVM RISC-V specific function stubs
- *
- * Copyright (c) 2020 Huawei Technologies Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include "qemu/osdep.h"
-#include "cpu.h"
-#include "kvm_riscv.h"
-
-void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-{
-    abort();
-}
-
-void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
-{
-    abort();
-}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'zce_helper.c',
   'vcrypto_helper.c'
 ))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_system_ss = ss.source_set()
 riscv_system_ss.add(files(
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add a KVM accelerator class like we did with TCG. The difference is
that, at least for now, we won't be using a realize() implementation for
this accelerator.

We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
through the 'cpu_instance_init' impl of the current acceleration (if
available) and execute it. The end result is that the KVM initial setup,
i.e. starting registers and adding its specific properties, will be done
via this hook.

Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
calling riscv_cpu_add_user_properties() when running KVM. We'll remove
this condition when the TCG accel class get its own 'cpu_instance_init'
implementation.

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #ifndef QEMU_KVM_RISCV_H
 #define QEMU_KVM_RISCV_H
 
-void kvm_riscv_cpu_add_kvm_properties(Object *obj);
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_user_properties(Object *cpu_obj)
 
 static void riscv_cpu_post_init(Object *obj)
 {
-    if (riscv_cpu_has_user_properties(obj)) {
+    accel_cpu_instance_init(CPU(obj));
+
+    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
         riscv_cpu_add_user_properties(obj);
     }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
 static void riscv_cpu_add_user_properties(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
-    if (kvm_enabled()) {
-        kvm_riscv_cpu_add_kvm_properties(obj);
-        return;
-    }
     riscv_add_satp_mode_properties(obj);
 #endif
 
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm_int.h"
 #include "cpu.h"
 #include "trace.h"
+#include "hw/core/accel-cpu.h"
 #include "hw/pci/pci.h"
 #include "exec/memattrs.h"
 #include "exec/address-spaces.h"
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 }
 
-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+static void kvm_cpu_instance_init(CPUState *cs)
 {
+    Object *obj = OBJECT(RISCV_CPU(cs));
     DeviceState *dev = DEVICE(obj);
 
     riscv_init_user_properties(obj);
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 
     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
-        /* Check if KVM created the property already */
+        /* Check if we have a specific KVM handler for the option */
         if (object_property_find(obj, prop->name)) {
             continue;
         }
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     }
 }
 
+static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+    acc->cpu_instance_init = kvm_cpu_instance_init;
+}
+
+static const TypeInfo kvm_cpu_accel_type_info = {
+    .name = ACCEL_CPU_NAME("kvm"),
+
+    .parent = TYPE_ACCEL_CPU,
+    .class_init = kvm_cpu_accel_class_init,
+    .abstract = true,
+};
+static void kvm_cpu_accel_register_types(void)
+{
+    type_register_static(&kvm_cpu_accel_type_info);
+}
+type_init(kvm_cpu_accel_register_types);
+
 static void riscv_host_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.

Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/{ => kvm}/kvm_riscv.h    | 0
 hw/intc/riscv_aplic.c                 | 2 +-
 hw/riscv/virt.c                       | 2 +-
 target/riscv/cpu.c                    | 2 +-
 target/riscv/{kvm.c => kvm/kvm-cpu.c} | 0
 target/riscv/kvm/meson.build          | 1 +
 target/riscv/meson.build              | 2 +-
 7 files changed, 5 insertions(+), 4 deletions(-)
 rename target/riscv/{ => kvm}/kvm_riscv.h (100%)
 rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (100%)
 create mode 100644 target/riscv/kvm/meson.build

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
similarity index 100%
rename from target/riscv/kvm_riscv.h
rename to target/riscv/kvm/kvm_riscv.h
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
 #include "migration/vmstate.h"
 
 #define APLIC_MAX_IDC                  (1UL << 14)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
 #include "hw/intc/riscv_aclint.h"
 #include "hw/intc/riscv_aplic.h"
 #include "hw/intc/riscv_imsic.h"
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "fpu/softfloat-helpers.h"
 #include "sysemu/kvm.h"
 #include "sysemu/tcg.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
 #include "tcg/tcg.h"
 
 /* RISC-V CPU definitions */
diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c
similarity index 100%
rename from target/riscv/kvm.c
rename to target/riscv/kvm/kvm-cpu.c
diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm/meson.build
@@ -0,0 +1 @@
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'zce_helper.c',
   'vcrypto_helper.c'
 ))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_system_ss = ss.source_set()
 riscv_system_ss.add(files(
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
 ))
 
 subdir('tcg')
+subdir('kvm')
 
 target_arch += {'riscv': riscv_ss}
 target_system_arch += {'riscv': riscv_system_ss}
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

riscv_cpu_add_misa_properties() is being used to fill the missing KVM
MISA properties but it is a TCG helper that was adapted to do so. We'll
move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
the remaining MISA properties on its own.

Do not use riscv_cpu_add_misa_properties(). Let's create a new array
with all available MISA bits we support that can be read by KVM. The
array is zero terminate to allow us to iterate through it without
knowing its size.

Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
MISA properties as usual and then use this array to add any missing MISA
properties with the riscv_cpu_add_kvm_unavail_prop() helper.

Note that we're creating misa_bits[], and not using the existing
'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
related functions and it doesn't have all MISA bits we support. Commit
0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
full context.

While we're at it, move both satp and the multi-letter extension
properties to kvm_riscv_add_cpu_user_properties() as well.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 ++-
 target/riscv/cpu.c         |  2 ++
 target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++--------
 3 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define RV(x) ((target_ulong)1 << (x - 'A'))
 
 /*
- * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[]
+ * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
  * when adding new MISA bits here.
  */
 #define RVI RV('I')
@@ -XXX,XX +XXX,XX @@
 #define RVJ RV('J')
 #define RVG RV('G')
 
+extern const uint32_t misa_bits[];
 const char *riscv_get_misa_ext_name(uint32_t bit);
 const char *riscv_get_misa_ext_description(uint32_t bit);
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 
 /* RISC-V CPU definitions */
 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
+const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
+                              RVC, RVS, RVU, RVH, RVJ, RVG, 0};
 
 struct isa_ext_data {
     const char *name;
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
 {
     int i;
 
+    riscv_add_satp_mode_properties(cpu_obj);
+
     for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) {
         KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i];
         int bit = misa_cfg->offset;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
                                         misa_cfg->description);
     }
 
+    for (i = 0; misa_bits[i] != 0; i++) {
+        const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]);
+        riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name);
+    }
+
     for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
         KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i];
 
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
     object_property_add(cpu_obj, "cboz_blocksize", "uint16",
                         NULL, kvm_cpu_set_cbomz_blksize,
                         NULL, &kvm_cboz_blocksize);
+
+    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions);
+    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts);
 }
 
 static int kvm_riscv_get_regs_core(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     }
 }
 
-static void riscv_init_user_properties(Object *cpu_obj)
+static void riscv_init_kvm_registers(Object *cpu_obj)
 {
     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
     KVMScratchCPU kvmcpu;
@@ -XXX,XX +XXX,XX @@ static void riscv_init_user_properties(Object *cpu_obj)
         return;
     }
 
-    kvm_riscv_add_cpu_user_properties(cpu_obj);
     kvm_riscv_init_machine_ids(cpu, &kvmcpu);
     kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
     kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_instance_init(CPUState *cs)
     Object *obj = OBJECT(RISCV_CPU(cs));
     DeviceState *dev = DEVICE(obj);
 
-    riscv_init_user_properties(obj);
-    riscv_add_satp_mode_properties(obj);
-    riscv_cpu_add_misa_properties(obj);
+    riscv_init_kvm_registers(obj);
 
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+    kvm_riscv_add_cpu_user_properties(obj);
 
     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if we have a specific KVM handler for the option */
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
patch and set_misa() needs to be usable from there.

Rename it to riscv_cpu_set_misa() and make it public.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  1 +
 target/riscv/cpu.c | 34 ++++++++++++++++++----------------
 2 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
 bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
 
 typedef struct RISCVCPUMultiExtConfig {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
     }
 }
 
-static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 {
     env->misa_mxl_max = env->misa_mxl = mxl;
     env->misa_ext_mask = env->misa_ext = ext;
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
 #if defined(TARGET_RISCV32)
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #elif defined(TARGET_RISCV64)
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #endif
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
 #ifdef TARGET_RISCV32
     mlx = MXL_RV32;
 #endif
-    set_misa(env, mlx, 0);
+    riscv_cpu_set_misa(env, mlx, 0);
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, MXL_RV64, 0);
+    riscv_cpu_set_misa(env, MXL_RV64, 0);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64,
+                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
     env->priv_ver = PRIV_VERSION_1_11_0;
 
     cpu->cfg.ext_zfa = true;
@@ -XXX,XX +XXX,XX @@ static void rv64_veyron_v1_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
     env->priv_ver = PRIV_VERSION_1_12_0;
 
     /* Enable ISA extensions */
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
     }
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, MXL_RV128, 0);
+    riscv_cpu_set_misa(env, MXL_RV128, 0);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, MXL_RV32, 0);
+    riscv_cpu_set_misa(env, MXL_RV32, 0);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32,
+                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_11_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
accelerator. It'll be called from within riscv_cpu_post_init(), via
accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
preserve behavior, the implementation will be similar to what
riscv_cpu_post_init() already does.

In this patch we'll move riscv_cpu_add_user_properties() and
riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
All multi-extension properties code was moved. The 'multi_ext_user_opts'
hash table was also moved to tcg-cpu.c since it's a TCG only structure,
meaning that we won't have to worry about initializing a TCG hash table
when running a KVM CPU anymore.

riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
much code it requires to be moved at the same time. We'll do that in the
next patch.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |   1 -
 target/riscv/cpu.c         | 150 -------------------------------------
 target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+), 151 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
 
 /* used by tcg/tcg-cpu.c*/
 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
 };
 
-/* Hash that stores user set extensions */
-static GHashTable *multi_ext_user_opts;
-
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
@@ -XXX,XX +XXX,XX @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
     g_assert_not_reached();
 }
 
-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
-{
-    return g_hash_table_contains(multi_ext_user_opts,
-                                 GUINT_TO_POINTER(ext_offset));
-}
-
 const char * const riscv_int_regnames[] = {
     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
     "reserved"
 };
 
-static void riscv_cpu_add_user_properties(Object *obj);
-static void riscv_init_max_cpu_extensions(Object *obj);
-
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 {
     if (async) {
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 }
 
-static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
-{
-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
-}
-
-static bool riscv_cpu_has_user_properties(Object *cpu_obj)
-{
-    if (kvm_enabled() &&
-        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
-        return true;
-    }
-
-    return riscv_cpu_is_dynamic(cpu_obj);
-}
-
 static void riscv_cpu_post_init(Object *obj)
 {
     accel_cpu_instance_init(CPU(obj));
-
-    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
-        riscv_cpu_add_user_properties(obj);
-    }
-
-    if (riscv_cpu_has_max_extensions(obj)) {
-        riscv_init_max_cpu_extensions(obj);
-    }
 }
 
 static void riscv_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
 #endif /* CONFIG_USER_ONLY */
-
-    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 }
 
 typedef struct RISCVCPUMisaExtConfig {
@@ -XXX,XX +XXX,XX @@ Property riscv_cpu_options[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                  void *opaque, Error **errp)
-{
-    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-    bool value;
-
-    if (!visit_type_bool(v, name, &value, errp)) {
-        return;
-    }
-
-    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
-
-    g_hash_table_insert(multi_ext_user_opts,
-                        GUINT_TO_POINTER(multi_ext_cfg->offset),
-                        (gpointer)value);
-}
-
-static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                  void *opaque, Error **errp)
-{
-    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
-
-    visit_type_bool(v, name, &value, errp);
-}
-
-static void cpu_add_multi_ext_prop(Object *cpu_obj,
-                                   const RISCVCPUMultiExtConfig *multi_cfg)
-{
-    object_property_add(cpu_obj, multi_cfg->name, "bool",
-                        cpu_get_multi_ext_cfg,
-                        cpu_set_multi_ext_cfg,
-                        NULL, (void *)multi_cfg);
-
-    /*
-     * Set def val directly instead of using
-     * object_property_set_bool() to save the set()
-     * callback hash for user inputs.
-     */
-    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
-                           multi_cfg->enabled);
-}
-
-static void riscv_cpu_add_multiext_prop_array(Object *obj,
-                                        const RISCVCPUMultiExtConfig *array)
-{
-    const RISCVCPUMultiExtConfig *prop;
-
-    g_assert(array);
-
-    for (prop = array; prop && prop->name; prop++) {
-        cpu_add_multi_ext_prop(obj, prop);
-    }
-}
-
-/*
- * Add CPU properties with user-facing flags.
- *
- * This will overwrite existing env->misa_ext values with the
- * defaults set via riscv_cpu_add_misa_properties().
- */
-static void riscv_cpu_add_user_properties(Object *obj)
-{
-#ifndef CONFIG_USER_ONLY
-    riscv_add_satp_mode_properties(obj);
-#endif
-
-    riscv_cpu_add_misa_properties(obj);
-
-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
-
-    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
-        qdev_property_add_static(DEVICE(obj), prop);
-    }
-}
-
-/*
- * The 'max' type CPU will have all possible ratified
- * non-vendor extensions enabled.
- */
-static void riscv_init_max_cpu_extensions(Object *obj)
-{
-    RISCVCPU *cpu = RISCV_CPU(obj);
-    CPURISCVState *env = &cpu->env;
-    const RISCVCPUMultiExtConfig *prop;
-
-    /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-
-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        isa_ext_update_enabled(cpu, prop->offset, true);
-    }
-
-    /* set vector version */
-    env->vext_ver = VEXT_VERSION_1_00_0;
-
-    /* Zfinx is not compatible with F. Disable it */
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
-
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
-
-    if (env->misa_mxl != MXL_RV32) {
-        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
-    }
-}
-
 static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "pmu.h"
 #include "time_helper.h"
 #include "qapi/error.h"
+#include "qapi/visitor.h"
 #include "qemu/accel.h"
 #include "qemu/error-report.h"
 #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/core/tcg-cpu-ops.h"
 #include "tcg/tcg.h"
 
+/* Hash that stores user set extensions */
+static GHashTable *multi_ext_user_opts;
+
+static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+{
+    return g_hash_table_contains(multi_ext_user_opts,
+                                 GUINT_TO_POINTER(ext_offset));
+}
+
 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
                                           const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
     return true;
 }
 
+static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
+
+    g_hash_table_insert(multi_ext_user_opts,
+                        GUINT_TO_POINTER(multi_ext_cfg->offset),
+                        (gpointer)value);
+}
+
+static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_add_multi_ext_prop(Object *cpu_obj,
+                                   const RISCVCPUMultiExtConfig *multi_cfg)
+{
+    object_property_add(cpu_obj, multi_cfg->name, "bool",
+                        cpu_get_multi_ext_cfg,
+                        cpu_set_multi_ext_cfg,
+                        NULL, (void *)multi_cfg);
+
+    /*
+     * Set def val directly instead of using
+     * object_property_set_bool() to save the set()
+     * callback hash for user inputs.
+     */
+    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
+                           multi_cfg->enabled);
+}
+
+static void riscv_cpu_add_multiext_prop_array(Object *obj,
+                                        const RISCVCPUMultiExtConfig *array)
+{
+    const RISCVCPUMultiExtConfig *prop;
+
+    g_assert(array);
+
+    for (prop = array; prop && prop->name; prop++) {
+        cpu_add_multi_ext_prop(obj, prop);
+    }
+}
+
+/*
+ * Add CPU properties with user-facing flags.
+ *
+ * This will overwrite existing env->misa_ext values with the
+ * defaults set via riscv_cpu_add_misa_properties().
+ */
+static void riscv_cpu_add_user_properties(Object *obj)
+{
+#ifndef CONFIG_USER_ONLY
+    riscv_add_satp_mode_properties(obj);
+#endif
+
+    riscv_cpu_add_misa_properties(obj);
+
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
+
+    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+        qdev_property_add_static(DEVICE(obj), prop);
+    }
+}
+
+/*
+ * The 'max' type CPU will have all possible ratified
+ * non-vendor extensions enabled.
+ */
+static void riscv_init_max_cpu_extensions(Object *obj)
+{
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    const RISCVCPUMultiExtConfig *prop;
+
+    /* Enable RVG, RVJ and RVV that are disabled by default */
+    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+
+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+        isa_ext_update_enabled(cpu, prop->offset, true);
+    }
+
+    /* set vector version */
+    env->vext_ver = VEXT_VERSION_1_00_0;
+
+    /* Zfinx is not compatible with F. Disable it */
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
+
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
+
+    if (env->misa_mxl != MXL_RV32) {
+        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
+    }
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static void tcg_cpu_instance_init(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    Object *obj = OBJECT(cpu);
+
+    if (riscv_cpu_has_user_properties(obj)) {
+        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+        riscv_cpu_add_user_properties(obj);
+    }
+
+    if (riscv_cpu_has_max_extensions(obj)) {
+        riscv_init_max_cpu_extensions(obj);
+    }
+}
+
 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 
     acc->cpu_class_init = tcg_cpu_class_init;
+    acc->cpu_instance_init = tcg_cpu_instance_init;
     acc->cpu_target_realize = tcg_cpu_realize;
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The array isn't marked as 'const' because we're initializing their
elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
fields.

In a closer look we can see that we're not using these 2 fields after
creating the MISA properties. And we can create the properties by using
riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
directly.

Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
and make misa_ext_cfgs[] a const array.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 }
 
 typedef struct RISCVCPUMisaExtConfig {
-    const char *name;
-    const char *description;
     target_ulong misa_bit;
     bool enabled;
 } RISCVCPUMisaExtConfig;
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
 #define MISA_CFG(_bit, _enabled) \
     {.misa_bit = _bit, .enabled = _enabled}
 
-static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
     MISA_CFG(RVA, true),
     MISA_CFG(RVC, true),
     MISA_CFG(RVD, true),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_add_misa_properties(Object *cpu_obj)
     int i;
 
     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
-        RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
         int bit = misa_cfg->misa_bit;
-
-        misa_cfg->name = riscv_get_misa_ext_name(bit);
-        misa_cfg->description = riscv_get_misa_ext_description(bit);
+        const char *name = riscv_get_misa_ext_name(bit);
+        const char *desc = riscv_get_misa_ext_description(bit);
 
         /* Check if KVM already created the property */
-        if (object_property_find(cpu_obj, misa_cfg->name)) {
+        if (object_property_find(cpu_obj, name)) {
             continue;
         }
 
-        object_property_add(cpu_obj, misa_cfg->name, "bool",
+        object_property_add(cpu_obj, name, "bool",
                             cpu_get_misa_ext_cfg,
                             cpu_set_misa_ext_cfg,
                             NULL, (void *)misa_cfg);
-        object_property_set_description(cpu_obj, misa_cfg->name,
-                                        misa_cfg->description);
-        object_property_set_bool(cpu_obj, misa_cfg->name,
-                                 misa_cfg->enabled, NULL);
+        object_property_set_description(cpu_obj, name, desc);
+        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
     }
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

All code related to MISA TCG properties is also moved.

At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
properties handling is done in kvm-cpu.c.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 -
 target/riscv/cpu.c         | 90 --------------------------------------
 target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 90 insertions(+), 91 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 extern Property riscv_cpu_options[];
 
-void riscv_cpu_add_misa_properties(Object *cpu_obj);
 void riscv_add_satp_mode_properties(Object *obj);
 
 /* CSR function table */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 #endif /* CONFIG_USER_ONLY */
 }
 
-typedef struct RISCVCPUMisaExtConfig {
-    target_ulong misa_bit;
-    bool enabled;
-} RISCVCPUMisaExtConfig;
-
-static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                 void *opaque, Error **errp)
-{
-    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-    target_ulong misa_bit = misa_ext_cfg->misa_bit;
-    RISCVCPU *cpu = RISCV_CPU(obj);
-    CPURISCVState *env = &cpu->env;
-    bool value;
-
-    if (!visit_type_bool(v, name, &value, errp)) {
-        return;
-    }
-
-    if (value) {
-        env->misa_ext |= misa_bit;
-        env->misa_ext_mask |= misa_bit;
-    } else {
-        env->misa_ext &= ~misa_bit;
-        env->misa_ext_mask &= ~misa_bit;
-    }
-}
-
-static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                 void *opaque, Error **errp)
-{
-    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-    target_ulong misa_bit = misa_ext_cfg->misa_bit;
-    RISCVCPU *cpu = RISCV_CPU(obj);
-    CPURISCVState *env = &cpu->env;
-    bool value;
-
-    value = env->misa_ext & misa_bit;
-
-    visit_type_bool(v, name, &value, errp);
-}
-
 typedef struct misa_ext_info {
     const char *name;
     const char *description;
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
     return val;
 }
 
-#define MISA_CFG(_bit, _enabled) \
-    {.misa_bit = _bit, .enabled = _enabled}
-
-static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
-    MISA_CFG(RVA, true),
-    MISA_CFG(RVC, true),
-    MISA_CFG(RVD, true),
-    MISA_CFG(RVF, true),
-    MISA_CFG(RVI, true),
-    MISA_CFG(RVE, false),
-    MISA_CFG(RVM, true),
-    MISA_CFG(RVS, true),
-    MISA_CFG(RVU, true),
-    MISA_CFG(RVH, true),
-    MISA_CFG(RVJ, false),
-    MISA_CFG(RVV, false),
-    MISA_CFG(RVG, false),
-};
-
-/*
- * We do not support user choice tracking for MISA
- * extensions yet because, so far, we do not silently
- * change MISA bits during realize() (RVG enables MISA
- * bits but the user is warned about it).
- */
-void riscv_cpu_add_misa_properties(Object *cpu_obj)
-{
-    int i;
-
-    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
-        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
-        int bit = misa_cfg->misa_bit;
-        const char *name = riscv_get_misa_ext_name(bit);
-        const char *desc = riscv_get_misa_ext_description(bit);
-
-        /* Check if KVM already created the property */
-        if (object_property_find(cpu_obj, name)) {
-            continue;
-        }
-
-        object_property_add(cpu_obj, name, "bool",
-                            cpu_get_misa_ext_cfg,
-                            cpu_set_misa_ext_cfg,
-                            NULL, (void *)misa_cfg);
-        object_property_set_description(cpu_obj, name, desc);
-        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
-    }
-}
-
 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .enabled = _defval}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
     return true;
 }
 
+typedef struct RISCVCPUMisaExtConfig {
+    target_ulong misa_bit;
+    bool enabled;
+} RISCVCPUMisaExtConfig;
+
+static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                 void *opaque, Error **errp)
+{
+    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+    target_ulong misa_bit = misa_ext_cfg->misa_bit;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    if (value) {
+        env->misa_ext |= misa_bit;
+        env->misa_ext_mask |= misa_bit;
+    } else {
+        env->misa_ext &= ~misa_bit;
+        env->misa_ext_mask &= ~misa_bit;
+    }
+}
+
+static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                 void *opaque, Error **errp)
+{
+    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+    target_ulong misa_bit = misa_ext_cfg->misa_bit;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    bool value;
+
+    value = env->misa_ext & misa_bit;
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+#define MISA_CFG(_bit, _enabled) \
+    {.misa_bit = _bit, .enabled = _enabled}
+
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+    MISA_CFG(RVA, true),
+    MISA_CFG(RVC, true),
+    MISA_CFG(RVD, true),
+    MISA_CFG(RVF, true),
+    MISA_CFG(RVI, true),
+    MISA_CFG(RVE, false),
+    MISA_CFG(RVM, true),
+    MISA_CFG(RVS, true),
+    MISA_CFG(RVU, true),
+    MISA_CFG(RVH, true),
+    MISA_CFG(RVJ, false),
+    MISA_CFG(RVV, false),
+    MISA_CFG(RVG, false),
+};
+
+/*
+ * We do not support user choice tracking for MISA
+ * extensions yet because, so far, we do not silently
+ * change MISA bits during realize() (RVG enables MISA
+ * bits but the user is warned about it).
+ */
+static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+        int bit = misa_cfg->misa_bit;
+        const char *name = riscv_get_misa_ext_name(bit);
+        const char *desc = riscv_get_misa_ext_description(bit);
+
+        /* Check if KVM already created the property */
+        if (object_property_find(cpu_obj, name)) {
+            continue;
+        }
+
+        object_property_add(cpu_obj, name, "bool",
+                            cpu_get_misa_ext_cfg,
+                            cpu_set_misa_ext_cfg,
+                            NULL, (void *)misa_cfg);
+        object_property_set_description(cpu_obj, name, desc);
+        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+    }
+}
+
 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                   void *opaque, Error **errp)
 {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This array will be read by the TCG accel class, allowing it to handle
priv spec verifications on its own. The array will remain here in cpu.c
because it's also used by the riscv,isa string function.

To export it we'll finish it with an empty element since ARRAY_SIZE()
won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
alleviate the changes for the next patch.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  7 +++++++
 target/riscv/cpu.c | 47 +++++++++++++++++++++-------------------------
 2 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 extern Property riscv_cpu_options[];
 
+typedef struct isa_ext_data {
+    const char *name;
+    int min_version;
+    int ext_enable_offset;
+} RISCVIsaExtData;
+extern const RISCVIsaExtData isa_edata_arr[];
+
 void riscv_add_satp_mode_properties(Object *obj);
 
 /* CSR function table */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
                               RVC, RVS, RVU, RVH, RVJ, RVG, 0};
 
-struct isa_ext_data {
-    const char *name;
-    int min_version;
-    int ext_enable_offset;
-};
-
-#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
-    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
-
 /*
  * From vector_helper.c
  * Note that vector data is stored in host-endian 64-bit chunks,
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
 #define BYTE(x)   (x)
 #endif
 
+#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
+    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
+
 /*
  * Here are the ordering rules of extension naming defined by RISC-V
  * specification :
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
  * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
  * instead.
  */
-static const struct isa_ext_data isa_edata_arr[] = {
+const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
     ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+
+    DEFINE_PROP_END_OF_LIST(),
 };
 
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
 
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 {
-    int i;
+    const RISCVIsaExtData *edata;
 
-    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
+        if (edata->ext_enable_offset != ext_offset) {
             continue;
         }
 
-        return isa_edata_arr[i].min_version;
+        return edata->min_version;
     }
 
     g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
-    int i;
+    const RISCVIsaExtData *edata;
 
     /* Force disable extensions if priv spec version does not match */
-    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
-            (env->priv_ver < isa_edata_arr[i].min_version)) {
-            isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
-                                   false);
+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
+        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
+            (env->priv_ver < edata->min_version)) {
+            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 #ifndef CONFIG_USER_ONLY
             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
                         " because privilege spec version does not match",
-                        isa_edata_arr[i].name, env->mhartid);
+                        edata->name, env->mhartid);
 #else
             warn_report("disabling %s extension because "
                         "privilege spec version does not match",
-                        isa_edata_arr[i].name);
+                        edata->name);
 #endif
         }
     }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
                                  int max_str_len)
 {
+    const RISCVIsaExtData *edata;
     char *old = *isa_str;
     char *new = *isa_str;
-    int i;
 
-    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
-            new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
+        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
+            new = g_strconcat(old, "_", edata->name, NULL);
             g_free(old);
             old = new;
         }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Priv spec validation is TCG specific. Move it to the TCG accel class.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230925175709.35696-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  2 --
 target/riscv/cpu.c         | 38 --------------------------------------
 target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 38 insertions(+), 40 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll introduce generic errors that will output a CPU type name via its
RISCVCPU pointer. Create a helper for that.

Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host'
CPU name.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230926183109.165878-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/cpu.c         | 11 +++++++++++
 target/riscv/tcg/tcg-cpu.c |  4 +++-
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct isa_ext_data {
     int ext_enable_offset;
 } RISCVIsaExtData;
 extern const RISCVIsaExtData isa_edata_arr[];
+char *riscv_cpu_get_name(RISCVCPU *cpu);
 
 void riscv_add_satp_mode_properties(Object *obj);
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
+char *riscv_cpu_get_name(RISCVCPU *cpu)
+{
+    RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
+    const char *typename = object_class_get_name(OBJECT_CLASS(rcc));
+
+    g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX));
+
+    return g_strndup(typename,
+                     strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX));
+}
+
 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
     Error *local_err = NULL;
 
     if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
-        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
+        g_autofree char *name = riscv_cpu_get_name(cpu);
+        error_setg(errp, "'%s' CPU is not compatible with TCG acceleration",
+                   name);
         return false;
     }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

At this moment we do not expose extension properties for vendor CPUs
because that would allow users to change them via command line. The
drawback is that if we were to add an API that shows all CPU properties,
e.g. qmp-query-cpu-model-expansion, we won't be able to show extensions
state of vendor CPUs.

We have the required machinery to create extension properties for vendor
CPUs while not allowing users to enable extensions. Disabling existing
extensions is allowed since it can be useful for debugging.

Change the set() callback cpu_set_multi_ext_cfg() to allow enabling
extensions only for generic CPUs. In cpu_add_multi_ext_prop() let's not
set the default values for the properties if we're not dealing with
generic CPUs, otherwise the values set in cpu_init() of vendor CPUs will
be overwritten. And finally, in tcg_cpu_instance_init(), add cpu user
properties for all CPUs.

For the veyron-v1 CPU, we're now able to disable existing extensions
like smstateen:

$ ./build/qemu-system-riscv64 --nographic -M virt \
    -cpu veyron-v1,smstateen=false

But setting extensions that the CPU didn't set during cpu_init(), like
V, is not allowed:

$ ./build/qemu-system-riscv64 --nographic -M virt \
    -cpu veyron-v1,v=true
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.v=true:
  'veyron-v1' CPU does not allow enabling extensions

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230926183109.165878-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/tcg-cpu.c | 64 +++++++++++++++++++++++++++++---------
 1 file changed, 50 insertions(+), 14 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     riscv_cpu_disable_priv_spec_isa_exts(cpu);
 }
 
+static bool riscv_cpu_is_generic(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
 /*
  * We'll get here via the following path:
  *
@@ -XXX,XX +XXX,XX @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
     target_ulong misa_bit = misa_ext_cfg->misa_bit;
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    bool value;
+    bool generic_cpu = riscv_cpu_is_generic(obj);
+    bool prev_val, value;
 
     if (!visit_type_bool(v, name, &value, errp)) {
         return;
     }
 
+    prev_val = env->misa_ext & misa_bit;
+
+    if (value == prev_val) {
+        return;
+    }
+
     if (value) {
+        if (!generic_cpu) {
+            g_autofree char *cpuname = riscv_cpu_get_name(cpu);
+            error_setg(errp, "'%s' CPU does not allow enabling extensions",
+                       cpuname);
+            return;
+        }
+
         env->misa_ext |= misa_bit;
         env->misa_ext_mask |= misa_bit;
     } else {
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
  */
 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 {
+    bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
     int i;
 
     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
                             cpu_set_misa_ext_cfg,
                             NULL, (void *)misa_cfg);
         object_property_set_description(cpu_obj, name, desc);
-        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+        if (use_def_vals) {
+            object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+        }
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                   void *opaque, Error **errp)
 {
     const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-    bool value;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    bool generic_cpu = riscv_cpu_is_generic(obj);
+    bool prev_val, value;
 
     if (!visit_type_bool(v, name, &value, errp)) {
         return;
     }
 
-    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
-
     g_hash_table_insert(multi_ext_user_opts,
                         GUINT_TO_POINTER(multi_ext_cfg->offset),
                         (gpointer)value);
+
+    prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
+
+    if (value == prev_val) {
+        return;
+    }
+
+    if (value && !generic_cpu) {
+        g_autofree char *cpuname = riscv_cpu_get_name(cpu);
+        error_setg(errp, "'%s' CPU does not allow enabling extensions",
+                   cpuname);
+        return;
+    }
+
+    isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value);
 }
 
 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 static void cpu_add_multi_ext_prop(Object *cpu_obj,
                                    const RISCVCPUMultiExtConfig *multi_cfg)
 {
+    bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
+
     object_property_add(cpu_obj, multi_cfg->name, "bool",
                         cpu_get_multi_ext_cfg,
                         cpu_set_multi_ext_cfg,
                         NULL, (void *)multi_cfg);
 
+    if (!generic_cpu) {
+        return;
+    }
+
     /*
      * Set def val directly instead of using
      * object_property_set_bool() to save the set()
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
     return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
 }
 
-static bool riscv_cpu_has_user_properties(Object *cpu_obj)
-{
-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-}
-
 static void tcg_cpu_instance_init(CPUState *cs)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     Object *obj = OBJECT(cpu);
 
-    if (riscv_cpu_has_user_properties(obj)) {
-        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
-        riscv_cpu_add_user_properties(obj);
-    }
+    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+    riscv_cpu_add_user_properties(obj);
 
     if (riscv_cpu_has_max_extensions(obj)) {
         riscv_init_max_cpu_extensions(obj);
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

As of now, the exit code was either EXIT_FAILURE when a panic shutdown
was requested or EXIT_SUCCESS otherwise.
However, some hardware could want to pass more complex exit codes. Thus,
introduce a new shutdown request function allowing that.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-2-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/sysemu/runstate.h |  2 ++
 system/runstate.c         | 12 +++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/runstate.h
+++ b/include/sysemu/runstate.h
@@ -XXX,XX +XXX,XX @@ void qemu_system_wakeup_request(WakeupReason reason, Error **errp);
 void qemu_system_wakeup_enable(WakeupReason reason, bool enabled);
 void qemu_register_wakeup_notifier(Notifier *notifier);
 void qemu_register_wakeup_support(void);
+void qemu_system_shutdown_request_with_code(ShutdownCause reason,
+                                            int exit_code);
 void qemu_system_shutdown_request(ShutdownCause reason);
 void qemu_system_powerdown_request(void);
 void qemu_register_powerdown_notifier(Notifier *notifier);
diff --git a/system/runstate.c b/system/runstate.c
index XXXXXXX..XXXXXXX 100644
--- a/system/runstate.c
+++ b/system/runstate.c
@@ -XXX,XX +XXX,XX @@ void vm_state_notify(bool running, RunState state)
 
 static ShutdownCause reset_requested;
 static ShutdownCause shutdown_requested;
+static int shutdown_exit_code = EXIT_SUCCESS;
 static int shutdown_signal;
 static pid_t shutdown_pid;
 static int powerdown_requested;
@@ -XXX,XX +XXX,XX @@ void qemu_system_killed(int signal, pid_t pid)
     qemu_notify_event();
 }
 
+void qemu_system_shutdown_request_with_code(ShutdownCause reason,
+                                            int exit_code)
+{
+    shutdown_exit_code = exit_code;
+    qemu_system_shutdown_request(reason);
+}
+
 void qemu_system_shutdown_request(ShutdownCause reason)
 {
     trace_qemu_system_shutdown_request(reason);
@@ -XXX,XX +XXX,XX @@ static bool main_loop_should_exit(int *status)
         if (shutdown_action == SHUTDOWN_ACTION_PAUSE) {
             vm_stop(RUN_STATE_SHUTDOWN);
         } else {
-            if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
+            if (shutdown_exit_code != EXIT_SUCCESS) {
+                *status = shutdown_exit_code;
+            } else if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
                 panic_action == PANIC_ACTION_EXIT_FAILURE) {
                 *status = EXIT_FAILURE;
             }
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

gdb_exit function aims to close gdb sessions and sends the exit code of
the current execution. It's being called by qemu_cleanup once the main
loop is over.
Until now, the exit code sent was always 0. Now that hardware can
shutdown this main loop with custom exit codes, these codes must be
transfered to gdb as well.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-3-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/sysemu/sysemu.h | 2 +-
 system/main.c           | 2 +-
 system/runstate.c       | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -XXX,XX +XXX,XX @@ bool defaults_enabled(void);
 
 void qemu_init(int argc, char **argv);
 int qemu_main_loop(void);
-void qemu_cleanup(void);
+void qemu_cleanup(int);
 
 extern QemuOptsList qemu_legacy_drive_opts;
 extern QemuOptsList qemu_common_drive_opts;
diff --git a/system/main.c b/system/main.c
index XXXXXXX..XXXXXXX 100644
--- a/system/main.c
+++ b/system/main.c
@@ -XXX,XX +XXX,XX @@ int qemu_default_main(void)
     int status;
 
     status = qemu_main_loop();
-    qemu_cleanup();
+    qemu_cleanup(status);
 
     return status;
 }
diff --git a/system/runstate.c b/system/runstate.c
index XXXXXXX..XXXXXXX 100644
--- a/system/runstate.c
+++ b/system/runstate.c
@@ -XXX,XX +XXX,XX @@ void qemu_init_subsystems(void)
 }
 
 
-void qemu_cleanup(void)
+void qemu_cleanup(int status)
 {
-    gdb_exit(0);
+    gdb_exit(status);
 
     /*
      * cleaning up the migration object cancels any existing migration
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Otherwise, some connections like gdb could be broken
before its final packet ("Wxx") is being sent. This part, being done
inside qemu_cleanup function, can be reached only when the main loop
exits after a shutdown request.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-4-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/misc/sifive_test.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_test.c
+++ b/hw/misc/sifive_test.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
 #include "hw/misc/sifive_test.h"
+#include "sysemu/sysemu.h"
 
 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
 {
@@ -XXX,XX +XXX,XX @@ static void sifive_test_write(void *opaque, hwaddr addr,
         int code = (val64 >> 16) & 0xffff;
         switch (status) {
         case FINISHER_FAIL:
-            exit(code);
+            qemu_system_shutdown_request_with_code(
+                SHUTDOWN_CAUSE_GUEST_PANIC, code);
+            return;
         case FINISHER_PASS:
-            exit(0);
+            qemu_system_shutdown_request_with_code(
+                SHUTDOWN_CAUSE_GUEST_SHUTDOWN, code);
+            return;
         case FINISHER_RESET:
             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
             return;
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-5-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "exec/tswap.h"
 #include "sysemu/dma.h"
+#include "sysemu/runstate.h"
 
 #define RISCV_DEBUG_HTIF 0
 #define HTIF_DEBUG(fmt, ...)                                                   \
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
                     g_free(sig_data);
                 }
 
-                exit(exit_code);
+                qemu_system_shutdown_request_with_code(
+                    SHUTDOWN_CAUSE_GUEST_SHUTDOWN, exit_code);
+                return;
             } else {
                 uint64_t syscall[8];
                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Features like net/vhost-vdpa.c are expecting
qemu_cleanup to be called to remove their last residuals.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-6-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/gdbstub/syscalls.h | 9 +++++++++
 gdbstub/gdbstub.c          | 5 +++--
 gdbstub/system.c           | 6 ++++++
 gdbstub/user.c             | 6 ++++++
 4 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/include/gdbstub/syscalls.h b/include/gdbstub/syscalls.h
index XXXXXXX..XXXXXXX 100644
--- a/include/gdbstub/syscalls.h
+++ b/include/gdbstub/syscalls.h
@@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void);
  */
 void gdb_exit(int code);
 
+/**
+ * gdb_qemu_exit: ask qemu to exit
+ * @code: exit code reported
+ *
+ * This requests qemu to exit. This function is allowed to return as
+ * the exit request might be processed asynchronously by qemu backend.
+ */
+void gdb_qemu_exit(int code);
+
 #endif /* _SYSCALLS_H_ */
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void handle_v_kill(GArray *params, void *user_ctx)
     gdb_put_packet("OK");
     error_report("QEMU: Terminated via GDBstub");
     gdb_exit(0);
-    exit(0);
+    gdb_qemu_exit(0);
 }
 
 static const GdbCmdParseEntry gdb_v_commands_table[] = {
@@ -XXX,XX +XXX,XX @@ static int gdb_handle_packet(const char *line_buf)
         /* Kill the target */
         error_report("QEMU: Terminated via GDBstub");
         gdb_exit(0);
-        exit(0);
+        gdb_qemu_exit(0);
+        break;
     case 'D':
         {
             static const GdbCmdParseEntry detach_cmd_desc = {
diff --git a/gdbstub/system.c b/gdbstub/system.c
index XXXXXXX..XXXXXXX 100644
--- a/gdbstub/system.c
+++ b/gdbstub/system.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
     qemu_chr_fe_deinit(&gdbserver_system_state.chr, true);
 }
 
+void gdb_qemu_exit(int code)
+{
+    qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN,
+                                           code);
+}
+
 /*
  * Memory access
  */
diff --git a/gdbstub/user.c b/gdbstub/user.c
index XXXXXXX..XXXXXXX 100644
--- a/gdbstub/user.c
+++ b/gdbstub/user.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
         gdb_put_packet(buf);
         gdbserver_state.allow_stop_reply = false;
     }
+
+}
+
+void gdb_qemu_exit(int code)
+{
+    exit(code);
 }
 
 int gdb_handlesig(CPUState *cpu, int sig)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Our error message is returning the value of 'ret', which will be always
-1 in case of error, and will not be that useful:

qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error -1

Improve the error message by outputting 'errno' instead of 'ret'. Use
strerrorname_np() to output the error name instead of the error code.
This will give us what we need to know right away:

qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error code: ENOENT

Given that we're going to exit(1) in this condition instead of
attempting to recover, remove the 'kvm_riscv_destroy_scratch_vcpu()'
call.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231003132148.797921-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It
consists of a KVM ioctl() that retrieves a list of all available regs
for get_one_reg/set_one_reg. Regs that aren't present in the list aren't
supported in the host.

This simplifies our lives when initing the KVM regs since we don't have
to always attempt a KVM_GET_ONE_REG for all regs QEMU knows. We'll only
attempt a get_one_reg() if we're sure the reg is supported, i.e. it was
retrieved by KVM_GET_REG_LIST. Any error in get_one_reg() will then
always considered fatal, instead of having to handle special error codes
that might indicate a non-fatal failure.

Start by moving the current kvm_riscv_init_multiext_cfg() logic into a
new kvm_riscv_read_multiext_legacy() helper. We'll prioritize using
KVM_GET_REG_LIST, so check if we have it available and, in case we
don't, use the legacy() logic.

Otherwise, retrieve the available reg list and use it to check if the
host supports our known KVM regs, doing the usual get_one_reg() for
the supported regs and setting cpu->cfg accordingly.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003132148.797921-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 96 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
     }
 }
 
-static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
+                                           KVMScratchCPU *kvmcpu)
 {
     CPURISCVState *env = &cpu->env;
     uint64_t val;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     }
 }
 
+static int uint64_cmp(const void *a, const void *b)
+{
+    uint64_t val1 = *(const uint64_t *)a;
+    uint64_t val2 = *(const uint64_t *)b;
+
+    if (val1 < val2) {
+        return -1;
+    }
+
+    if (val1 > val2) {
+        return 1;
+    }
+
+    return 0;
+}
+
+static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+{
+    KVMCPUConfig *multi_ext_cfg;
+    struct kvm_one_reg reg;
+    struct kvm_reg_list rl_struct;
+    struct kvm_reg_list *reglist;
+    uint64_t val, reg_id, *reg_search;
+    int i, ret;
+
+    rl_struct.n = 0;
+    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct);
+
+    /*
+     * If KVM_GET_REG_LIST isn't supported we'll get errno 22
+     * (EINVAL). Use read_legacy() in this case.
+     */
+    if (errno == EINVAL) {
+        return kvm_riscv_read_multiext_legacy(cpu, kvmcpu);
+    } else if (errno != E2BIG) {
+        /*
+         * E2BIG is an expected error message for the API since we
+         * don't know the number of registers. The right amount will
+         * be written in rl_struct.n.
+         *
+         * Error out if we get any other errno.
+         */
+        error_report("Error when accessing get-reg-list, code: %s",
+                     strerrorname_np(errno));
+        exit(EXIT_FAILURE);
+    }
+
+    reglist = g_malloc(sizeof(struct kvm_reg_list) +
+                       rl_struct.n * sizeof(uint64_t));
+    reglist->n = rl_struct.n;
+    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist);
+    if (ret) {
+        error_report("Error when reading KVM_GET_REG_LIST, code %s ",
+                     strerrorname_np(errno));
+        exit(EXIT_FAILURE);
+    }
+
+    /* sort reglist to use bsearch() */
+    qsort(&reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp);
+
+    for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
+        multi_ext_cfg = &kvm_multi_ext_cfgs[i];
+        reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT,
+                                  multi_ext_cfg->kvm_reg_id);
+        reg_search = bsearch(&reg_id, reglist->reg, reglist->n,
+                             sizeof(uint64_t), uint64_cmp);
+        if (!reg_search) {
+            continue;
+        }
+
+        reg.id = reg_id;
+        reg.addr = (uint64_t)&val;
+        ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg);
+        if (ret != 0) {
+            error_report("Unable to read ISA_EXT KVM register %s, "
+                         "error code: %s", multi_ext_cfg->name,
+                         strerrorname_np(errno));
+            exit(EXIT_FAILURE);
+        }
+
+        multi_ext_cfg->supported = true;
+        kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
+    }
+
+    if (cpu->cfg.ext_icbom) {
+        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
+    }
+
+    if (cpu->cfg.ext_icboz) {
+        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
+    }
+}
+
 static void riscv_init_kvm_registers(Object *cpu_obj)
 {
     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Vendor CPUs that set RVG are displaying user warnings about other
extensions that RVG must enable, one warning per CPU. E.g.:

$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei

This happens because we decided a while ago that, for simplicity, vendor
CPUs could set RVG instead of setting each G extension individually in
their cpu_init(). Our warning isn't taking that into account, and we're
bugging users with a warning that we're causing ourselves.

In a closer look we conclude that this warning is not warranted in any
other circumstance since we're just following the ISA [1], which states
in chapter 24:

"One goal of the RISC-V project is that it be used as a stable software
development target. For this purpose, we define a combination of a base
ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for
the IMAFDZicsr Zifencei combination of instruction-set extensions."

With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly
enables 'G' is an expected behavior and the warning is unneeded. Any
user caught by surprise should refer to the ISA.

Remove the warning when handling RVG.

[1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf

Reported-by: Paul A. Clarke <pclarke@ventanamicro.com>
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/tcg-cpu.c | 1 -
 1 file changed, 1 deletion(-)

From: "Richard W.M. Jones" <rjones@redhat.com>

RISCV_CPU(cs) uses a checked cast.  When QOM cast debugging is enabled
this adds about 5% total overhead when emulating RV64 on x86-64 host.

Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk
disk.  The guest has a copy of the qemu source tree.  The test
involves compiling the qemu source tree with 'make clean; time make -j16'.

Before making this change the compile step took 449 & 447 seconds over
two consecutive runs.

After making this change: 428 & 421 seconds.

The saving is over 5%.

Thanks: Paolo Bonzini
Thanks: Philippe Mathieu-Daudé
Signed-off-by: Richard W.M. Jones <rjones@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231009124859.3373696-2-rjones@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
                           uint64_t *cs_base, uint32_t *pflags)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
     RISCVExtStatus fs, vs;
     uint32_t flags = 0;
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

At this moment there are eleven CPU extension properties that starts
with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa,
Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named
with lower-case letters.

We want all properties to be named with lower-case letters since it's
consistent with the riscv-isa string that we create in the FDT. Having
these 11 properties to be exceptions can be confusing.

Deprecate all of them. Create their lower-case counterpart to be used as
maintained CPU properties. When trying to use any deprecated property a
warning message will be displayed, recommending users to switch to the
lower-case variant:

./build/qemu-system-riscv64 -M virt -cpu rv64,Zifencei=true --nographic
qemu-system-riscv64: warning: CPU property 'Zifencei' is deprecated. Please use 'zifencei' instead

This will give users some time to change their scripts before we remove
the capital 'Z' properties entirely.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231009112817.8896-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst  | 23 ++++++++++++++++++++++
 target/riscv/cpu.h         |  1 +
 target/riscv/cpu.c         | 39 +++++++++++++++++++++++++++-----------
 target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++-
 4 files changed, 82 insertions(+), 12 deletions(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
 CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
 CPU type starting in 8.2.
 
+RISC-V CPU properties which start with capital 'Z' (since 8.2)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+All RISC-V CPU properties which start with capital 'Z' are being deprecated
+starting in 8.2. The reason is that they were wrongly added with capital 'Z'
+in the past. CPU properties were later added with lower-case names, which
+is the format we want to use from now on.
+
+Users which try to use these deprecated properties will receive a warning
+recommending to switch to their stable counterparts:
+
+- "Zifencei" should be replaced with "zifencei"
+- "Zicsr" should be replaced with "zicsr"
+- "Zihintntl" should be replaced with "zihintntl"
+- "Zihintpause" should be replaced with "zihintpause"
+- "Zawrs" should be replaced with "zawrs"
+- "Zfa" should be replaced with "zfa"
+- "Zfh" should be replaced with "zfh"
+- "Zfhmin" should be replaced with "zfhmin"
+- "Zve32f" should be replaced with "zve32f"
+- "Zve64f" should be replaced with "zve64f"
+- "Zve64d" should be replaced with "zve64d"
+
 Block device options
 ''''''''''''''''''''
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
 extern Property riscv_cpu_options[];
 
 typedef struct isa_ext_data {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
 const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
-    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
-    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
-    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
-    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
-    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
-    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
-    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
-    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
-    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
-    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
-    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
+    MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
+    MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
+    MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
+    MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
+    MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
+    MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
+    MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
+    MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
 
     MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+/* Deprecated entries marked for future removal */
+const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
+    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
+    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
+    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
+    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
+    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
+    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
+    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
+    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
+
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 Property riscv_cpu_options[] = {
     DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
     }
 }
 
+static bool cpu_ext_is_deprecated(const char *ext_name)
+{
+    return isupper(ext_name[0]);
+}
+
+/*
+ * String will be allocated in the heap. Caller is responsible
+ * for freeing it.
+ */
+static char *cpu_ext_to_lower(const char *ext_name)
+{
+    char *ret = g_malloc0(strlen(ext_name) + 1);
+
+    strcpy(ret, ext_name);
+    ret[0] = tolower(ret[0]);
+
+    return ret;
+}
+
 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                   void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
         return;
     }
 
+    if (cpu_ext_is_deprecated(multi_ext_cfg->name)) {
+        g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name);
+
+        warn_report("CPU property '%s' is deprecated. Please use '%s' instead",
+                    multi_ext_cfg->name, lower);
+    }
+
     g_hash_table_insert(multi_ext_user_opts,
                         GUINT_TO_POINTER(multi_ext_cfg->offset),
                         (gpointer)value);
@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
                                    const RISCVCPUMultiExtConfig *multi_cfg)
 {
     bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
+    bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name);
 
     object_property_add(cpu_obj, multi_cfg->name, "bool",
                         cpu_get_multi_ext_cfg,
                         cpu_set_multi_ext_cfg,
                         NULL, (void *)multi_cfg);
 
-    if (!generic_cpu) {
+    if (!generic_cpu || deprecated_ext) {
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
 
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
+
     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
         qdev_property_add_static(DEVICE(obj), prop);
     }
-- 
2.41.0

From: Max Chou <max.chou@sifive.com>

The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
replaced by fwmaccbf16.

Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231005095734.567575-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16)
 GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
-RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
+RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16)
 GEN_VEXT_VF(vfwmaccbf16_vf, 4)
 
 static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
-- 
2.41.0

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1