[PATCH RESEND v5 13/57] target/loongarch: Add avail_LASX to check LASX instructions

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/loongarch/translate.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 89b49a859e..195f53573a 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -23,6 +23,7 @@
 #define avail_LSPW(C)  (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
 #define avail_LAM(C)   (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
 #define avail_LSX(C)   (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
+#define avail_LASX(C)  (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))
 #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
 
 /*
-- 
2.39.1

• [PATCH RESEND v5 01/57] target/loongarch: Renamed lsx*.c to vec* .c
• [PATCH RESEND v5 02/57] target/loongarch: Implement gvec_*_vl functions
• [PATCH RESEND v5 03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions
• [PATCH RESEND v5 04/57] target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions
• [PATCH RESEND v5 05/57] target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions
• [PATCH RESEND v5 06/57] target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions
• [PATCH RESEND v5 07/57] target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructions
• [PATCH RESEND v5 08/57] target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions
• [PATCH RESEND v5 09/57] target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions
• [PATCH RESEND v5 10/57] target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)
• [PATCH RESEND v5 11/57] target/loongarch: Add LASX data support
• [PATCH RESEND v5 12/57] target/loongarch: check_vec support check LASX instructions
• [PATCH RESEND v5 13/57] target/loongarch: Add avail_LASX to check LASX instructions
• [PATCH RESEND v5 14/57] target/loongarch: Implement xvadd/xvsub
• [PATCH RESEND v5 15/57] target/loongarch: Implement xvreplgr2vr
• [PATCH RESEND v5 16/57] target/loongarch: Implement xvaddi/xvsubi
• [PATCH RESEND v5 17/57] target/loongarch: Implement xvneg
• [PATCH RESEND v5 18/57] target/loongarch: Implement xvsadd/xvssub
• [PATCH RESEND v5 19/57] target/loongarch: Implement xvhaddw/xvhsubw
• [PATCH RESEND v5 20/57] target/loongarch: Implement xvaddw/xvsubw
• [PATCH RESEND v5 21/57] target/loongarch: Implement xavg/xvagr
• [PATCH RESEND v5 22/57] target/loongarch: Implement xvabsd
• [PATCH RESEND v5 23/57] target/loongarch: Implement xvadda
• [PATCH RESEND v5 24/57] target/loongarch: Implement xvmax/xvmin
• [PATCH RESEND v5 25/57] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
• [PATCH RESEND v5 26/57] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
• [PATCH RESEND v5 27/57] target/loongarch; Implement xvdiv/xvmod
• [PATCH RESEND v5 28/57] target/loongarch: Implement xvsat
• [PATCH RESEND v5 29/57] target/loongarch: Implement xvexth
• [PATCH RESEND v5 30/57] target/loongarch: Implement vext2xv
• [PATCH RESEND v5 31/57] target/loongarch: Implement xvsigncov
• [PATCH RESEND v5 32/57] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz
• [PATCH RESEND v5 33/57] target/loognarch: Implement xvldi
• [PATCH RESEND v5 34/57] target/loongarch: Implement LASX logic instructions
• [PATCH RESEND v5 35/57] target/loongarch: Implement xvsll xvsrl xvsra xvrotr
• [PATCH RESEND v5 36/57] target/loongarch: Implement xvsllwil xvextl
• [PATCH RESEND v5 37/57] target/loongarch: Implement xvsrlr xvsrar
• [PATCH RESEND v5 38/57] target/loongarch: Implement xvsrln xvsran
• [PATCH RESEND v5 39/57] target/loongarch: Implement xvsrlrn xvsrarn
• [PATCH RESEND v5 40/57] target/loongarch: Implement xvssrln xvssran
• [PATCH RESEND v5 41/57] target/loongarch: Implement xvssrlrn xvssrarn
• [PATCH RESEND v5 42/57] target/loongarch: Implement xvclo xvclz
• [PATCH RESEND v5 43/57] target/loongarch: Implement xvpcnt
• [PATCH RESEND v5 44/57] target/loongarch: Implement xvbitclr xvbitset xvbitrev
• [PATCH RESEND v5 45/57] target/loongarch: Implement xvfrstp
• [PATCH RESEND v5 46/57] target/loongarch: Implement LASX fpu arith instructions
• [PATCH RESEND v5 47/57] target/loongarch: Implement LASX fpu fcvt instructions
• [PATCH RESEND v5 48/57] target/loongarch: Implement xvseq xvsle xvslt
• [PATCH RESEND v5 49/57] target/loongarch: Implement xvfcmp
• [PATCH RESEND v5 50/57] target/loongarch: Implement xvbitsel xvset
• [PATCH RESEND v5 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr
• [PATCH RESEND v5 52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve
• [PATCH RESEND v5 53/57] target/loongarch: Implement xvpack xvpick xvilv{l/h}
• [PATCH RESEND v5 54/57] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i
• [PATCH RESEND v5 55/57] target/loongarch: Implement xvld xvst
• [PATCH RESEND v5 56/57] target/loongarch: Move simply DO_XX marcos togther
• [PATCH RESEND v5 57/57] target/loongarch: CPUCFG support LASX