Please ignore this series. I will resend.
Thanks.
Song Gao
在 2023/9/7 下午4:08, Song Gao 写道:
> Hi,
>
> This series adds LoongArch LASX instructions.
>
> About test:
> We use RISU test the LoongArch LASX instructions.
>
> QEMU:
> https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx
> RISU:
> https://github.com/loongson/risu/tree/loongarch-suport-lasx
>
> Please review, Thanks.
>
> Changes for v5:
> - Rebase;
> - Split V4'patch 10 to 7 patches(patch3-9);
> - LSX use gen/gvec_vv..
> - LASX use gen/gvec_xx...
> - Don't use an array of shift_res. (patch40,41);
> - Move simply DO_XX marcos together (patch56);
> - Renamed lsx*.c to vec*.c,(patch 1);
> - Change marcos CHECK_VEC to check_vec(ctx, oprsz);
> - R-b.
>
> Changes for v4:
> - Rebase;
> - Add avail_LASX to check.
>
> Changes for v3:
> - Add a new patch 9, rename lsx_helper.c to vec_helper.c,
> and use gen_helper_gvec_* series functions;
> - Use i < oprsz / (BIT / 8) in loop;
> - Some helper functions use loop;
> - patch 46: use tcg_gen_qemu_ld/st_i64 for xvld/xvst{x};
> - R-b.
>
> Changes for v2:
> - Expand the definition of VReg to be 256 bits.
> - Use more LSX functions.
> - R-b.
>
> Song Gao (57):
> target/loongarch: Renamed lsx*.c to vec* .c
> target/loongarch: Implement gvec_*_vl functions
> target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector
> instructions
> target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions
> target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector
> instructions
> target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions
> target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector
> instructions
> target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions
> target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector
> instructions
> target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)
> target/loongarch: Add LASX data support
> target/loongarch: check_vec support check LASX instructions
> target/loongarch: Add avail_LASX to check LASX instructions
> target/loongarch: Implement xvadd/xvsub
> target/loongarch: Implement xvreplgr2vr
> target/loongarch: Implement xvaddi/xvsubi
> target/loongarch: Implement xvneg
> target/loongarch: Implement xvsadd/xvssub
> target/loongarch: Implement xvhaddw/xvhsubw
> target/loongarch: Implement xvaddw/xvsubw
> target/loongarch: Implement xavg/xvagr
> target/loongarch: Implement xvabsd
> target/loongarch: Implement xvadda
> target/loongarch: Implement xvmax/xvmin
> target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
> target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
> target/loongarch; Implement xvdiv/xvmod
> target/loongarch: Implement xvsat
> target/loongarch: Implement xvexth
> target/loongarch: Implement vext2xv
> target/loongarch: Implement xvsigncov
> target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz
> target/loognarch: Implement xvldi
> target/loongarch: Implement LASX logic instructions
> target/loongarch: Implement xvsll xvsrl xvsra xvrotr
> target/loongarch: Implement xvsllwil xvextl
> target/loongarch: Implement xvsrlr xvsrar
> target/loongarch: Implement xvsrln xvsran
> target/loongarch: Implement xvsrlrn xvsrarn
> target/loongarch: Implement xvssrln xvssran
> target/loongarch: Implement xvssrlrn xvssrarn
> target/loongarch: Implement xvclo xvclz
> target/loongarch: Implement xvpcnt
> target/loongarch: Implement xvbitclr xvbitset xvbitrev
> target/loongarch: Implement xvfrstp
> target/loongarch: Implement LASX fpu arith instructions
> target/loongarch: Implement LASX fpu fcvt instructions
> target/loongarch: Implement xvseq xvsle xvslt
> target/loongarch: Implement xvfcmp
> target/loongarch: Implement xvbitsel xvset
> target/loongarch: Implement xvinsgr2vr xvpickve2gr
> target/loongarch: Implement xvreplve xvinsve0 xvpickve
> target/loongarch: Implement xvpack xvpick xvilv{l/h}
> target/loongarch: Implement xvshuf xvperm{i} xvshuf4i
> target/loongarch: Implement xvld xvst
> target/loongarch: Move simply DO_XX marcos togther
> target/loongarch: CPUCFG support LASX
>
> target/loongarch/cpu.h | 26 +-
> target/loongarch/helper.h | 689 ++--
> target/loongarch/internals.h | 22 -
> target/loongarch/translate.h | 1 +
> target/loongarch/vec.h | 75 +
> target/loongarch/insns.decode | 782 ++++
> linux-user/loongarch64/signal.c | 1 +
> target/loongarch/cpu.c | 4 +
> target/loongarch/disas.c | 924 +++++
> target/loongarch/gdbstub.c | 1 +
> target/loongarch/lsx_helper.c | 3004 --------------
> target/loongarch/machine.c | 36 +-
> target/loongarch/translate.c | 7 +-
> target/loongarch/vec_helper.c | 3508 +++++++++++++++++
> .../{trans_lsx.c.inc => trans_vec.c.inc} | 2413 +++++++++---
> target/loongarch/meson.build | 2 +-
> 16 files changed, 7669 insertions(+), 3826 deletions(-)
> create mode 100644 target/loongarch/vec.h
> delete mode 100644 target/loongarch/lsx_helper.c
> create mode 100644 target/loongarch/vec_helper.c
> rename target/loongarch/insn_trans/{trans_lsx.c.inc => trans_vec.c.inc} (62%)
>