docs/devel/tcg-ops.rst | 15 +- accel/tcg/atomic_template.h | 16 +- include/exec/cpu-all.h | 4 +- include/exec/cpu_ldst.h | 28 +-- include/sysemu/hvf.h | 12 +- include/sysemu/kvm.h | 12 +- include/tcg/tcg-op-common.h | 4 + include/tcg/tcg-op.h | 2 + include/tcg/tcg-opc.h | 6 +- include/tcg/tcg.h | 4 +- tcg/aarch64/tcg-target.h | 5 +- tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target-con-set.h | 2 +- tcg/i386/tcg-target-con-str.h | 1 - tcg/i386/tcg-target.h | 9 +- tcg/loongarch64/tcg-target.h | 6 +- tcg/mips/tcg-target.h | 5 +- tcg/ppc/tcg-target.h | 5 +- tcg/riscv/tcg-target.h | 5 +- tcg/s390x/tcg-target.h | 5 +- tcg/sparc64/tcg-target.h | 5 +- tcg/tci/tcg-target.h | 5 +- accel/hvf/hvf-accel-ops.c | 4 +- accel/hvf/hvf-all.c | 2 +- accel/kvm/kvm-all.c | 3 +- accel/tcg/cputlb.c | 17 +- target/alpha/translate.c | 7 +- target/arm/hvf/hvf.c | 4 +- target/arm/kvm64.c | 6 +- target/arm/tcg/translate-a64.c | 22 +-- target/arm/tcg/translate.c | 12 +- target/cris/translate.c | 20 +- target/i386/hvf/hvf.c | 4 +- target/i386/kvm/kvm.c | 8 +- target/m68k/translate.c | 35 ++-- target/openrisc/translate.c | 6 +- target/ppc/kvm.c | 13 +- target/riscv/vector_helper.c | 2 +- target/rx/op_helper.c | 6 +- target/s390x/kvm/kvm.c | 6 +- target/sparc/translate.c | 17 +- target/tricore/translate.c | 16 +- tcg/optimize.c | 78 +++++++- tcg/tcg-op-gvec.c | 6 +- tcg/tcg-op.c | 151 ++++++++++++--- tcg/tcg.c | 9 +- target/ppc/translate/fixedpoint-impl.c.inc | 6 +- target/ppc/translate/vmx-impl.c.inc | 8 +- tcg/aarch64/tcg-target.c.inc | 14 +- tcg/arm/tcg-target.c.inc | 19 +- tcg/i386/tcg-target.c.inc | 291 ++++++++++++++++++----------- tcg/ppc/tcg-target.c.inc | 149 ++++++++++----- tcg/riscv/tcg-target.c.inc | 49 ++++- tcg/s390x/tcg-target.c.inc | 78 +++++--- tcg/sparc64/tcg-target.c.inc | 40 +++- 55 files changed, 832 insertions(+), 433 deletions(-)
The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:
Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 10:08:33 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230823-2
for you to fetch changes up to 4daad8d9d6b9d426beb8ce505d2164ba36ea3168:
tcg: spelling fixes (2023-08-24 11:22:42 -0700)
----------------------------------------------------------------
accel/*: Widen pc/saved_insn for *_sw_breakpoint
accel/tcg: Replace remaining target_ulong in system-mode accel
tcg: spelling fixes
tcg: Document bswap, hswap, wswap byte patterns
tcg: Introduce negsetcond opcodes
tcg: Fold deposit with zero to and
tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
tcg/i386: Drop BYTEH deposits for 64-bit
tcg/i386: Allow immediate as input to deposit
target/*: Use tcg_gen_negsetcond_*
----------------------------------------------------------------
Anton Johansson (9):
accel/kvm: Widen pc/saved_insn for kvm_sw_breakpoint
accel/hvf: Widen pc/saved_insn for hvf_sw_breakpoint
sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint
sysemu/hvf: Use vaddr for hvf_arch_[insert|remove]_hw_breakpoint
include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()
include/exec: typedef abi_ptr to vaddr in softmmu
include/exec: Widen tlb_hit/tlb_hit_page()
accel/tcg: Widen address arg in tlb_compare_set()
accel/tcg: Update run_on_cpu_data static assert
Mark Cave-Ayland (1):
docs/devel/tcg-ops: fix missing newlines in "Host vector operations"
Michael Tokarev (1):
tcg: spelling fixes
Philippe Mathieu-Daudé (9):
docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32()
tcg/tcg-op: Document bswap16_i32() byte pattern
tcg/tcg-op: Document bswap16_i64() byte pattern
tcg/tcg-op: Document bswap32_i32() byte pattern
tcg/tcg-op: Document bswap32_i64() byte pattern
tcg/tcg-op: Document bswap64_i64() byte pattern
tcg/tcg-op: Document hswap_i32/64() byte pattern
tcg/tcg-op: Document wswap_i64() byte pattern
target/cris: Fix a typo in gen_swapr()
Richard Henderson (28):
target/m68k: Use tcg_gen_deposit_i32 in gen_partset_reg
tcg/i386: Drop BYTEH deposits for 64-bit
tcg: Fold deposit with zero to and
tcg/i386: Allow immediate as input to deposit_*
tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
tcg: Introduce negsetcond opcodes
tcg: Use tcg_gen_negsetcond_*
target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero
target/arm: Use tcg_gen_negsetcond_*
target/m68k: Use tcg_gen_negsetcond_*
target/openrisc: Use tcg_gen_negsetcond_*
target/ppc: Use tcg_gen_negsetcond_*
target/sparc: Use tcg_gen_movcond_i64 in gen_edge
target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl
tcg/ppc: Implement negsetcond_*
tcg/ppc: Use the Set Boolean Extension
tcg/aarch64: Implement negsetcond_*
tcg/arm: Implement negsetcond_i32
tcg/riscv: Implement negsetcond_*
tcg/s390x: Implement negsetcond_*
tcg/sparc64: Implement negsetcond_*
tcg/i386: Merge tcg_out_brcond{32,64}
tcg/i386: Merge tcg_out_setcond{32,64}
tcg/i386: Merge tcg_out_movcond{32,64}
tcg/i386: Use CMP+SBB in tcg_out_setcond
tcg/i386: Clear dest first in tcg_out_setcond if possible
tcg/i386: Use shift in tcg_out_setcond
tcg/i386: Implement negsetcond_*
docs/devel/tcg-ops.rst | 15 +-
accel/tcg/atomic_template.h | 16 +-
include/exec/cpu-all.h | 4 +-
include/exec/cpu_ldst.h | 28 +--
include/sysemu/hvf.h | 12 +-
include/sysemu/kvm.h | 12 +-
include/tcg/tcg-op-common.h | 4 +
include/tcg/tcg-op.h | 2 +
include/tcg/tcg-opc.h | 6 +-
include/tcg/tcg.h | 4 +-
tcg/aarch64/tcg-target.h | 5 +-
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target-con-set.h | 2 +-
tcg/i386/tcg-target-con-str.h | 1 -
tcg/i386/tcg-target.h | 9 +-
tcg/loongarch64/tcg-target.h | 6 +-
tcg/mips/tcg-target.h | 5 +-
tcg/ppc/tcg-target.h | 5 +-
tcg/riscv/tcg-target.h | 5 +-
tcg/s390x/tcg-target.h | 5 +-
tcg/sparc64/tcg-target.h | 5 +-
tcg/tci/tcg-target.h | 5 +-
accel/hvf/hvf-accel-ops.c | 4 +-
accel/hvf/hvf-all.c | 2 +-
accel/kvm/kvm-all.c | 3 +-
accel/tcg/cputlb.c | 17 +-
target/alpha/translate.c | 7 +-
target/arm/hvf/hvf.c | 4 +-
target/arm/kvm64.c | 6 +-
target/arm/tcg/translate-a64.c | 22 +--
target/arm/tcg/translate.c | 12 +-
target/cris/translate.c | 20 +-
target/i386/hvf/hvf.c | 4 +-
target/i386/kvm/kvm.c | 8 +-
target/m68k/translate.c | 35 ++--
target/openrisc/translate.c | 6 +-
target/ppc/kvm.c | 13 +-
target/riscv/vector_helper.c | 2 +-
target/rx/op_helper.c | 6 +-
target/s390x/kvm/kvm.c | 6 +-
target/sparc/translate.c | 17 +-
target/tricore/translate.c | 16 +-
tcg/optimize.c | 78 +++++++-
tcg/tcg-op-gvec.c | 6 +-
tcg/tcg-op.c | 151 ++++++++++++---
tcg/tcg.c | 9 +-
target/ppc/translate/fixedpoint-impl.c.inc | 6 +-
target/ppc/translate/vmx-impl.c.inc | 8 +-
tcg/aarch64/tcg-target.c.inc | 14 +-
tcg/arm/tcg-target.c.inc | 19 +-
tcg/i386/tcg-target.c.inc | 291 ++++++++++++++++++-----------
tcg/ppc/tcg-target.c.inc | 149 ++++++++++-----
tcg/riscv/tcg-target.c.inc | 49 ++++-
tcg/s390x/tcg-target.c.inc | 78 +++++---
tcg/sparc64/tcg-target.c.inc | 40 +++-
55 files changed, 832 insertions(+), 433 deletions(-)
On Thu, 24 Aug 2023 at 14:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:
>
> Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 10:08:33 -0400)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230823-2
>
> for you to fetch changes up to 4daad8d9d6b9d426beb8ce505d2164ba36ea3168:
>
> tcg: spelling fixes (2023-08-24 11:22:42 -0700)
>
> ----------------------------------------------------------------
> accel/*: Widen pc/saved_insn for *_sw_breakpoint
> accel/tcg: Replace remaining target_ulong in system-mode accel
> tcg: spelling fixes
> tcg: Document bswap, hswap, wswap byte patterns
> tcg: Introduce negsetcond opcodes
> tcg: Fold deposit with zero to and
> tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
> tcg/i386: Drop BYTEH deposits for 64-bit
> tcg/i386: Allow immediate as input to deposit
> target/*: Use tcg_gen_negsetcond_*
Hi Richard,
I'm seeing a segfault in "make docker-test-tcg@debian-tricore-cross"
after this pull request.
Note that it has already been merged into qemu.git/master. CI actually
caught it but I accidentally pushed staging to master.
Stefan
>
> ----------------------------------------------------------------
> Anton Johansson (9):
> accel/kvm: Widen pc/saved_insn for kvm_sw_breakpoint
> accel/hvf: Widen pc/saved_insn for hvf_sw_breakpoint
> sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint
> sysemu/hvf: Use vaddr for hvf_arch_[insert|remove]_hw_breakpoint
> include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()
> include/exec: typedef abi_ptr to vaddr in softmmu
> include/exec: Widen tlb_hit/tlb_hit_page()
> accel/tcg: Widen address arg in tlb_compare_set()
> accel/tcg: Update run_on_cpu_data static assert
>
> Mark Cave-Ayland (1):
> docs/devel/tcg-ops: fix missing newlines in "Host vector operations"
>
> Michael Tokarev (1):
> tcg: spelling fixes
>
> Philippe Mathieu-Daudé (9):
> docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32()
> tcg/tcg-op: Document bswap16_i32() byte pattern
> tcg/tcg-op: Document bswap16_i64() byte pattern
> tcg/tcg-op: Document bswap32_i32() byte pattern
> tcg/tcg-op: Document bswap32_i64() byte pattern
> tcg/tcg-op: Document bswap64_i64() byte pattern
> tcg/tcg-op: Document hswap_i32/64() byte pattern
> tcg/tcg-op: Document wswap_i64() byte pattern
> target/cris: Fix a typo in gen_swapr()
>
> Richard Henderson (28):
> target/m68k: Use tcg_gen_deposit_i32 in gen_partset_reg
> tcg/i386: Drop BYTEH deposits for 64-bit
> tcg: Fold deposit with zero to and
> tcg/i386: Allow immediate as input to deposit_*
> tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
> tcg: Introduce negsetcond opcodes
> tcg: Use tcg_gen_negsetcond_*
> target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero
> target/arm: Use tcg_gen_negsetcond_*
> target/m68k: Use tcg_gen_negsetcond_*
> target/openrisc: Use tcg_gen_negsetcond_*
> target/ppc: Use tcg_gen_negsetcond_*
> target/sparc: Use tcg_gen_movcond_i64 in gen_edge
> target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl
> tcg/ppc: Implement negsetcond_*
> tcg/ppc: Use the Set Boolean Extension
> tcg/aarch64: Implement negsetcond_*
> tcg/arm: Implement negsetcond_i32
> tcg/riscv: Implement negsetcond_*
> tcg/s390x: Implement negsetcond_*
> tcg/sparc64: Implement negsetcond_*
> tcg/i386: Merge tcg_out_brcond{32,64}
> tcg/i386: Merge tcg_out_setcond{32,64}
> tcg/i386: Merge tcg_out_movcond{32,64}
> tcg/i386: Use CMP+SBB in tcg_out_setcond
> tcg/i386: Clear dest first in tcg_out_setcond if possible
> tcg/i386: Use shift in tcg_out_setcond
> tcg/i386: Implement negsetcond_*
>
> docs/devel/tcg-ops.rst | 15 +-
> accel/tcg/atomic_template.h | 16 +-
> include/exec/cpu-all.h | 4 +-
> include/exec/cpu_ldst.h | 28 +--
> include/sysemu/hvf.h | 12 +-
> include/sysemu/kvm.h | 12 +-
> include/tcg/tcg-op-common.h | 4 +
> include/tcg/tcg-op.h | 2 +
> include/tcg/tcg-opc.h | 6 +-
> include/tcg/tcg.h | 4 +-
> tcg/aarch64/tcg-target.h | 5 +-
> tcg/arm/tcg-target.h | 1 +
> tcg/i386/tcg-target-con-set.h | 2 +-
> tcg/i386/tcg-target-con-str.h | 1 -
> tcg/i386/tcg-target.h | 9 +-
> tcg/loongarch64/tcg-target.h | 6 +-
> tcg/mips/tcg-target.h | 5 +-
> tcg/ppc/tcg-target.h | 5 +-
> tcg/riscv/tcg-target.h | 5 +-
> tcg/s390x/tcg-target.h | 5 +-
> tcg/sparc64/tcg-target.h | 5 +-
> tcg/tci/tcg-target.h | 5 +-
> accel/hvf/hvf-accel-ops.c | 4 +-
> accel/hvf/hvf-all.c | 2 +-
> accel/kvm/kvm-all.c | 3 +-
> accel/tcg/cputlb.c | 17 +-
> target/alpha/translate.c | 7 +-
> target/arm/hvf/hvf.c | 4 +-
> target/arm/kvm64.c | 6 +-
> target/arm/tcg/translate-a64.c | 22 +--
> target/arm/tcg/translate.c | 12 +-
> target/cris/translate.c | 20 +-
> target/i386/hvf/hvf.c | 4 +-
> target/i386/kvm/kvm.c | 8 +-
> target/m68k/translate.c | 35 ++--
> target/openrisc/translate.c | 6 +-
> target/ppc/kvm.c | 13 +-
> target/riscv/vector_helper.c | 2 +-
> target/rx/op_helper.c | 6 +-
> target/s390x/kvm/kvm.c | 6 +-
> target/sparc/translate.c | 17 +-
> target/tricore/translate.c | 16 +-
> tcg/optimize.c | 78 +++++++-
> tcg/tcg-op-gvec.c | 6 +-
> tcg/tcg-op.c | 151 ++++++++++++---
> tcg/tcg.c | 9 +-
> target/ppc/translate/fixedpoint-impl.c.inc | 6 +-
> target/ppc/translate/vmx-impl.c.inc | 8 +-
> tcg/aarch64/tcg-target.c.inc | 14 +-
> tcg/arm/tcg-target.c.inc | 19 +-
> tcg/i386/tcg-target.c.inc | 291 ++++++++++++++++++-----------
> tcg/ppc/tcg-target.c.inc | 149 ++++++++++-----
> tcg/riscv/tcg-target.c.inc | 49 ++++-
> tcg/s390x/tcg-target.c.inc | 78 +++++---
> tcg/sparc64/tcg-target.c.inc | 40 +++-
> 55 files changed, 832 insertions(+), 433 deletions(-)
>
On Mon, Aug 28, 2023 at 06:52:42PM -0400, Stefan Hajnoczi wrote:
> On Thu, 24 Aug 2023 at 14:29, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:
> >
> > Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 10:08:33 -0400)
> >
> > are available in the Git repository at:
> >
> > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230823-2
> >
> > for you to fetch changes up to 4daad8d9d6b9d426beb8ce505d2164ba36ea3168:
> >
> > tcg: spelling fixes (2023-08-24 11:22:42 -0700)
> >
> > ----------------------------------------------------------------
> > accel/*: Widen pc/saved_insn for *_sw_breakpoint
> > accel/tcg: Replace remaining target_ulong in system-mode accel
> > tcg: spelling fixes
> > tcg: Document bswap, hswap, wswap byte patterns
> > tcg: Introduce negsetcond opcodes
> > tcg: Fold deposit with zero to and
> > tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
> > tcg/i386: Drop BYTEH deposits for 64-bit
> > tcg/i386: Allow immediate as input to deposit
> > target/*: Use tcg_gen_negsetcond_*
>
> Hi Richard,
> I'm seeing a segfault in "make docker-test-tcg@debian-tricore-cross"
> after this pull request.
git bisect points to:
commit fc15bfb6a6bda8d4d01f1383579d385acae17c0f
Author: Anton Johansson <anjo@rev.ng>
Date: Mon Aug 7 17:57:03 2023 +0200
include/exec: typedef abi_ptr to vaddr in softmmu
In system mode, abi_ptr is primarily used for representing addresses
when accessing guest memory with cpu_[st|ld]*(). Widening it from
target_ulong to vaddr reduces the target dependence of these functions
and is step towards building accel/ once for system mode.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230807155706.9580-7-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index da10ba1433..f3ce4eb1d0 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
h2g_nocheck(x); \
})
#else
-typedef target_ulong abi_ptr;
-#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
+typedef vaddr abi_ptr;
+#define TARGET_ABI_FMT_ptr "%016" VADDR_PRIx
#endif
Changeing typedef vaddr abi_ptr back to target_ulong fixes it.
The faulting TriCore insn is OPC1_32_BOL_ST_W_LONGOFF, that tries to write to
guest addr 0xd0000124, which is in a valid memory region.
Cheers,
Bastian
On 8/28/23 23:17, Bastian Koppelmann wrote:
>> I'm seeing a segfault in "make docker-test-tcg@debian-tricore-cross"
>> after this pull request.
>
> git bisect points to:
>
> commit fc15bfb6a6bda8d4d01f1383579d385acae17c0f
> Author: Anton Johansson <anjo@rev.ng>
> Date: Mon Aug 7 17:57:03 2023 +0200
>
> include/exec: typedef abi_ptr to vaddr in softmmu
>
> In system mode, abi_ptr is primarily used for representing addresses
> when accessing guest memory with cpu_[st|ld]*(). Widening it from
> target_ulong to vaddr reduces the target dependence of these functions
> and is step towards building accel/ once for system mode.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Message-Id: <20230807155706.9580-7-anjo@rev.ng>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
> index da10ba1433..f3ce4eb1d0 100644
> --- a/include/exec/cpu_ldst.h
> +++ b/include/exec/cpu_ldst.h
> @@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
> h2g_nocheck(x); \
> })
> #else
> -typedef target_ulong abi_ptr;
> -#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
> +typedef vaddr abi_ptr;
> +#define TARGET_ABI_FMT_ptr "%016" VADDR_PRIx
> #endif
>
>
> Changeing typedef vaddr abi_ptr back to target_ulong fixes it.
>
> The faulting TriCore insn is OPC1_32_BOL_ST_W_LONGOFF, that tries to write to
> guest addr 0xd0000124, which is in a valid memory region.
Right. The traceback is
#6 0x000055555582c511 in mmu_lookup
(env=0x555555e98ee0, addr=18446744072904253376, oi=32, ra=0, type=MMU_DATA_STORE,
l=0x7ffff1888cc0) at ../src/accel/tcg/cputlb.c:1828
#7 0x000055555582f531 in do_st4_mmu
(env=0x555555e98ee0, addr=18446744072904253376, val=0, oi=32, ra=0)
at ../src/accel/tcg/cputlb.c:2991
#8 0x000055555582fe59 in cpu_stl_mmu
(env=0x555555e98ee0, addr=18446744072904253376, val=0, oi=32, retaddr=0)
at ../src/accel/tcg/cputlb.c:3138
#9 0x000055555583041d in cpu_stl_le_mmuidx_ra
(env=0x555555e98ee0, addr=18446744072904253376, val=0, mmu_idx=0, ra=0)
at ../src/accel/tcg/ldst_common.c.inc:118
#10 0x00005555558308b5 in cpu_stl_le_data_ra
(env=0x555555e98ee0, addr=18446744072904253376, val=0, ra=0)
at ../src/accel/tcg/ldst_common.c.inc:213
#11 0x0000555555830bf2 in cpu_stl_le_data
(env=0x555555e98ee0, addr=18446744072904253376, val=0)
at ../src/accel/tcg/ldst_common.c.inc:301
#12 0x00005555557a2ce2 in save_context_upper
(env=0x555555e98ee0, ea=-805298240)
at ../src/target/tricore/op_helper.c:2400
#13 0x00005555557a35ee in helper_call (env=0x555555e98ee0, next_pc=2147484092)
at ../src/target/tricore/op_helper.c:2519
With
void save_context_upper(CPUTriCoreState *env, int ea)
providing the signed address variable, which gets extended to 64-bits with the change to
abi_ptr instead of converted to unsigned 32-bits in cpu_stl_le_data.
For the short-term, let's revert this patch.
r~
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
Dangit, missed the PULL tag for v2.
The only change is fixing Anton's --author.
r~
On 8/24/23 11:28, Richard Henderson wrote:
> The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:
>
> Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 10:08:33 -0400)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230823-2
>
> for you to fetch changes up to 4daad8d9d6b9d426beb8ce505d2164ba36ea3168:
>
> tcg: spelling fixes (2023-08-24 11:22:42 -0700)
>
> ----------------------------------------------------------------
> accel/*: Widen pc/saved_insn for *_sw_breakpoint
> accel/tcg: Replace remaining target_ulong in system-mode accel
> tcg: spelling fixes
> tcg: Document bswap, hswap, wswap byte patterns
> tcg: Introduce negsetcond opcodes
> tcg: Fold deposit with zero to and
> tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
> tcg/i386: Drop BYTEH deposits for 64-bit
> tcg/i386: Allow immediate as input to deposit
> target/*: Use tcg_gen_negsetcond_*
>
> ----------------------------------------------------------------
> Anton Johansson (9):
> accel/kvm: Widen pc/saved_insn for kvm_sw_breakpoint
> accel/hvf: Widen pc/saved_insn for hvf_sw_breakpoint
> sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint
> sysemu/hvf: Use vaddr for hvf_arch_[insert|remove]_hw_breakpoint
> include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()
> include/exec: typedef abi_ptr to vaddr in softmmu
> include/exec: Widen tlb_hit/tlb_hit_page()
> accel/tcg: Widen address arg in tlb_compare_set()
> accel/tcg: Update run_on_cpu_data static assert
>
> Mark Cave-Ayland (1):
> docs/devel/tcg-ops: fix missing newlines in "Host vector operations"
>
> Michael Tokarev (1):
> tcg: spelling fixes
>
> Philippe Mathieu-Daudé (9):
> docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32()
> tcg/tcg-op: Document bswap16_i32() byte pattern
> tcg/tcg-op: Document bswap16_i64() byte pattern
> tcg/tcg-op: Document bswap32_i32() byte pattern
> tcg/tcg-op: Document bswap32_i64() byte pattern
> tcg/tcg-op: Document bswap64_i64() byte pattern
> tcg/tcg-op: Document hswap_i32/64() byte pattern
> tcg/tcg-op: Document wswap_i64() byte pattern
> target/cris: Fix a typo in gen_swapr()
>
> Richard Henderson (28):
> target/m68k: Use tcg_gen_deposit_i32 in gen_partset_reg
> tcg/i386: Drop BYTEH deposits for 64-bit
> tcg: Fold deposit with zero to and
> tcg/i386: Allow immediate as input to deposit_*
> tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
> tcg: Introduce negsetcond opcodes
> tcg: Use tcg_gen_negsetcond_*
> target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero
> target/arm: Use tcg_gen_negsetcond_*
> target/m68k: Use tcg_gen_negsetcond_*
> target/openrisc: Use tcg_gen_negsetcond_*
> target/ppc: Use tcg_gen_negsetcond_*
> target/sparc: Use tcg_gen_movcond_i64 in gen_edge
> target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl
> tcg/ppc: Implement negsetcond_*
> tcg/ppc: Use the Set Boolean Extension
> tcg/aarch64: Implement negsetcond_*
> tcg/arm: Implement negsetcond_i32
> tcg/riscv: Implement negsetcond_*
> tcg/s390x: Implement negsetcond_*
> tcg/sparc64: Implement negsetcond_*
> tcg/i386: Merge tcg_out_brcond{32,64}
> tcg/i386: Merge tcg_out_setcond{32,64}
> tcg/i386: Merge tcg_out_movcond{32,64}
> tcg/i386: Use CMP+SBB in tcg_out_setcond
> tcg/i386: Clear dest first in tcg_out_setcond if possible
> tcg/i386: Use shift in tcg_out_setcond
> tcg/i386: Implement negsetcond_*
>
> docs/devel/tcg-ops.rst | 15 +-
> accel/tcg/atomic_template.h | 16 +-
> include/exec/cpu-all.h | 4 +-
> include/exec/cpu_ldst.h | 28 +--
> include/sysemu/hvf.h | 12 +-
> include/sysemu/kvm.h | 12 +-
> include/tcg/tcg-op-common.h | 4 +
> include/tcg/tcg-op.h | 2 +
> include/tcg/tcg-opc.h | 6 +-
> include/tcg/tcg.h | 4 +-
> tcg/aarch64/tcg-target.h | 5 +-
> tcg/arm/tcg-target.h | 1 +
> tcg/i386/tcg-target-con-set.h | 2 +-
> tcg/i386/tcg-target-con-str.h | 1 -
> tcg/i386/tcg-target.h | 9 +-
> tcg/loongarch64/tcg-target.h | 6 +-
> tcg/mips/tcg-target.h | 5 +-
> tcg/ppc/tcg-target.h | 5 +-
> tcg/riscv/tcg-target.h | 5 +-
> tcg/s390x/tcg-target.h | 5 +-
> tcg/sparc64/tcg-target.h | 5 +-
> tcg/tci/tcg-target.h | 5 +-
> accel/hvf/hvf-accel-ops.c | 4 +-
> accel/hvf/hvf-all.c | 2 +-
> accel/kvm/kvm-all.c | 3 +-
> accel/tcg/cputlb.c | 17 +-
> target/alpha/translate.c | 7 +-
> target/arm/hvf/hvf.c | 4 +-
> target/arm/kvm64.c | 6 +-
> target/arm/tcg/translate-a64.c | 22 +--
> target/arm/tcg/translate.c | 12 +-
> target/cris/translate.c | 20 +-
> target/i386/hvf/hvf.c | 4 +-
> target/i386/kvm/kvm.c | 8 +-
> target/m68k/translate.c | 35 ++--
> target/openrisc/translate.c | 6 +-
> target/ppc/kvm.c | 13 +-
> target/riscv/vector_helper.c | 2 +-
> target/rx/op_helper.c | 6 +-
> target/s390x/kvm/kvm.c | 6 +-
> target/sparc/translate.c | 17 +-
> target/tricore/translate.c | 16 +-
> tcg/optimize.c | 78 +++++++-
> tcg/tcg-op-gvec.c | 6 +-
> tcg/tcg-op.c | 151 ++++++++++++---
> tcg/tcg.c | 9 +-
> target/ppc/translate/fixedpoint-impl.c.inc | 6 +-
> target/ppc/translate/vmx-impl.c.inc | 8 +-
> tcg/aarch64/tcg-target.c.inc | 14 +-
> tcg/arm/tcg-target.c.inc | 19 +-
> tcg/i386/tcg-target.c.inc | 291 ++++++++++++++++++-----------
> tcg/ppc/tcg-target.c.inc | 149 ++++++++++-----
> tcg/riscv/tcg-target.c.inc | 49 ++++-
> tcg/s390x/tcg-target.c.inc | 78 +++++---
> tcg/sparc64/tcg-target.c.inc | 40 +++-
> 55 files changed, 832 insertions(+), 433 deletions(-)
© 2016 - 2024 Red Hat, Inc.