target/loongarch: Sign-extend REVB.2H result

[RFC PATCH] target/loongarch: Sign-extend REVB.2H result

Posted by Philippe Mathieu-Daudé 8 months, 4 weeks ago

Per [*]:

  The REVB.2H instruction performs [...] and write the 32-bit
  intermediate result sign extended to the general register 'rd'.

Add the missing sign extension.

[*] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_revb_2h4h2wd

Fixes: ad08cb3f97 ("target/loongarch: Add fixed point bit instruction translation")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
RFC: Totally untested, only noticed during code review.
---
 target/loongarch/insn_trans/trans_bit.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
index 25b4d7858b..a98c46d8cb 100644
--- a/target/loongarch/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
@@ -121,7 +121,8 @@ static void gen_revb_2h(TCGv dest, TCGv src1)
     tcg_gen_and_tl(t0, t0, mask);
     tcg_gen_and_tl(t1, src1, mask);
     tcg_gen_shli_tl(t1, t1, 8);
-    tcg_gen_or_tl(dest, t0, t1);
+    tcg_gen_or_tl(t0, t0, t1);
+    tcg_gen_ext32s_tl(dest, t0);
 }
 
 static void gen_revb_4h(TCGv dest, TCGv src1)
-- 
2.41.0

Re: [RFC PATCH] target/loongarch: Sign-extend REVB.2H result

Posted by Richard Henderson 8 months, 4 weeks ago

On 8/22/23 09:47, Philippe Mathieu-Daudé wrote:
> Per [*]:
> 
>    The REVB.2H instruction performs [...] and write the 32-bit
>    intermediate result sign extended to the general register 'rd'.
> 
> Add the missing sign extension.
> 
> [*] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_revb_2h4h2wd
> 
> Fixes: ad08cb3f97 ("target/loongarch: Add fixed point bit instruction translation")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> RFC: Totally untested, only noticed during code review.
> ---
>   target/loongarch/insn_trans/trans_bit.c.inc | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
> index 25b4d7858b..a98c46d8cb 100644
> --- a/target/loongarch/insn_trans/trans_bit.c.inc
> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
> @@ -121,7 +121,8 @@ static void gen_revb_2h(TCGv dest, TCGv src1)
>       tcg_gen_and_tl(t0, t0, mask);
>       tcg_gen_and_tl(t1, src1, mask);
>       tcg_gen_shli_tl(t1, t1, 8);
> -    tcg_gen_or_tl(dest, t0, t1);
> +    tcg_gen_or_tl(t0, t0, t1);
> +    tcg_gen_ext32s_tl(dest, t0);
>   }

Nack.  This is handled via EXT_SIGN in

TRANS(revb_2h, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)



r~