[PATCH 5/6] target/mips: Use hswap_i64() in DSHD opcode

Philippe Mathieu-Daudé posted 6 patches 2 years, 5 months ago
[PATCH 5/6] target/mips: Use hswap_i64() in DSHD opcode
Posted by Philippe Mathieu-Daudé 2 years, 5 months ago
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it in gen_bshfl().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 9bb40f1849..4f34ea9b6a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -4948,19 +4948,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
         }
         break;
     case OPC_DSHD:
-        {
-            TCGv t1 = tcg_temp_new();
-            TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL);
-
-            tcg_gen_shri_tl(t1, t0, 16);
-            tcg_gen_and_tl(t1, t1, t2);
-            tcg_gen_and_tl(t0, t0, t2);
-            tcg_gen_shli_tl(t0, t0, 16);
-            tcg_gen_or_tl(t0, t0, t1);
-            tcg_gen_shri_tl(t1, t0, 32);
-            tcg_gen_shli_tl(t0, t0, 32);
-            tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
-        }
+        tcg_gen_hswap_i64(cpu_gpr[rd], t0);
         break;
 #endif
     default:
-- 
2.41.0


Re: [PATCH 5/6] target/mips: Use hswap_i64() in DSHD opcode
Posted by Peter Maydell 2 years, 5 months ago
On Tue, 22 Aug 2023 at 12:02, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
> introduced the generic hswap_i32(). Use it instead of open-coding
> it in gen_bshfl().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/mips/tcg/translate.c | 14 +-------------
>  1 file changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index 9bb40f1849..4f34ea9b6a 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -4948,19 +4948,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
>          }
>          break;
>      case OPC_DSHD:
> -        {
> -            TCGv t1 = tcg_temp_new();
> -            TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL);
> -
> -            tcg_gen_shri_tl(t1, t0, 16);
> -            tcg_gen_and_tl(t1, t1, t2);
> -            tcg_gen_and_tl(t0, t0, t2);
> -            tcg_gen_shli_tl(t0, t0, 16);
> -            tcg_gen_or_tl(t0, t0, t1);
> -            tcg_gen_shri_tl(t1, t0, 32);
> -            tcg_gen_shli_tl(t0, t0, 32);
> -            tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
> -        }
> +        tcg_gen_hswap_i64(cpu_gpr[rd], t0);

We know that target_long here is 64 bits, but for consistency
with the rest of the function maybe tcg_gen_hswap_tl()
is better? I'm not sure...

thanks
-- PMM