[PULL 0/6] target-arm queue
[PULL v2 00/29] target-arm queue
1
Hi; here's a target-arm pull for rc2. Four arm-related fixes,
1
v2: drop pvpanic-pci patches.
2
and a couple of bug fixes for other areas of the codebase
3
that seemed like they'd fallen through the cracks.
4
2
5
thanks
3
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
6
-- PMM
7
4
8
The following changes since commit ccb86f079a9e4d94918086a9df18c1844347aff8:
5
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
9
10
Merge tag 'pull-nbd-2023-07-28' of https://repo.or.cz/qemu/ericb into staging (2023-07-28 09:56:57 -0700)
11
6
12
are available in the Git repository at:
7
are available in the Git repository at:
13
8
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230731
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
15
10
16
for you to fetch changes up to 108e8180c6b0c315711aa54e914030a313505c17:
11
for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
17
12
18
gdbstub: Fix client Ctrl-C handling (2023-07-31 14:57:32 +0100)
13
docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
19
14
20
----------------------------------------------------------------
15
----------------------------------------------------------------
21
target-arm queue:
16
target-arm queue:
22
* Don't build AArch64 decodetree files for qemu-system-arm
17
* Implement IMPDEF pauth algorithm
23
* Fix TCG assert in v8.1M CSEL etc
18
* Support ARMv8.4-SEL2
24
* Fix MemOp for STGP
19
* Fix bug where we were truncating predicate vector lengths in SVE insns
25
* gdbstub: Fix client Ctrl-C handling
20
* npcm7xx_adc-test: Fix memleak in adc_qom_set
26
* kvm: Fix crash due to access uninitialized kvm_state
21
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
27
* elf2dmp: Don't abandon when Prcb is set to 0
22
* docs: Build and install all the docs in a single manual
28
23
29
----------------------------------------------------------------
24
----------------------------------------------------------------
30
Akihiko Odaki (1):
25
Gan Qixin (1):
31
elf2dmp: Don't abandon when Prcb is set to 0
26
npcm7xx_adc-test: Fix memleak in adc_qom_set
32
27
33
Gavin Shan (1):
28
Peter Maydell (1):
34
kvm: Fix crash due to access uninitialized kvm_state
29
docs: Build and install all the docs in a single manual
35
30
36
Nicholas Piggin (1):
31
Philippe Mathieu-Daudé (1):
37
gdbstub: Fix client Ctrl-C handling
32
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
38
33
39
Peter Maydell (2):
34
Richard Henderson (7):
40
target/arm: Avoid writing to constant TCGv in trans_CSEL()
35
target/arm: Implement an IMPDEF pauth algorithm
41
target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-arm
36
target/arm: Add cpu properties to control pauth
37
target/arm: Use object_property_add_bool for "sve" property
38
target/arm: Introduce PREDDESC field definitions
39
target/arm: Update PFIRST, PNEXT for pred_desc
40
target/arm: Update ZIP, UZP, TRN for pred_desc
41
target/arm: Update REV, PUNPK for pred_desc
42
42
43
Richard Henderson (1):
43
Rémi Denis-Courmont (19):
44
target/arm: Fix MemOp for STGP
44
target/arm: remove redundant tests
45
target/arm: add arm_is_el2_enabled() helper
46
target/arm: use arm_is_el2_enabled() where applicable
47
target/arm: use arm_hcr_el2_eff() where applicable
48
target/arm: factor MDCR_EL2 common handling
49
target/arm: Define isar_feature function to test for presence of SEL2
50
target/arm: add 64-bit S-EL2 to EL exception table
51
target/arm: add MMU stage 1 for Secure EL2
52
target/arm: add ARMv8.4-SEL2 system registers
53
target/arm: handle VMID change in secure state
54
target/arm: do S1_ptw_translate() before address space lookup
55
target/arm: translate NS bit in page-walks
56
target/arm: generalize 2-stage page-walk condition
57
target/arm: secure stage 2 translation regime
58
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
59
target/arm: revector to run-time pick target EL
60
target/arm: Implement SCR_EL2.EEL2
61
target/arm: enable Secure EL2 in max CPU
62
target/arm: refactor vae1_tlbmask()
45
63
46
accel/kvm/kvm-all.c | 2 +-
64
docs/conf.py | 46 ++++-
47
contrib/elf2dmp/main.c | 5 +++++
65
docs/devel/conf.py | 15 --
48
gdbstub/gdbstub.c | 13 +++++++++++--
66
docs/index.html.in | 17 --
49
target/arm/tcg/translate-a64.c | 21 ++++++++++++++++++---
67
docs/interop/conf.py | 28 ---
50
target/arm/tcg/translate.c | 15 ++++++++-------
68
docs/meson.build | 64 +++---
51
target/arm/tcg/meson.build | 10 +++++++---
69
docs/specs/conf.py | 16 --
52
6 files changed, 50 insertions(+), 16 deletions(-)
70
docs/system/arm/cpu-features.rst | 21 ++
71
docs/system/conf.py | 28 ---
72
docs/tools/conf.py | 37 ----
73
docs/user/conf.py | 15 --
74
include/qemu/xxhash.h | 98 +++++++++
75
target/arm/cpu-param.h | 2 +-
76
target/arm/cpu.h | 107 ++++++++--
77
target/arm/internals.h | 45 +++++
78
target/arm/cpu.c | 23 ++-
79
target/arm/cpu64.c | 65 ++++--
80
target/arm/helper-a64.c | 8 +-
81
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
82
target/arm/m_helper.c | 2 +-
83
target/arm/monitor.c | 1 +
84
target/arm/op_helper.c | 4 +-
85
target/arm/pauth_helper.c | 27 ++-
86
target/arm/sve_helper.c | 33 ++--
87
target/arm/tlb_helper.c | 3 +
88
target/arm/translate-a64.c | 4 +
89
target/arm/translate-sve.c | 31 ++-
90
target/arm/translate.c | 36 +++-
91
tests/qtest/arm-cpu-features.c | 13 ++
92
tests/qtest/npcm7xx_adc-test.c | 1 +
93
.gitlab-ci.yml | 4 +-
94
30 files changed, 770 insertions(+), 438 deletions(-)
95
delete mode 100644 docs/devel/conf.py
96
delete mode 100644 docs/index.html.in
97
delete mode 100644 docs/interop/conf.py
98
delete mode 100644 docs/specs/conf.py
99
delete mode 100644 docs/system/conf.py
100
delete mode 100644 docs/tools/conf.py
101
delete mode 100644 docs/user/conf.py
102
diff view generated by jsdifflib
[PULL 1/6] target/arm: Fix MemOp for STGP
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
When converting to decodetree, the code to rebuild mop for the pair
4
only made it into trans_STP and not into trans_STGP.
5
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1790
7
Fixes: 8c212eb6594 ("target/arm: Convert load/store-pair to decodetree")
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230726165416.309624-1-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/tcg/translate-a64.c | 21 ++++++++++++++++++---
14
1 file changed, 18 insertions(+), 3 deletions(-)
15
16
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/translate-a64.c
19
+++ b/target/arm/tcg/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
21
MemOp mop;
22
TCGv_i128 tmp;
23
24
+ /* STGP only comes in one size. */
25
+ tcg_debug_assert(a->sz == MO_64);
26
+
27
if (!dc_isar_feature(aa64_mte_insn_reg, s)) {
28
return false;
29
}
30
@@ -XXX,XX +XXX,XX @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
31
gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
32
}
33
34
- mop = finalize_memop(s, a->sz);
35
- clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz, mop);
36
+ mop = finalize_memop(s, MO_64);
37
+ clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << MO_64, mop);
38
39
tcg_rt = cpu_reg(s, a->rt);
40
tcg_rt2 = cpu_reg(s, a->rt2);
41
42
- assert(a->sz == 3);
43
+ /*
44
+ * STGP is defined as two 8-byte memory operations and one tag operation.
45
+ * We implement it as one single 16-byte memory operation for convenience.
46
+ * Rebuild mop as for STP.
47
+ * TODO: The atomicity with LSE2 is stronger than required.
48
+ * Need a form of MO_ATOM_WITHIN16_PAIR that never requires
49
+ * 16-byte atomicity.
50
+ */
51
+ mop = MO_128;
52
+ if (s->align_mem) {
53
+ mop |= MO_ALIGN_8;
54
+ }
55
+ mop = finalize_memop_pair(s, mop);
56
57
tmp = tcg_temp_new_i128();
58
if (s->be_data == MO_LE) {
59
--
60
2.34.1
diff view generated by jsdifflib
[PULL 2/6] elf2dmp: Don't abandon when Prcb is set to 0
Deleted patch
1
From: Akihiko Odaki <akihiko.odaki@daynix.com>
2
1
3
Prcb may be set to 0 for some CPUs if the dump was taken before they
4
start. The dump may still contain valuable information for started CPUs
5
so don't abandon conversion in such a case.
6
7
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
8
Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
9
Message-id: 20230611033434.14659-1-akihiko.odaki@daynix.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
contrib/elf2dmp/main.c | 5 +++++
13
1 file changed, 5 insertions(+)
14
15
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/contrib/elf2dmp/main.c
18
+++ b/contrib/elf2dmp/main.c
19
@@ -XXX,XX +XXX,XX @@ static int fill_context(KDDEBUGGER_DATA64 *kdbg,
20
return 1;
21
}
22
23
+ if (!Prcb) {
24
+ eprintf("Context for CPU #%d is missing\n", i);
25
+ continue;
26
+ }
27
+
28
if (va_space_rw(vs, Prcb + kdbg->OffsetPrcbContext,
29
&Context, sizeof(Context), 0)) {
30
eprintf("Failed to read CPU #%d ContextFrame location\n", i);
31
--
32
2.34.1
diff view generated by jsdifflib
[PULL 3/6] target/arm: Avoid writing to constant TCGv in trans_CSEL()
Deleted patch
1
In commit 0b188ea05acb5 we changed the implementation of
2
trans_CSEL() to use tcg_constant_i32(). However, this change
3
was incorrect, because the implementation of the function
4
sets up the TCGv_i32 rn and rm to be either zero or else
5
a TCG temp created in load_reg(), and these TCG temps are
6
then in both cases written to by the emitted TCG ops.
7
The result is that we hit a TCG assertion:
8
1
9
qemu-system-arm: ../../tcg/tcg.c:4455: tcg_reg_alloc_mov: Assertion `!temp_readonly(ots)' failed.
10
11
(or on a non-debug build, just produce a garbage result)
12
13
Adjust the code so that rn and rm are always writeable
14
temporaries whether the instruction is using the special
15
case "0" or a normal register as input.
16
17
Cc: qemu-stable@nongnu.org
18
Fixes: 0b188ea05acb5 ("target/arm: Use tcg_constant in trans_CSEL")
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20230727103906.2641264-1-peter.maydell@linaro.org
22
---
23
target/arm/tcg/translate.c | 15 ++++++++-------
24
1 file changed, 8 insertions(+), 7 deletions(-)
25
26
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/tcg/translate.c
29
+++ b/target/arm/tcg/translate.c
30
@@ -XXX,XX +XXX,XX @@ static bool trans_IT(DisasContext *s, arg_IT *a)
31
/* v8.1M CSEL/CSINC/CSNEG/CSINV */
32
static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
33
{
34
- TCGv_i32 rn, rm, zero;
35
+ TCGv_i32 rn, rm;
36
DisasCompare c;
37
38
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
39
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
40
}
41
42
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
43
- zero = tcg_constant_i32(0);
44
+ rn = tcg_temp_new_i32();
45
+ rm = tcg_temp_new_i32();
46
if (a->rn == 15) {
47
- rn = zero;
48
+ tcg_gen_movi_i32(rn, 0);
49
} else {
50
- rn = load_reg(s, a->rn);
51
+ load_reg_var(s, rn, a->rn);
52
}
53
if (a->rm == 15) {
54
- rm = zero;
55
+ tcg_gen_movi_i32(rm, 0);
56
} else {
57
- rm = load_reg(s, a->rm);
58
+ load_reg_var(s, rm, a->rm);
59
}
60
61
switch (a->op) {
62
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
63
}
64
65
arm_test_cc(&c, a->fcond);
66
- tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
67
+ tcg_gen_movcond_i32(c.cond, rn, c.value, tcg_constant_i32(0), rn, rm);
68
69
store_reg(s, a->rd, rn);
70
return true;
71
--
72
2.34.1
diff view generated by jsdifflib
[PULL 4/6] target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-arm
Deleted patch
1
Currently we list all the Arm decodetree files together and add them
2
unconditionally to arm_ss. This means we build them for both
3
qemu-system-aarch64 and qemu-system-arm. However, some of them are
4
AArch64-specific, so there is no need to build them for
5
qemu-system-arm. (Meson is smart enough to notice that the generated
6
.c.inc file is not used by any objects that go into qemu-system-arm,
7
so we only unnecessarily run decodetree, not anything more
8
heavyweight like a recompile or relink, but it's still unnecessary
9
work.)
10
1
11
Split gen into gen_a32 and gen_a64, and only add gen_a64 for
12
TARGET_AARCH64 compiles.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
Message-id: 20230718104628.1137734-1-peter.maydell@linaro.org
17
---
18
target/arm/tcg/meson.build | 10 +++++++---
19
1 file changed, 7 insertions(+), 3 deletions(-)
20
21
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/tcg/meson.build
24
+++ b/target/arm/tcg/meson.build
25
@@ -XXX,XX +XXX,XX @@
26
-gen = [
27
+gen_a64 = [
28
+ decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']),
29
decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
30
decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
31
decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
32
+]
33
+
34
+gen_a32 = [
35
decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
36
decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
37
decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
38
@@ -XXX,XX +XXX,XX @@ gen = [
39
decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
40
decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
41
decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
42
- decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']),
43
]
44
45
-arm_ss.add(gen)
46
+arm_ss.add(gen_a32)
47
+arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
48
49
arm_ss.add(files(
50
'cpu32.c',
51
--
52
2.34.1
53
54
diff view generated by jsdifflib
[PULL 5/6] kvm: Fix crash due to access uninitialized kvm_state
Deleted patch
1
From: Gavin Shan <gshan@redhat.com>
2
1
3
Runs into core dump on arm64 and the backtrace extracted from the
4
core dump is shown as below. It's caused by accessing uninitialized
5
@kvm_state in kvm_flush_coalesced_mmio_buffer() due to commit 176d073029
6
("hw/arm/virt: Use machine_memory_devices_init()"), where the machine's
7
memory region is added earlier than before.
8
9
main
10
qemu_init
11
configure_accelerators
12
qemu_opts_foreach
13
do_configure_accelerator
14
accel_init_machine
15
kvm_init
16
virt_kvm_type
17
virt_set_memmap
18
machine_memory_devices_init
19
memory_region_add_subregion
20
memory_region_add_subregion_common
21
memory_region_update_container_subregions
22
memory_region_transaction_begin
23
qemu_flush_coalesced_mmio_buffer
24
kvm_flush_coalesced_mmio_buffer
25
26
Fix it by bailing early in kvm_flush_coalesced_mmio_buffer() on the
27
uninitialized @kvm_state. With this applied, no crash is observed on
28
arm64.
29
30
Fixes: 176d073029 ("hw/arm/virt: Use machine_memory_devices_init()")
31
Signed-off-by: Gavin Shan <gshan@redhat.com>
32
Reviewed-by: David Hildenbrand <david@redhat.com>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
34
Message-id: 20230731125946.2038742-1-gshan@redhat.com
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
---
37
accel/kvm/kvm-all.c | 2 +-
38
1 file changed, 1 insertion(+), 1 deletion(-)
39
40
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/accel/kvm/kvm-all.c
43
+++ b/accel/kvm/kvm-all.c
44
@@ -XXX,XX +XXX,XX @@ void kvm_flush_coalesced_mmio_buffer(void)
45
{
46
KVMState *s = kvm_state;
47
48
- if (s->coalesced_flush_in_progress) {
49
+ if (!s || s->coalesced_flush_in_progress) {
50
return;
51
}
52
53
--
54
2.34.1
55
56
diff view generated by jsdifflib
[PULL 6/6] gdbstub: Fix client Ctrl-C handling
Deleted patch
1
From: Nicholas Piggin <npiggin@gmail.com>
2
1
3
The gdb remote protocol has a special interrupt character (0x03) that is
4
transmitted outside the regular packet processing, and represents a
5
Ctrl-C pressed in the client. Despite not being a regular packet, it
6
does expect a regular stop response if the stub successfully stops the
7
running program.
8
9
See: https://sourceware.org/gdb/onlinedocs/gdb/Interrupts.html
10
11
Inhibiting the stop reply packet can lead to gdb client hang. So permit
12
a stop response when receiving a character from gdb that stops the vm.
13
Additionally, add a warning if that was not a 0x03 character, because
14
the gdb session is likely to end up getting confused if this happens.
15
16
Cc: qemu-stable@nongnu.org
17
Fixes: 758370052fb ("gdbstub: only send stop-reply packets when allowed to")
18
Reported-by: Frederic Barrat <fbarrat@linux.ibm.com>
19
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
20
Tested-by: Joel Stanley <joel@jms.id.au>
21
Message-id: 20230711085903.304496-1-npiggin@gmail.com
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
gdbstub/gdbstub.c | 13 +++++++++++--
26
1 file changed, 11 insertions(+), 2 deletions(-)
27
28
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/gdbstub/gdbstub.c
31
+++ b/gdbstub/gdbstub.c
32
@@ -XXX,XX +XXX,XX @@ void gdb_read_byte(uint8_t ch)
33
return;
34
}
35
if (runstate_is_running()) {
36
- /* when the CPU is running, we cannot do anything except stop
37
- it when receiving a char */
38
+ /*
39
+ * When the CPU is running, we cannot do anything except stop
40
+ * it when receiving a char. This is expected on a Ctrl-C in the
41
+ * gdb client. Because we are in all-stop mode, gdb sends a
42
+ * 0x03 byte which is not a usual packet, so we handle it specially
43
+ * here, but it does expect a stop reply.
44
+ */
45
+ if (ch != 0x03) {
46
+ warn_report("gdbstub: client sent packet while target running\n");
47
+ }
48
+ gdbserver_state.allow_stop_reply = true;
49
vm_stop(RUN_STATE_PAUSED);
50
} else
51
#endif
52
--
53
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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