target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s
helper function.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc
index 2c715af3e5..0fdd2698f6 100644
--- a/target/riscv/insn_trans/trans_rvzfa.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfa.c.inc
@@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fltq_s(dest, cpu_env, src1, src2);
+ gen_helper_fleq_d(dest, cpu_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fltq_s(dest, cpu_env, src1, src2);
+ gen_helper_fltq_d(dest, cpu_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
--
2.17.1
On Thu, Jul 27, 2023 at 8:50 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote: > > Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension. > However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s > helper function. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Thanks! Applied to riscv-to-apply.next after adding a `Fixes` tag Alistair > --- > target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc > index 2c715af3e5..0fdd2698f6 100644 > --- a/target/riscv/insn_trans/trans_rvzfa.c.inc > +++ b/target/riscv/insn_trans/trans_rvzfa.c.inc > @@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a) > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > - gen_helper_fltq_s(dest, cpu_env, src1, src2); > + gen_helper_fleq_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a) > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > - gen_helper_fltq_s(dest, cpu_env, src1, src2); > + gen_helper_fltq_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > -- > 2.17.1 > >
On 7/27/23 21:39, LIU Zhiwei wrote: > Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension. > However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s > helper function. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc > index 2c715af3e5..0fdd2698f6 100644 > --- a/target/riscv/insn_trans/trans_rvzfa.c.inc > +++ b/target/riscv/insn_trans/trans_rvzfa.c.inc > @@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a) > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > - gen_helper_fltq_s(dest, cpu_env, src1, src2); > + gen_helper_fleq_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a) > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > - gen_helper_fltq_s(dest, cpu_env, src1, src2); > + gen_helper_fltq_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > }
On 2023/7/28 08:39, LIU Zhiwei wrote: > Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension. > However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s > helper function. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > --- Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc > index 2c715af3e5..0fdd2698f6 100644 > --- a/target/riscv/insn_trans/trans_rvzfa.c.inc > +++ b/target/riscv/insn_trans/trans_rvzfa.c.inc > @@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a) > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > - gen_helper_fltq_s(dest, cpu_env, src1, src2); > + gen_helper_fleq_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a) > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > - gen_helper_fltq_s(dest, cpu_env, src1, src2); > + gen_helper_fltq_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > }
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