1 | A last small test of bug fixes before rc1. | 1 | target-arm queue: just bugfixes, mostly mine. |
---|---|---|---|
2 | 2 | ||
3 | thanks | 3 | thanks |
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637: | 6 | The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d: |
7 | 7 | ||
8 | Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100) | 8 | Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725 |
13 | 13 | ||
14 | for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4: | 14 | for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5: |
15 | 15 | ||
16 | hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100) | 16 | tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * hw/arm/sbsa-ref: set 'slots' property of xhci | 20 | * tests/decode: Suppress "error: " string for expected-failure tests |
21 | * linux-user: Remove pointless NULL check in clock_adjtime handling | 21 | * ui/curses: For curses display, recognize a few more control keys |
22 | * ptw: Fix S1_ptw_translate() debug path | 22 | * target/arm: Special case M-profile in debug_helper.c code |
23 | * ptw: Account for FEAT_RME when applying {N}SW, SA bits | 23 | * scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour |
24 | * accel/tcg: Zero-pad PC in TCG CPU exec trace lines | 24 | * hw/arm/smmu: Handle big-endian hosts correctly |
25 | * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write | ||
26 | 25 | ||
27 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
28 | Peter Maydell (5): | 27 | Peter Maydell (4): |
29 | linux-user: Remove pointless NULL check in clock_adjtime handling | 28 | hw/arm/smmu: Handle big-endian hosts correctly |
30 | target/arm/ptw.c: Add comments to S1Translate struct fields | 29 | scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour |
31 | target/arm: Fix S1_ptw_translate() debug path | 30 | target/arm: Special case M-profile in debug_helper.c code |
32 | target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits | 31 | tests/decode: Suppress "error: " string for expected-failure tests |
33 | accel/tcg: Zero-pad PC in TCG CPU exec trace lines | ||
34 | 32 | ||
35 | Tong Ho (1): | 33 | Sean Estabrooks (1): |
36 | hw/nvram: Avoid unnecessary Xilinx eFuse backstore write | 34 | For curses display, recognize a few more control keys |
37 | 35 | ||
38 | Yuquan Wang (1): | 36 | ui/curses_keys.h | 6 ++++++ |
39 | hw/arm/sbsa-ref: set 'slots' property of xhci | 37 | hw/arm/smmu-common.c | 3 +-- |
40 | 38 | hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++-------- | |
41 | accel/tcg/cpu-exec.c | 4 +-- | 39 | target/arm/debug_helper.c | 18 ++++++++++++------ |
42 | accel/tcg/translate-all.c | 2 +- | 40 | scripts/decodetree.py | 6 +++++- |
43 | hw/arm/sbsa-ref.c | 1 + | 41 | scripts/git-submodule.sh | 2 +- |
44 | hw/nvram/xlnx-efuse.c | 11 ++++-- | 42 | 6 files changed, 56 insertions(+), 18 deletions(-) |
45 | linux-user/syscall.c | 12 +++---- | ||
46 | target/arm/ptw.c | 90 +++++++++++++++++++++++++++++++++++++++++------ | ||
47 | 6 files changed, 98 insertions(+), 22 deletions(-) | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Yuquan Wang <wangyuquan1236@phytium.com.cn> | ||
2 | 1 | ||
3 | This extends the slots of xhci to 64, since the default xhci_sysbus | ||
4 | just supports one slot. | ||
5 | |||
6 | Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn> | ||
7 | Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
10 | Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
11 | Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/sbsa-ref.c | 1 + | ||
15 | 1 file changed, 1 insertion(+) | ||
16 | |||
17 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/sbsa-ref.c | ||
20 | +++ b/hw/arm/sbsa-ref.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void create_xhci(const SBSAMachineState *sms) | ||
22 | hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; | ||
23 | int irq = sbsa_ref_irqmap[SBSA_XHCI]; | ||
24 | DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); | ||
25 | + qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); | ||
26 | |||
27 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
28 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); | ||
29 | -- | ||
30 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Tong Ho <tong.ho@amd.com> | 1 | The implementation of the SMMUv3 has multiple places where it reads a |
---|---|---|---|
2 | data structure from the guest and directly operates on it without | ||
3 | doing a guest-to-host endianness conversion. Since all SMMU data | ||
4 | structures are little-endian, this means that the SMMU doesn't work | ||
5 | on a big-endian host. In particular, this causes the Avocado test | ||
6 | machine_aarch64_virt.py:Aarch64VirtMachine.test_alpine_virt_tcg_gic_max | ||
7 | to fail on an s390x host. | ||
2 | 8 | ||
3 | Add a check in the bit-set operation to write the backstore | 9 | Add appropriate byte-swapping on reads and writes of guest in-memory |
4 | only if the affected bit is 0 before. | 10 | data structures so that the device works correctly on big-endian |
11 | hosts. | ||
5 | 12 | ||
6 | With this in place, there will be no need for callers to | 13 | As part of this we constrain queue_read() to operate only on Cmd |
7 | do the checking in order to avoid unnecessary writes. | 14 | structs and queue_write() on Evt structs, because in practice these |
15 | are the only data structures the two functions are used with, and we | ||
16 | need to know what the data structure is to be able to byte-swap its | ||
17 | parts correctly. | ||
8 | 18 | ||
9 | Signed-off-by: Tong Ho <tong.ho@amd.com> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 20 | Tested-by: Thomas Huth <thuth@redhat.com> |
11 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 21 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
23 | Message-id: 20230717132641.764660-1-peter.maydell@linaro.org | ||
24 | Cc: qemu-stable@nongnu.org | ||
14 | --- | 25 | --- |
15 | hw/nvram/xlnx-efuse.c | 11 +++++++++-- | 26 | hw/arm/smmu-common.c | 3 +-- |
16 | 1 file changed, 9 insertions(+), 2 deletions(-) | 27 | hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++-------- |
28 | 2 files changed, 32 insertions(+), 10 deletions(-) | ||
17 | 29 | ||
18 | diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c | 30 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c |
19 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/nvram/xlnx-efuse.c | 32 | --- a/hw/arm/smmu-common.c |
21 | +++ b/hw/nvram/xlnx-efuse.c | 33 | +++ b/hw/arm/smmu-common.c |
22 | @@ -XXX,XX +XXX,XX @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k) | 34 | @@ -XXX,XX +XXX,XX @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte, |
23 | 35 | dma_addr_t addr = baseaddr + index * sizeof(*pte); | |
24 | bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) | 36 | |
37 | /* TODO: guarantee 64-bit single-copy atomicity */ | ||
38 | - ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte), | ||
39 | - MEMTXATTRS_UNSPECIFIED); | ||
40 | + ret = ldq_le_dma(&address_space_memory, addr, pte, MEMTXATTRS_UNSPECIFIED); | ||
41 | |||
42 | if (ret != MEMTX_OK) { | ||
43 | info->type = SMMU_PTW_ERR_WALK_EABT; | ||
44 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/smmuv3.c | ||
47 | +++ b/hw/arm/smmuv3.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn) | ||
49 | trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn); | ||
50 | } | ||
51 | |||
52 | -static inline MemTxResult queue_read(SMMUQueue *q, void *data) | ||
53 | +static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd) | ||
25 | { | 54 | { |
26 | + uint32_t set, *row; | 55 | dma_addr_t addr = Q_CONS_ENTRY(q); |
27 | + | 56 | + MemTxResult ret; |
28 | if (efuse_ro_bits_find(s, bit)) { | 57 | + int i; |
29 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); | 58 | |
30 | 59 | - return dma_memory_read(&address_space_memory, addr, data, q->entry_size, | |
31 | @@ -XXX,XX +XXX,XX @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) | 60 | - MEMTXATTRS_UNSPECIFIED); |
32 | return false; | 61 | + ret = dma_memory_read(&address_space_memory, addr, cmd, sizeof(Cmd), |
62 | + MEMTXATTRS_UNSPECIFIED); | ||
63 | + if (ret != MEMTX_OK) { | ||
64 | + return ret; | ||
65 | + } | ||
66 | + for (i = 0; i < ARRAY_SIZE(cmd->word); i++) { | ||
67 | + le32_to_cpus(&cmd->word[i]); | ||
68 | + } | ||
69 | + return ret; | ||
70 | } | ||
71 | |||
72 | -static MemTxResult queue_write(SMMUQueue *q, void *data) | ||
73 | +static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in) | ||
74 | { | ||
75 | dma_addr_t addr = Q_PROD_ENTRY(q); | ||
76 | MemTxResult ret; | ||
77 | + Evt evt = *evt_in; | ||
78 | + int i; | ||
79 | |||
80 | - ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size, | ||
81 | + for (i = 0; i < ARRAY_SIZE(evt.word); i++) { | ||
82 | + cpu_to_le32s(&evt.word[i]); | ||
83 | + } | ||
84 | + ret = dma_memory_write(&address_space_memory, addr, &evt, sizeof(Evt), | ||
85 | MEMTXATTRS_UNSPECIFIED); | ||
86 | if (ret != MEMTX_OK) { | ||
87 | return ret; | ||
88 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) | ||
89 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | ||
90 | SMMUEventInfo *event) | ||
91 | { | ||
92 | - int ret; | ||
93 | + int ret, i; | ||
94 | |||
95 | trace_smmuv3_get_ste(addr); | ||
96 | /* TODO: guarantee 64-bit single-copy atomicity */ | ||
97 | @@ -XXX,XX +XXX,XX @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | ||
98 | event->u.f_ste_fetch.addr = addr; | ||
99 | return -EINVAL; | ||
33 | } | 100 | } |
34 | 101 | + for (i = 0; i < ARRAY_SIZE(buf->word); i++) { | |
35 | - s->fuse32[bit / 32] |= 1 << (bit % 32); | 102 | + le32_to_cpus(&buf->word[i]); |
36 | - efuse_bdrv_sync(s, bit); | ||
37 | + /* Avoid back-end write unless there is a real update */ | ||
38 | + row = &s->fuse32[bit / 32]; | ||
39 | + set = 1 << (bit % 32); | ||
40 | + if (!(set & *row)) { | ||
41 | + *row |= set; | ||
42 | + efuse_bdrv_sync(s, bit); | ||
43 | + } | 103 | + } |
44 | return true; | 104 | return 0; |
105 | |||
45 | } | 106 | } |
107 | @@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, | ||
108 | CD *buf, SMMUEventInfo *event) | ||
109 | { | ||
110 | dma_addr_t addr = STE_CTXPTR(ste); | ||
111 | - int ret; | ||
112 | + int ret, i; | ||
113 | |||
114 | trace_smmuv3_get_cd(addr); | ||
115 | /* TODO: guarantee 64-bit single-copy atomicity */ | ||
116 | @@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, | ||
117 | event->u.f_ste_fetch.addr = addr; | ||
118 | return -EINVAL; | ||
119 | } | ||
120 | + for (i = 0; i < ARRAY_SIZE(buf->word); i++) { | ||
121 | + le32_to_cpus(&buf->word[i]); | ||
122 | + } | ||
123 | return 0; | ||
124 | } | ||
125 | |||
126 | @@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, | ||
127 | return -EINVAL; | ||
128 | } | ||
129 | if (s->features & SMMU_FEATURE_2LVL_STE) { | ||
130 | - int l1_ste_offset, l2_ste_offset, max_l2_ste, span; | ||
131 | + int l1_ste_offset, l2_ste_offset, max_l2_ste, span, i; | ||
132 | dma_addr_t l1ptr, l2ptr; | ||
133 | STEDesc l1std; | ||
134 | |||
135 | @@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, | ||
136 | event->u.f_ste_fetch.addr = l1ptr; | ||
137 | return -EINVAL; | ||
138 | } | ||
139 | + for (i = 0; i < ARRAY_SIZE(l1std.word); i++) { | ||
140 | + le32_to_cpus(&l1std.word[i]); | ||
141 | + } | ||
142 | |||
143 | span = L1STD_SPAN(&l1std); | ||
46 | 144 | ||
47 | -- | 145 | -- |
48 | 2.34.1 | 146 | 2.34.1 |
49 | 147 | ||
50 | 148 | diff view generated by jsdifflib |
1 | In commit f0a08b0913befbd we changed the type of the PC from | 1 | The POSIX definition of the 'read' utility requires that you |
---|---|---|---|
2 | target_ulong to vaddr. In doing so we inadvertently dropped the | 2 | specify the variable name to set; omitting the name and |
3 | zero-padding on the PC in trace lines (the second item inside the [] | 3 | having it default to 'REPLY' is a bashism. If your system |
4 | in these lines). They used to look like this on AArch64, for | 4 | sh is dash, then it will print an error message during build: |
5 | instance: | ||
6 | 5 | ||
7 | Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000] | 6 | qemu/pc-bios/s390-ccw/../../scripts/git-submodule.sh: 106: read: arg count |
8 | 7 | ||
9 | and now they look like this: | 8 | Specify the variable name explicitly. |
10 | Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000] | ||
11 | 9 | ||
12 | and if the PC happens to be somewhere low like 0x5000 | 10 | Fixes: fdb8fd8cb915647b ("git-submodule: allow partial update of .git-submodule-status") |
13 | then the field is shown as /5000/. | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20230720153038.1587196-1-peter.maydell@linaro.org | ||
15 | --- | ||
16 | scripts/git-submodule.sh | 2 +- | ||
17 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
14 | 18 | ||
15 | This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier, | 19 | diff --git a/scripts/git-submodule.sh b/scripts/git-submodule.sh |
16 | depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64 | 20 | index XXXXXXX..XXXXXXX 100755 |
17 | with no width specifier. | 21 | --- a/scripts/git-submodule.sh |
18 | 22 | +++ b/scripts/git-submodule.sh | |
19 | Restore the zero-padding by adding an 016 width specifier to | 23 | @@ -XXX,XX +XXX,XX @@ update) |
20 | this tracing and a couple of others that were similarly recently | 24 | check_updated $module || echo Updated "$module" |
21 | changed to use VADDR_PRIx without a width specifier. | 25 | done |
22 | 26 | ||
23 | We can't unfortunately restore the "32-bit guests are padded to | 27 | - (while read -r; do |
24 | 8 hex digits and 64-bit guests to 16 hex digits" behaviour so | 28 | + (while read -r REPLY; do |
25 | easily. | 29 | for module in $modules; do |
26 | 30 | case $REPLY in | |
27 | Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr") | 31 | *" $module "*) continue 2 ;; |
28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
29 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
30 | Reviewed-by: Anton Johansson <anjo@rev.ng> | ||
31 | Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org | ||
32 | --- | ||
33 | accel/tcg/cpu-exec.c | 4 ++-- | ||
34 | accel/tcg/translate-all.c | 2 +- | ||
35 | 2 files changed, 3 insertions(+), 3 deletions(-) | ||
36 | |||
37 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/accel/tcg/cpu-exec.c | ||
40 | +++ b/accel/tcg/cpu-exec.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, | ||
42 | if (qemu_log_in_addr_range(pc)) { | ||
43 | qemu_log_mask(CPU_LOG_EXEC, | ||
44 | "Trace %d: %p [%08" PRIx64 | ||
45 | - "/%" VADDR_PRIx "/%08x/%08x] %s\n", | ||
46 | + "/%016" VADDR_PRIx "/%08x/%08x] %s\n", | ||
47 | cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, | ||
48 | tb->flags, tb->cflags, lookup_symbol(pc)); | ||
49 | |||
50 | @@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) | ||
51 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { | ||
52 | vaddr pc = log_pc(cpu, last_tb); | ||
53 | if (qemu_log_in_addr_range(pc)) { | ||
54 | - qemu_log("Stopped execution of TB chain before %p [%" | ||
55 | + qemu_log("Stopped execution of TB chain before %p [%016" | ||
56 | VADDR_PRIx "] %s\n", | ||
57 | last_tb->tc.ptr, pc, lookup_symbol(pc)); | ||
58 | } | ||
59 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/accel/tcg/translate-all.c | ||
62 | +++ b/accel/tcg/translate-all.c | ||
63 | @@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) | ||
64 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { | ||
65 | vaddr pc = log_pc(cpu, tb); | ||
66 | if (qemu_log_in_addr_range(pc)) { | ||
67 | - qemu_log("cpu_io_recompile: rewound execution of TB to %" | ||
68 | + qemu_log("cpu_io_recompile: rewound execution of TB to %016" | ||
69 | VADDR_PRIx "\n", pc); | ||
70 | } | ||
71 | } | ||
72 | -- | 32 | -- |
73 | 2.34.1 | 33 | 2.34.1 |
74 | 34 | ||
75 | 35 | diff view generated by jsdifflib |
1 | In get_phys_addr_twostage() the code that applies the effects of | 1 | A lot of the code called from helper_exception_bkpt_insn() is written |
---|---|---|---|
2 | VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure. | 2 | assuming A-profile, but we will also call this helper on M-profile |
3 | Now we also have f.attrs.space for FEAT_RME, we need to keep the two | 3 | CPUs when they execute a BKPT insn. This used to work by accident, |
4 | in sync. | 4 | but recent changes mean that we will hit an assert when some of this |
5 | code calls down into lower level functions that end up calling | ||
6 | arm_security_space_below_el3(), arm_el_is_aa64(), and other functions | ||
7 | that now explicitly assert that the guest CPU is not M-profile. | ||
5 | 8 | ||
6 | These bits only have an effect for Secure space translations, not | 9 | Handle M-profile directly to avoid the assertions: |
7 | for Root, so use the input in_space field to determine whether to | 10 | * in arm_debug_target_el(), M-profile debug exceptions always |
8 | apply them rather than the input is_secure. This doesn't actually | 11 | go to EL1 |
9 | make a difference because Root translations are never two-stage, | 12 | * in arm_debug_exception_fsr(), M-profile always uses the short |
10 | but it's a little clearer. | 13 | format FSR (compare commit d7fe699be54b2, though in this case |
14 | the code in arm_v7m_cpu_do_interrupt() does not need to | ||
15 | look at the FSR value at all) | ||
11 | 16 | ||
17 | Cc: qemu-stable@nongnu.org | ||
18 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1775 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org | 21 | Message-id: 20230721143239.1753066-1-peter.maydell@linaro.org |
15 | --- | 22 | --- |
16 | target/arm/ptw.c | 13 ++++++++----- | 23 | target/arm/debug_helper.c | 18 ++++++++++++------ |
17 | 1 file changed, 8 insertions(+), 5 deletions(-) | 24 | 1 file changed, 12 insertions(+), 6 deletions(-) |
18 | 25 | ||
19 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | 26 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
20 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/ptw.c | 28 | --- a/target/arm/debug_helper.c |
22 | +++ b/target/arm/ptw.c | 29 | +++ b/target/arm/debug_helper.c |
23 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | 30 | @@ -XXX,XX +XXX,XX @@ static int arm_debug_target_el(CPUARMState *env) |
24 | hwaddr ipa; | 31 | bool secure = arm_is_secure(env); |
25 | int s1_prot, s1_lgpgsz; | 32 | bool route_to_el2 = false; |
26 | bool is_secure = ptw->in_secure; | 33 | |
27 | + ARMSecuritySpace in_space = ptw->in_space; | 34 | + if (arm_feature(env, ARM_FEATURE_M)) { |
28 | bool ret, ipa_secure; | 35 | + return 1; |
29 | ARMCacheAttrs cacheattrs1; | ||
30 | ARMSecuritySpace ipa_space; | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
32 | * Check if IPA translates to secure or non-secure PA space. | ||
33 | * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. | ||
34 | */ | ||
35 | - result->f.attrs.secure = | ||
36 | - (is_secure | ||
37 | - && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) | ||
38 | - && (ipa_secure | ||
39 | - || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)))); | ||
40 | + if (in_space == ARMSS_Secure) { | ||
41 | + result->f.attrs.secure = | ||
42 | + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) | ||
43 | + && (ipa_secure | ||
44 | + || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))); | ||
45 | + result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure); | ||
46 | + } | 36 | + } |
47 | 37 | + | |
48 | return false; | 38 | if (arm_is_el2_enabled(env)) { |
49 | } | 39 | route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || |
40 | env->cp15.mdcr_el2 & MDCR_TDE; | ||
41 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env) | ||
42 | { | ||
43 | ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; | ||
44 | int target_el = arm_debug_target_el(env); | ||
45 | - bool using_lpae = false; | ||
46 | + bool using_lpae; | ||
47 | |||
48 | - if (target_el == 2 || arm_el_is_aa64(env, target_el)) { | ||
49 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
50 | + using_lpae = false; | ||
51 | + } else if (target_el == 2 || arm_el_is_aa64(env, target_el)) { | ||
52 | using_lpae = true; | ||
53 | } else if (arm_feature(env, ARM_FEATURE_PMSA) && | ||
54 | arm_feature(env, ARM_FEATURE_V8)) { | ||
55 | using_lpae = true; | ||
56 | + } else if (arm_feature(env, ARM_FEATURE_LPAE) && | ||
57 | + (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { | ||
58 | + using_lpae = true; | ||
59 | } else { | ||
60 | - if (arm_feature(env, ARM_FEATURE_LPAE) && | ||
61 | - (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { | ||
62 | - using_lpae = true; | ||
63 | - } | ||
64 | + using_lpae = false; | ||
65 | } | ||
66 | |||
67 | if (using_lpae) { | ||
50 | -- | 68 | -- |
51 | 2.34.1 | 69 | 2.34.1 | diff view generated by jsdifflib |
1 | In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate() | 1 | From: Sean Estabrooks <sean.estabrooks@gmail.com> |
---|---|---|---|
2 | so that the debug-access "call get_phys_addr_*" codepath is used both | ||
3 | when S1 is doing ptw reads from stage 2 and when it is doing ptw | ||
4 | reads from physical memory. However, we didn't update the | ||
5 | calculation of s2ptw->in_space and s2ptw->in_secure to account for | ||
6 | the "ptw reads from physical memory" case. This meant that debug | ||
7 | accesses when in Secure state broke. | ||
8 | 2 | ||
9 | Create a new function S2_security_space() which returns the | 3 | The curses display handles most control-X keys, and translates |
10 | correct security space to use for the ptw load, and use it to | 4 | them into their corresponding keycode. Here we recognize |
11 | determine the correct .in_secure and .in_space fields for the | 5 | a few that are missing, Ctrl-@ (null), Ctrl-\ (backslash), |
12 | stage 2 lookup for the ptw load. | 6 | Ctrl-] (right bracket), Ctrl-^ (caret), Ctrl-_ (underscore). |
13 | 7 | ||
14 | Reported-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | 8 | Signed-off-by: Sean Estabrooks <sean.estabrooks@gmail.com> |
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Message-id: CAHyVn3Bh9CRgDuOmf7G7Ngwamu8d4cVozAcB2i4ymnnggBXNmg@mail.gmail.com |
16 | Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org | ||
19 | Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate") | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 12 | --- |
22 | target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++----- | 13 | ui/curses_keys.h | 6 ++++++ |
23 | 1 file changed, 32 insertions(+), 5 deletions(-) | 14 | 1 file changed, 6 insertions(+) |
24 | 15 | ||
25 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | 16 | diff --git a/ui/curses_keys.h b/ui/curses_keys.h |
26 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/ptw.c | 18 | --- a/ui/curses_keys.h |
28 | +++ b/target/arm/ptw.c | 19 | +++ b/ui/curses_keys.h |
29 | @@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) | 20 | @@ -XXX,XX +XXX,XX @@ static const int _curses2keycode[CURSES_CHARS] = { |
30 | } | 21 | ['N' - '@'] = 49 | CNTRL, /* Control + n */ |
31 | } | 22 | /* Control + m collides with the keycode for Enter */ |
32 | 23 | ||
33 | +static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space, | 24 | + ['@' - '@'] = 3 | CNTRL, /* Control + @ */ |
34 | + ARMMMUIdx s2_mmu_idx) | 25 | + /* Control + [ collides with the keycode for Escape */ |
35 | +{ | 26 | + ['\\' - '@'] = 43 | CNTRL, /* Control + Backslash */ |
36 | + /* | 27 | + [']' - '@'] = 27 | CNTRL, /* Control + ] */ |
37 | + * Return the security space to use for stage 2 when doing | 28 | + ['^' - '@'] = 7 | CNTRL, /* Control + ^ */ |
38 | + * the S1 page table descriptor load. | 29 | + ['_' - '@'] = 12 | CNTRL, /* Control + Underscore */ |
39 | + */ | 30 | }; |
40 | + if (regime_is_stage2(s2_mmu_idx)) { | 31 | |
41 | + /* | 32 | static const int _curseskey2keycode[CURSES_KEYS] = { |
42 | + * The security space for ptw reads is almost always the same | ||
43 | + * as that of the security space of the stage 1 translation. | ||
44 | + * The only exception is when stage 1 is Secure; in that case | ||
45 | + * the ptw read might be to the Secure or the NonSecure space | ||
46 | + * (but never Realm or Root), and the s2_mmu_idx tells us which. | ||
47 | + * Root translations are always single-stage. | ||
48 | + */ | ||
49 | + if (s1_space == ARMSS_Secure) { | ||
50 | + return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S); | ||
51 | + } else { | ||
52 | + assert(s2_mmu_idx != ARMMMUIdx_Stage2_S); | ||
53 | + assert(s1_space != ARMSS_Root); | ||
54 | + return s1_space; | ||
55 | + } | ||
56 | + } else { | ||
57 | + /* ptw loads are from phys: the mmu idx itself says which space */ | ||
58 | + return arm_phys_to_space(s2_mmu_idx); | ||
59 | + } | ||
60 | +} | ||
61 | + | ||
62 | /* Translate a S1 pagetable walk through S2 if needed. */ | ||
63 | static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
64 | hwaddr addr, ARMMMUFaultInfo *fi) | ||
65 | { | ||
66 | - ARMSecuritySpace space = ptw->in_space; | ||
67 | bool is_secure = ptw->in_secure; | ||
68 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; | ||
69 | ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; | ||
70 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
71 | * From gdbstub, do not use softmmu so that we don't modify the | ||
72 | * state of the cpu at all, including softmmu tlb contents. | ||
73 | */ | ||
74 | + ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx); | ||
75 | S1Translate s2ptw = { | ||
76 | .in_mmu_idx = s2_mmu_idx, | ||
77 | .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), | ||
78 | - .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, | ||
79 | - .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure | ||
80 | - : space == ARMSS_Realm ? ARMSS_Realm | ||
81 | - : ARMSS_NonSecure), | ||
82 | + .in_secure = arm_space_is_secure(s2_space), | ||
83 | + .in_space = s2_space, | ||
84 | .in_debug = true, | ||
85 | }; | ||
86 | GetPhysAddrResult s2 = { }; | ||
87 | -- | 33 | -- |
88 | 2.34.1 | 34 | 2.34.1 | diff view generated by jsdifflib |
1 | In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to | 1 | The "expected failure" tests for decodetree result in the |
---|---|---|---|
2 | the address of the local variable htx. This means it can never be | 2 | error messages from decodetree ending up in logs and in |
3 | NULL, but later in the code we check it for NULL anyway. Coverity | 3 | V=1 output: |
4 | complains about this (CID 1507683) because the NULL check comes after | ||
5 | a call to clock_adjtime() that assumes it is non-NULL. | ||
6 | 4 | ||
7 | Since phtx is always &htx, and is used only in three places, it's not | 5 | >>> MALLOC_PERTURB_=226 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/pyvenv/bin/python3 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/scripts/decodetree.py --output-null --test-for-error /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode |
8 | really necessary. Remove it, bringing the code structure in to line | 6 | ――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― ✀ ―――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― |
9 | with that for TARGET_NR_clock_adjtime64, which already uses a simple | 7 | /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode:5: error: duplicate argument "a" |
10 | '&htx' when it wants a pointer to 'htx'. | 8 | ――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― |
9 | 1/44 qemu:decodetree / err_argset1 OK 0.05s | ||
10 | |||
11 | This then produces false positives when scanning the | ||
12 | logfiles for strings like "error: ". | ||
13 | |||
14 | For the expected-failure tests, make decodetree print | ||
15 | "detected:" instead of "error:". | ||
11 | 16 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org | 20 | Message-id: 20230720131521.1325905-1-peter.maydell@linaro.org |
16 | --- | 21 | --- |
17 | linux-user/syscall.c | 12 +++++------- | 22 | scripts/decodetree.py | 6 +++++- |
18 | 1 file changed, 5 insertions(+), 7 deletions(-) | 23 | 1 file changed, 5 insertions(+), 1 deletion(-) |
19 | 24 | ||
20 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | 25 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py |
21 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/linux-user/syscall.c | 27 | --- a/scripts/decodetree.py |
23 | +++ b/linux-user/syscall.c | 28 | +++ b/scripts/decodetree.py |
24 | @@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1, | 29 | @@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args): |
25 | #if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME) | 30 | global output_file |
26 | case TARGET_NR_clock_adjtime: | 31 | global output_fd |
27 | { | 32 | |
28 | - struct timex htx, *phtx = &htx; | 33 | + # For the test suite expected-errors case, don't print the |
29 | + struct timex htx; | 34 | + # string "error: ", so they don't turn up as false positives |
30 | 35 | + # if you grep the meson logs for strings like that. | |
31 | - if (target_to_host_timex(phtx, arg2) != 0) { | 36 | + end = 'error: ' if not testforerror else 'detected: ' |
32 | + if (target_to_host_timex(&htx, arg2) != 0) { | 37 | prefix = '' |
33 | return -TARGET_EFAULT; | 38 | if file: |
34 | } | 39 | prefix += f'{file}:' |
35 | - ret = get_errno(clock_adjtime(arg1, phtx)); | 40 | @@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args): |
36 | - if (!is_error(ret) && phtx) { | 41 | prefix += f'{lineno}:' |
37 | - if (host_to_target_timex(arg2, phtx) != 0) { | 42 | if prefix: |
38 | - return -TARGET_EFAULT; | 43 | prefix += ' ' |
39 | - } | 44 | - print(prefix, end='error: ', file=sys.stderr) |
40 | + ret = get_errno(clock_adjtime(arg1, &htx)); | 45 | + print(prefix, end=end, file=sys.stderr) |
41 | + if (!is_error(ret) && host_to_target_timex(arg2, &htx)) { | 46 | print(*args, file=sys.stderr) |
42 | + return -TARGET_EFAULT; | 47 | |
43 | } | 48 | if output_file and output_fd: |
44 | } | ||
45 | return ret; | ||
46 | -- | 49 | -- |
47 | 2.34.1 | 50 | 2.34.1 |
48 | 51 | ||
49 | 52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add comments to the in_* fields in the S1Translate struct | ||
2 | that explain what they're doing. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++ | ||
9 | 1 file changed, 40 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/ptw.c | ||
14 | +++ b/target/arm/ptw.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #endif | ||
17 | |||
18 | typedef struct S1Translate { | ||
19 | + /* | ||
20 | + * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk. | ||
21 | + * Together with in_space, specifies the architectural translation regime. | ||
22 | + */ | ||
23 | ARMMMUIdx in_mmu_idx; | ||
24 | + /* | ||
25 | + * in_ptw_idx: specifies which mmuidx to use for the actual | ||
26 | + * page table descriptor load operations. This will be one of the | ||
27 | + * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes. | ||
28 | + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, | ||
29 | + * this field is updated accordingly. | ||
30 | + */ | ||
31 | ARMMMUIdx in_ptw_idx; | ||
32 | + /* | ||
33 | + * in_space: the security space for this walk. This plus | ||
34 | + * the in_mmu_idx specify the architectural translation regime. | ||
35 | + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, | ||
36 | + * this field is updated accordingly. | ||
37 | + * | ||
38 | + * Note that the security space for the in_ptw_idx may be different | ||
39 | + * from that for the in_mmu_idx. We do not need to explicitly track | ||
40 | + * the in_ptw_idx security space because: | ||
41 | + * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx | ||
42 | + * itself specifies the security space | ||
43 | + * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security | ||
44 | + * space used for ptw reads is the same as that of the security | ||
45 | + * space of the stage 1 translation for all cases except where | ||
46 | + * stage 1 is Secure; in that case the only possibilities for | ||
47 | + * the ptw read are Secure and NonSecure, and the in_ptw_idx | ||
48 | + * value being Stage2 vs Stage2_S distinguishes those. | ||
49 | + */ | ||
50 | ARMSecuritySpace in_space; | ||
51 | + /* | ||
52 | + * in_secure: whether the translation regime is a Secure one. | ||
53 | + * This is always equal to arm_space_is_secure(in_space). | ||
54 | + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, | ||
55 | + * this field is updated accordingly. | ||
56 | + */ | ||
57 | bool in_secure; | ||
58 | + /* | ||
59 | + * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug | ||
60 | + * accesses will not update the guest page table access flags | ||
61 | + * and will not change the state of the softmmu TLBs. | ||
62 | + */ | ||
63 | bool in_debug; | ||
64 | /* | ||
65 | * If this is stage 2 of a stage 1+2 page table walk, then this must | ||
66 | -- | ||
67 | 2.34.1 | diff view generated by jsdifflib |