[PULL 0/7] target-arm queue
[PULL v2 00/67] target-arm queue
1
A last small test of bug fixes before rc1.
1
v1->v2 changes: dropped the patch adding the new ast2600
2
board, as it doesn't pass "make check" on 32-bit hosts or
3
low-memory hosts.
2
4
3
thanks
5
thanks
4
-- PMM
6
-- PMM
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7
6
The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:
8
The following changes since commit 3af78db68176a049e2570822f64604e0692c1447:
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9
8
Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100)
10
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-10-15 13:25:05 +0100)
9
11
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are available in the Git repository at:
12
are available in the Git repository at:
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13
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191015
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15
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for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:
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for you to fetch changes up to 19845504da1bdee4be7d0fba33da5be9efa4c11b:
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hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100)
18
hw/misc/bcm2835_mbox: Add trace events (2019-10-15 18:09:05 +0100)
17
19
18
----------------------------------------------------------------
20
----------------------------------------------------------------
19
target-arm queue:
21
target-arm queue:
20
* hw/arm/sbsa-ref: set 'slots' property of xhci
22
* Add Aspeed AST2600 SoC support (but no new board model yet)
21
* linux-user: Remove pointless NULL check in clock_adjtime handling
23
* aspeed/wdt: Check correct register for clock source
22
* ptw: Fix S1_ptw_translate() debug path
24
* bcm2835: code cleanups, better logging, trace events
23
* ptw: Account for FEAT_RME when applying {N}SW, SA bits
25
* implement v2.0 of the Arm semihosting specification
24
* accel/tcg: Zero-pad PC in TCG CPU exec trace lines
26
* provide new 'transaction-based' ptimer API and use it
25
* hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
27
for the Arm devices that use ptimers
28
* ARM: KVM: support more than 256 CPUs
26
29
27
----------------------------------------------------------------
30
----------------------------------------------------------------
28
Peter Maydell (5):
31
Amithash Prasad (1):
29
linux-user: Remove pointless NULL check in clock_adjtime handling
32
aspeed/wdt: Check correct register for clock source
30
target/arm/ptw.c: Add comments to S1Translate struct fields
33
31
target/arm: Fix S1_ptw_translate() debug path
34
Cédric Le Goater (14):
32
target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
35
aspeed/timer: Introduce an object class per SoC
33
accel/tcg: Zero-pad PC in TCG CPU exec trace lines
36
aspeed/timer: Add support for control register 3
34
37
aspeed/timer: Add AST2600 support
35
Tong Ho (1):
38
aspeed/timer: Add support for IRQ status register on the AST2600
36
hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
39
aspeed/sdmc: Introduce an object class per SoC
37
40
watchdog/aspeed: Introduce an object class per SoC
38
Yuquan Wang (1):
41
aspeed/smc: Introduce segment operations
39
hw/arm/sbsa-ref: set 'slots' property of xhci
42
aspeed/smc: Add AST2600 support
40
43
aspeed/i2c: Introduce an object class per SoC
41
accel/tcg/cpu-exec.c | 4 +--
44
aspeed/i2c: Add AST2600 support
42
accel/tcg/translate-all.c | 2 +-
45
aspeed: Introduce an object class per SoC
43
hw/arm/sbsa-ref.c | 1 +
46
aspeed/soc: Add AST2600 support
44
hw/nvram/xlnx-efuse.c | 11 ++++--
47
m25p80: Add support for w25q512jv
45
linux-user/syscall.c | 12 +++----
48
aspeed: add support for the Aspeed MII controller of the AST2600
46
target/arm/ptw.c | 90 +++++++++++++++++++++++++++++++++++++++++------
49
47
6 files changed, 98 insertions(+), 22 deletions(-)
50
Eddie James (1):
51
hw/sd/aspeed_sdhci: New device
52
53
Eric Auger (3):
54
linux headers: update against v5.4-rc1
55
intc/arm_gic: Support IRQ injection for more than 256 vpus
56
ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256
57
58
Joel Stanley (5):
59
hw: aspeed_scu: Add AST2600 support
60
aspeed/sdmc: Add AST2600 support
61
hw: wdt_aspeed: Add AST2600 support
62
aspeed: Parameterise number of MACs
63
aspeed/soc: Add ASPEED Video stub
64
65
Peter Maydell (36):
66
ptimer: Rename ptimer_init() to ptimer_init_with_bh()
67
ptimer: Provide new transaction-based API
68
tests/ptimer-test: Switch to transaction-based ptimer API
69
hw/timer/arm_timer.c: Switch to transaction-based ptimer API
70
hw/arm/musicpal.c: Switch to transaction-based ptimer API
71
hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API
72
hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API
73
hw/timer/cmsdk-apb-dualtimer.c: Switch to transaction-based ptimer API
74
hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API
75
hw/timer/digic-timer.c: Switch to transaction-based ptimer API
76
hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API
77
hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API
78
hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API
79
hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API
80
hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API
81
hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API
82
hw/timer/imx_epit.c: Switch to transaction-based ptimer API
83
hw/timer/imx_gpt.c: Switch to transaction-based ptimer API
84
hw/timer/mss-timerc: Switch to transaction-based ptimer API
85
hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API
86
hw/net/lan9118.c: Switch to transaction-based ptimer API
87
target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno()
88
target/arm/arm-semi: Always set some kind of errno for failed calls
89
target/arm/arm-semi: Correct comment about gdb syscall races
90
target/arm/arm-semi: Make semihosting code hand out its own file descriptors
91
target/arm/arm-semi: Restrict use of TaskState*
92
target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions
93
target/arm/arm-semi: Factor out implementation of SYS_CLOSE
94
target/arm/arm-semi: Factor out implementation of SYS_WRITE
95
target/arm/arm-semi: Factor out implementation of SYS_READ
96
target/arm/arm-semi: Factor out implementation of SYS_ISTTY
97
target/arm/arm-semi: Factor out implementation of SYS_SEEK
98
target/arm/arm-semi: Factor out implementation of SYS_FLEN
99
target/arm/arm-semi: Implement support for semihosting feature detection
100
target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension
101
target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension
102
103
Philippe Mathieu-Daudé (6):
104
hw/arm/raspi: Use the IEC binary prefix definitions
105
hw/arm/bcm2835_peripherals: Improve logging
106
hw/arm/bcm2835_peripherals: Name various address spaces
107
hw/arm/bcm2835: Rename some definitions
108
hw/arm/bcm2835: Add various unimplemented peripherals
109
hw/misc/bcm2835_mbox: Add trace events
110
111
Rashmica Gupta (1):
112
hw/gpio: Add in AST2600 specific implementation
113
114
hw/arm/Makefile.objs | 2 +-
115
hw/sd/Makefile.objs | 1 +
116
include/hw/arm/aspeed_soc.h | 29 +-
117
include/hw/arm/bcm2835_peripherals.h | 15 +
118
include/hw/arm/raspi_platform.h | 24 +-
119
include/hw/i2c/aspeed_i2c.h | 20 +-
120
include/hw/misc/aspeed_scu.h | 7 +-
121
include/hw/misc/aspeed_sdmc.h | 20 +-
122
include/hw/net/ftgmac100.h | 17 +
123
include/hw/ptimer.h | 83 ++-
124
include/hw/sd/aspeed_sdhci.h | 34 ++
125
include/hw/ssi/aspeed_smc.h | 4 +
126
include/hw/timer/aspeed_timer.h | 18 +
127
include/hw/timer/mss-timer.h | 1 -
128
include/hw/watchdog/wdt_aspeed.h | 19 +-
129
include/standard-headers/asm-x86/bootparam.h | 2 +
130
include/standard-headers/asm-x86/kvm_para.h | 1 +
131
include/standard-headers/linux/ethtool.h | 24 +
132
include/standard-headers/linux/pci_regs.h | 19 +-
133
include/standard-headers/linux/virtio_fs.h | 19 +
134
include/standard-headers/linux/virtio_ids.h | 2 +
135
include/standard-headers/linux/virtio_iommu.h | 165 ++++++
136
include/standard-headers/linux/virtio_pmem.h | 6 +-
137
linux-headers/asm-arm/kvm.h | 16 +-
138
linux-headers/asm-arm/unistd-common.h | 2 +
139
linux-headers/asm-arm64/kvm.h | 21 +-
140
linux-headers/asm-generic/mman-common.h | 18 +-
141
linux-headers/asm-generic/mman.h | 10 +-
142
linux-headers/asm-generic/unistd.h | 10 +-
143
linux-headers/asm-mips/mman.h | 3 +
144
linux-headers/asm-mips/unistd_n32.h | 1 +
145
linux-headers/asm-mips/unistd_n64.h | 1 +
146
linux-headers/asm-mips/unistd_o32.h | 1 +
147
linux-headers/asm-powerpc/mman.h | 6 +-
148
linux-headers/asm-powerpc/unistd_32.h | 2 +
149
linux-headers/asm-powerpc/unistd_64.h | 2 +
150
linux-headers/asm-s390/kvm.h | 6 +
151
linux-headers/asm-s390/unistd_32.h | 2 +
152
linux-headers/asm-s390/unistd_64.h | 2 +
153
linux-headers/asm-x86/kvm.h | 28 +-
154
linux-headers/asm-x86/unistd.h | 2 +-
155
linux-headers/asm-x86/unistd_32.h | 2 +
156
linux-headers/asm-x86/unistd_64.h | 2 +
157
linux-headers/asm-x86/unistd_x32.h | 2 +
158
linux-headers/linux/kvm.h | 12 +-
159
linux-headers/linux/psp-sev.h | 5 +-
160
linux-headers/linux/vfio.h | 71 ++-
161
target/arm/kvm_arm.h | 1 +
162
hw/arm/aspeed.c | 19 +-
163
hw/arm/aspeed_ast2600.c | 523 +++++++++++++++++++
164
hw/arm/aspeed_soc.c | 199 +++++---
165
hw/arm/bcm2835_peripherals.c | 38 +-
166
hw/arm/bcm2836.c | 2 +-
167
hw/arm/musicpal.c | 16 +-
168
hw/arm/raspi.c | 4 +-
169
hw/block/m25p80.c | 1 +
170
hw/char/bcm2835_aux.c | 5 +-
171
hw/core/ptimer.c | 154 +++++-
172
hw/display/bcm2835_fb.c | 2 +-
173
hw/dma/bcm2835_dma.c | 10 +-
174
hw/dma/xilinx_axidma.c | 2 +-
175
hw/gpio/aspeed_gpio.c | 142 +++++-
176
hw/i2c/aspeed_i2c.c | 106 +++-
177
hw/intc/arm_gic_kvm.c | 7 +-
178
hw/intc/bcm2836_control.c | 7 +-
179
hw/m68k/mcf5206.c | 2 +-
180
hw/m68k/mcf5208.c | 2 +-
181
hw/misc/aspeed_scu.c | 194 ++++++-
182
hw/misc/aspeed_sdmc.c | 250 ++++++---
183
hw/misc/bcm2835_mbox.c | 14 +-
184
hw/misc/bcm2835_property.c | 20 +-
185
hw/net/fsl_etsec/etsec.c | 2 +-
186
hw/net/ftgmac100.c | 162 ++++++
187
hw/net/lan9118.c | 11 +-
188
hw/sd/aspeed_sdhci.c | 198 ++++++++
189
hw/ssi/aspeed_smc.c | 177 ++++++-
190
hw/timer/allwinner-a10-pit.c | 12 +-
191
hw/timer/altera_timer.c | 2 +-
192
hw/timer/arm_mptimer.c | 18 +-
193
hw/timer/arm_timer.c | 16 +-
194
hw/timer/aspeed_timer.c | 213 +++++++-
195
hw/timer/cmsdk-apb-dualtimer.c | 14 +-
196
hw/timer/cmsdk-apb-timer.c | 15 +-
197
hw/timer/digic-timer.c | 16 +-
198
hw/timer/etraxfs_timer.c | 6 +-
199
hw/timer/exynos4210_mct.c | 107 +++-
200
hw/timer/exynos4210_pwm.c | 17 +-
201
hw/timer/exynos4210_rtc.c | 22 +-
202
hw/timer/grlib_gptimer.c | 2 +-
203
hw/timer/imx_epit.c | 32 +-
204
hw/timer/imx_gpt.c | 21 +-
205
hw/timer/lm32_timer.c | 2 +-
206
hw/timer/milkymist-sysctl.c | 4 +-
207
hw/timer/mss-timer.c | 11 +-
208
hw/timer/puv3_ost.c | 2 +-
209
hw/timer/sh_timer.c | 2 +-
210
hw/timer/slavio_timer.c | 2 +-
211
hw/timer/xilinx_timer.c | 2 +-
212
hw/watchdog/cmsdk-apb-watchdog.c | 13 +-
213
hw/watchdog/wdt_aspeed.c | 153 +++---
214
target/arm/arm-semi.c | 707 +++++++++++++++++++++-----
215
target/arm/cpu.c | 10 +-
216
target/arm/kvm.c | 22 +-
217
tests/ptimer-test.c | 106 +++-
218
hw/misc/trace-events | 6 +
219
105 files changed, 3934 insertions(+), 650 deletions(-)
220
create mode 100644 include/hw/sd/aspeed_sdhci.h
221
create mode 100644 include/standard-headers/linux/virtio_fs.h
222
create mode 100644 include/standard-headers/linux/virtio_iommu.h
223
create mode 100644 hw/arm/aspeed_ast2600.c
224
create mode 100644 hw/sd/aspeed_sdhci.c
225
diff view generated by jsdifflib
[PULL 1/7] hw/arm/sbsa-ref: set 'slots' property of xhci
Deleted patch
1
From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
2
1
3
This extends the slots of xhci to 64, since the default xhci_sysbus
4
just supports one slot.
5
6
Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn>
7
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
10
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
11
Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/sbsa-ref.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/sbsa-ref.c
20
+++ b/hw/arm/sbsa-ref.c
21
@@ -XXX,XX +XXX,XX @@ static void create_xhci(const SBSAMachineState *sms)
22
hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
23
int irq = sbsa_ref_irqmap[SBSA_XHCI];
24
DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
25
+ qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
26
27
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
28
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
29
--
30
2.34.1
diff view generated by jsdifflib
[PULL 2/7] linux-user: Remove pointless NULL check in clock_adjtime handling
Deleted patch
1
In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
2
the address of the local variable htx. This means it can never be
3
NULL, but later in the code we check it for NULL anyway. Coverity
4
complains about this (CID 1507683) because the NULL check comes after
5
a call to clock_adjtime() that assumes it is non-NULL.
6
1
7
Since phtx is always &htx, and is used only in three places, it's not
8
really necessary. Remove it, bringing the code structure in to line
9
with that for TARGET_NR_clock_adjtime64, which already uses a simple
10
'&htx' when it wants a pointer to 'htx'.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org
16
---
17
linux-user/syscall.c | 12 +++++-------
18
1 file changed, 5 insertions(+), 7 deletions(-)
19
20
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/linux-user/syscall.c
23
+++ b/linux-user/syscall.c
24
@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,
25
#if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME)
26
case TARGET_NR_clock_adjtime:
27
{
28
- struct timex htx, *phtx = &htx;
29
+ struct timex htx;
30
31
- if (target_to_host_timex(phtx, arg2) != 0) {
32
+ if (target_to_host_timex(&htx, arg2) != 0) {
33
return -TARGET_EFAULT;
34
}
35
- ret = get_errno(clock_adjtime(arg1, phtx));
36
- if (!is_error(ret) && phtx) {
37
- if (host_to_target_timex(arg2, phtx) != 0) {
38
- return -TARGET_EFAULT;
39
- }
40
+ ret = get_errno(clock_adjtime(arg1, &htx));
41
+ if (!is_error(ret) && host_to_target_timex(arg2, &htx)) {
42
+ return -TARGET_EFAULT;
43
}
44
}
45
return ret;
46
--
47
2.34.1
48
49
diff view generated by jsdifflib
[PULL 3/7] target/arm/ptw.c: Add comments to S1Translate struct fields
Deleted patch
1
Add comments to the in_* fields in the S1Translate struct
2
that explain what they're doing.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org
7
---
8
target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++
9
1 file changed, 40 insertions(+)
10
11
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/ptw.c
14
+++ b/target/arm/ptw.c
15
@@ -XXX,XX +XXX,XX @@
16
#endif
17
18
typedef struct S1Translate {
19
+ /*
20
+ * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk.
21
+ * Together with in_space, specifies the architectural translation regime.
22
+ */
23
ARMMMUIdx in_mmu_idx;
24
+ /*
25
+ * in_ptw_idx: specifies which mmuidx to use for the actual
26
+ * page table descriptor load operations. This will be one of the
27
+ * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes.
28
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
29
+ * this field is updated accordingly.
30
+ */
31
ARMMMUIdx in_ptw_idx;
32
+ /*
33
+ * in_space: the security space for this walk. This plus
34
+ * the in_mmu_idx specify the architectural translation regime.
35
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
36
+ * this field is updated accordingly.
37
+ *
38
+ * Note that the security space for the in_ptw_idx may be different
39
+ * from that for the in_mmu_idx. We do not need to explicitly track
40
+ * the in_ptw_idx security space because:
41
+ * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx
42
+ * itself specifies the security space
43
+ * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security
44
+ * space used for ptw reads is the same as that of the security
45
+ * space of the stage 1 translation for all cases except where
46
+ * stage 1 is Secure; in that case the only possibilities for
47
+ * the ptw read are Secure and NonSecure, and the in_ptw_idx
48
+ * value being Stage2 vs Stage2_S distinguishes those.
49
+ */
50
ARMSecuritySpace in_space;
51
+ /*
52
+ * in_secure: whether the translation regime is a Secure one.
53
+ * This is always equal to arm_space_is_secure(in_space).
54
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
55
+ * this field is updated accordingly.
56
+ */
57
bool in_secure;
58
+ /*
59
+ * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug
60
+ * accesses will not update the guest page table access flags
61
+ * and will not change the state of the softmmu TLBs.
62
+ */
63
bool in_debug;
64
/*
65
* If this is stage 2 of a stage 1+2 page table walk, then this must
66
--
67
2.34.1
diff view generated by jsdifflib
[PULL 4/7] target/arm: Fix S1_ptw_translate() debug path
Deleted patch
1
In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate()
2
so that the debug-access "call get_phys_addr_*" codepath is used both
3
when S1 is doing ptw reads from stage 2 and when it is doing ptw
4
reads from physical memory. However, we didn't update the
5
calculation of s2ptw->in_space and s2ptw->in_secure to account for
6
the "ptw reads from physical memory" case. This meant that debug
7
accesses when in Secure state broke.
8
1
9
Create a new function S2_security_space() which returns the
10
correct security space to use for the ptw load, and use it to
11
determine the correct .in_secure and .in_space fields for the
12
stage 2 lookup for the ptw load.
13
14
Reported-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org
19
Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate")
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++-----
23
1 file changed, 32 insertions(+), 5 deletions(-)
24
25
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/ptw.c
28
+++ b/target/arm/ptw.c
29
@@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
30
}
31
}
32
33
+static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space,
34
+ ARMMMUIdx s2_mmu_idx)
35
+{
36
+ /*
37
+ * Return the security space to use for stage 2 when doing
38
+ * the S1 page table descriptor load.
39
+ */
40
+ if (regime_is_stage2(s2_mmu_idx)) {
41
+ /*
42
+ * The security space for ptw reads is almost always the same
43
+ * as that of the security space of the stage 1 translation.
44
+ * The only exception is when stage 1 is Secure; in that case
45
+ * the ptw read might be to the Secure or the NonSecure space
46
+ * (but never Realm or Root), and the s2_mmu_idx tells us which.
47
+ * Root translations are always single-stage.
48
+ */
49
+ if (s1_space == ARMSS_Secure) {
50
+ return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S);
51
+ } else {
52
+ assert(s2_mmu_idx != ARMMMUIdx_Stage2_S);
53
+ assert(s1_space != ARMSS_Root);
54
+ return s1_space;
55
+ }
56
+ } else {
57
+ /* ptw loads are from phys: the mmu idx itself says which space */
58
+ return arm_phys_to_space(s2_mmu_idx);
59
+ }
60
+}
61
+
62
/* Translate a S1 pagetable walk through S2 if needed. */
63
static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
64
hwaddr addr, ARMMMUFaultInfo *fi)
65
{
66
- ARMSecuritySpace space = ptw->in_space;
67
bool is_secure = ptw->in_secure;
68
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
69
ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
70
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
71
* From gdbstub, do not use softmmu so that we don't modify the
72
* state of the cpu at all, including softmmu tlb contents.
73
*/
74
+ ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx);
75
S1Translate s2ptw = {
76
.in_mmu_idx = s2_mmu_idx,
77
.in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
78
- .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
79
- .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
80
- : space == ARMSS_Realm ? ARMSS_Realm
81
- : ARMSS_NonSecure),
82
+ .in_secure = arm_space_is_secure(s2_space),
83
+ .in_space = s2_space,
84
.in_debug = true,
85
};
86
GetPhysAddrResult s2 = { };
87
--
88
2.34.1
diff view generated by jsdifflib
[PULL 5/7] target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
Deleted patch
1
In get_phys_addr_twostage() the code that applies the effects of
2
VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure.
3
Now we also have f.attrs.space for FEAT_RME, we need to keep the two
4
in sync.
5
1
6
These bits only have an effect for Secure space translations, not
7
for Root, so use the input in_space field to determine whether to
8
apply them rather than the input is_secure. This doesn't actually
9
make a difference because Root translations are never two-stage,
10
but it's a little clearer.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org
15
---
16
target/arm/ptw.c | 13 ++++++++-----
17
1 file changed, 8 insertions(+), 5 deletions(-)
18
19
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/ptw.c
22
+++ b/target/arm/ptw.c
23
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
24
hwaddr ipa;
25
int s1_prot, s1_lgpgsz;
26
bool is_secure = ptw->in_secure;
27
+ ARMSecuritySpace in_space = ptw->in_space;
28
bool ret, ipa_secure;
29
ARMCacheAttrs cacheattrs1;
30
ARMSecuritySpace ipa_space;
31
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
32
* Check if IPA translates to secure or non-secure PA space.
33
* Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
34
*/
35
- result->f.attrs.secure =
36
- (is_secure
37
- && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
38
- && (ipa_secure
39
- || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
40
+ if (in_space == ARMSS_Secure) {
41
+ result->f.attrs.secure =
42
+ !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
43
+ && (ipa_secure
44
+ || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)));
45
+ result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure);
46
+ }
47
48
return false;
49
}
50
--
51
2.34.1
diff view generated by jsdifflib
[PULL 6/7] accel/tcg: Zero-pad PC in TCG CPU exec trace lines
Deleted patch
1
In commit f0a08b0913befbd we changed the type of the PC from
2
target_ulong to vaddr. In doing so we inadvertently dropped the
3
zero-padding on the PC in trace lines (the second item inside the []
4
in these lines). They used to look like this on AArch64, for
5
instance:
6
1
7
Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000]
8
9
and now they look like this:
10
Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000]
11
12
and if the PC happens to be somewhere low like 0x5000
13
then the field is shown as /5000/.
14
15
This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier,
16
depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64
17
with no width specifier.
18
19
Restore the zero-padding by adding an 016 width specifier to
20
this tracing and a couple of others that were similarly recently
21
changed to use VADDR_PRIx without a width specifier.
22
23
We can't unfortunately restore the "32-bit guests are padded to
24
8 hex digits and 64-bit guests to 16 hex digits" behaviour so
25
easily.
26
27
Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr")
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
30
Reviewed-by: Anton Johansson <anjo@rev.ng>
31
Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org
32
---
33
accel/tcg/cpu-exec.c | 4 ++--
34
accel/tcg/translate-all.c | 2 +-
35
2 files changed, 3 insertions(+), 3 deletions(-)
36
37
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/cpu-exec.c
40
+++ b/accel/tcg/cpu-exec.c
41
@@ -XXX,XX +XXX,XX @@ static void log_cpu_exec(vaddr pc, CPUState *cpu,
42
if (qemu_log_in_addr_range(pc)) {
43
qemu_log_mask(CPU_LOG_EXEC,
44
"Trace %d: %p [%08" PRIx64
45
- "/%" VADDR_PRIx "/%08x/%08x] %s\n",
46
+ "/%016" VADDR_PRIx "/%08x/%08x] %s\n",
47
cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
48
tb->flags, tb->cflags, lookup_symbol(pc));
49
50
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
51
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
52
vaddr pc = log_pc(cpu, last_tb);
53
if (qemu_log_in_addr_range(pc)) {
54
- qemu_log("Stopped execution of TB chain before %p [%"
55
+ qemu_log("Stopped execution of TB chain before %p [%016"
56
VADDR_PRIx "] %s\n",
57
last_tb->tc.ptr, pc, lookup_symbol(pc));
58
}
59
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/accel/tcg/translate-all.c
62
+++ b/accel/tcg/translate-all.c
63
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
64
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
65
vaddr pc = log_pc(cpu, tb);
66
if (qemu_log_in_addr_range(pc)) {
67
- qemu_log("cpu_io_recompile: rewound execution of TB to %"
68
+ qemu_log("cpu_io_recompile: rewound execution of TB to %016"
69
VADDR_PRIx "\n", pc);
70
}
71
}
72
--
73
2.34.1
74
75
diff view generated by jsdifflib
[PULL 7/7] hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
Deleted patch
1
From: Tong Ho <tong.ho@amd.com>
2
1
3
Add a check in the bit-set operation to write the backstore
4
only if the affected bit is 0 before.
5
6
With this in place, there will be no need for callers to
7
do the checking in order to avoid unnecessary writes.
8
9
Signed-off-by: Tong Ho <tong.ho@amd.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/nvram/xlnx-efuse.c | 11 +++++++++--
16
1 file changed, 9 insertions(+), 2 deletions(-)
17
18
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/nvram/xlnx-efuse.c
21
+++ b/hw/nvram/xlnx-efuse.c
22
@@ -XXX,XX +XXX,XX @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
23
24
bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
25
{
26
+ uint32_t set, *row;
27
+
28
if (efuse_ro_bits_find(s, bit)) {
29
g_autofree char *path = object_get_canonical_path(OBJECT(s));
30
31
@@ -XXX,XX +XXX,XX @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
32
return false;
33
}
34
35
- s->fuse32[bit / 32] |= 1 << (bit % 32);
36
- efuse_bdrv_sync(s, bit);
37
+ /* Avoid back-end write unless there is a real update */
38
+ row = &s->fuse32[bit / 32];
39
+ set = 1 << (bit % 32);
40
+ if (!(set & *row)) {
41
+ *row |= set;
42
+ efuse_bdrv_sync(s, bit);
43
+ }
44
return true;
45
}
46
47
--
48
2.34.1
49
50
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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