The following changes since commit fcb237e64f9d026c03d635579c7b288d0008a6e5:

  Merge tag 'pull-vfio-20230710' of https://github.com/legoater/qemu into staging (2023-07-10 09:17:06 +0100)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/mips-20230710

for you to fetch changes up to 752dfff5ecf35a38145c2dfbb842224177fd1afd:

  hw/ide/piix: Move registration of VMStateDescription to DeviceClass (2023-07-11 00:11:25 +0200)

----------------------------------------------------------------
MIPS patches queue

- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
- Implement Loongson CSR instructions (Jiaxun)
- Implement Ingenic MXU ASE v1 rev2 (Siarhei)
- Enable GINVx support for I6400 and I6500 cores (Marcin)
- Generalize PCI IDE controller models (Bernhard)

----------------------------------------------------------------

Bernhard Beschow (7):
  hw/ide/pci: Expose legacy interrupts as named GPIOs
  hw/ide/via: Wire up IDE legacy interrupts in host device
  hw/isa/vt82c686: Remove via_isa_set_irq()
  hw/ide: Extract IDEBus assignment into bmdma_init()
  hw/ide: Extract bmdma_status_writeb()
  hw/ide/pci: Replace some magic numbers by constants
  hw/ide/piix: Move registration of VMStateDescription to DeviceClass

Jiaxun Yang (3):
  target/mips: Rework cp0_timer with clock API
  target/mips: Implement Loongson CSR instructions
  hw/mips/loongson3_virt: Relax CPU restrictions for TCG

Marcin Nowakowski (1):
  target/mips: enable GINVx support for I6400 and I6500

Siarhei Volkau (33):
  target/mips: Add emulation of MXU instructions for 32-bit load/store
  target/mips: Add support of two XBurst CPUs
  target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions
  target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions
  target/mips/mxu: Add Q8SLT Q8SLTU instructions
  target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions
  target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns
  target/mips/mxu: Add Q8ADD instruction
  target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns
  target/mips/mxu: Add D16MULF D16MULE instructions
  target/mips/mxu: Add D16MACF D16MACE instructions
  target/mips/mxu: Add D16MADL instruction
  target/mips/mxu: Add S16MAD instruction
  target/mips/mxu: Add Q16ADD instruction
  target/mips/mxu: Add D32ADD instruction
  target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions
  target/mips/mxu: Add D32ADDC instruction
  target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions
  target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions
  target/mips/mxu: Add S8STD S8LDI S8SDI instructions
  target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions
  target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns
  target/mips/mxu: Add S32ALN S32LUI insns
  target/mips/mxu: Add D32SARL D32SARW instructions
  target/mips/mxu: Add D32SLL D32SLR D32SAR instructions
  target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions
  target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions
  target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions
  target/mips/mxu: Add Q8MAC Q8MACSU instructions
  target/mips/mxu: Add Q16SCOP instruction
  target/mips/mxu: Add Q8MADL instruction
  target/mips/mxu: Add S32SFL instruction
  target/mips/mxu: Add Q8SAD instruction

 include/hw/ide/pci.h                 |    1 +
 include/hw/isa/vt82c686.h            |    2 -
 target/mips/cpu.h                    |   45 +-
 target/mips/helper.h                 |    4 +
 target/mips/internal.h               |    2 +
 target/mips/tcg/translate.h          |    1 +
 target/mips/tcg/sysemu_helper.h.inc  |    8 +
 target/mips/tcg/lcsr.decode          |   17 +
 hw/ide/cmd646.c                      |    3 +-
 hw/ide/pci.c                         |   16 +
 hw/ide/piix.c                        |    8 +-
 hw/ide/sii3112.c                     |    7 +-
 hw/ide/via.c                         |    9 +-
 hw/isa/vt82c686.c                    |   11 +-
 hw/mips/loongson3_virt.c             |    4 +-
 target/mips/cpu.c                    |   18 +-
 target/mips/sysemu/cp0_timer.c       |   35 +-
 target/mips/tcg/lcsr_translate.c     |   75 +
 target/mips/tcg/mxu_translate.c      | 3761 +++++++++++++++++++++++++-
 target/mips/tcg/op_helper.c          |   16 +
 target/mips/tcg/sysemu/lcsr_helper.c |   45 +
 target/mips/tcg/translate.c          |   10 +-
 target/mips/cpu-defs.c.inc           |   59 +-
 target/mips/tcg/meson.build          |    2 +
 target/mips/tcg/sysemu/meson.build   |    4 +
 25 files changed, 4001 insertions(+), 162 deletions(-)
 create mode 100644 target/mips/tcg/lcsr.decode
 create mode 100644 target/mips/tcg/lcsr_translate.c
 create mode 100644 target/mips/tcg/sysemu/lcsr_helper.c

-- 
2.38.1

On 7/10/23 23:25, Philippe Mathieu-Daudé wrote:
> The following changes since commit fcb237e64f9d026c03d635579c7b288d0008a6e5:
> 
>    Merge tag 'pull-vfio-20230710' ofhttps://github.com/legoater/qemu  into staging (2023-07-10 09:17:06 +0100)
> 
> are available in the Git repository at:
> 
>    https://github.com/philmd/qemu.git  tags/mips-20230710
> 
> for you to fetch changes up to 752dfff5ecf35a38145c2dfbb842224177fd1afd:
> 
>    hw/ide/piix: Move registration of VMStateDescription to DeviceClass (2023-07-11 00:11:25 +0200)
> 
> ----------------------------------------------------------------
> MIPS patches queue
> 
> - Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
> - Implement Loongson CSR instructions (Jiaxun)
> - Implement Ingenic MXU ASE v1 rev2 (Siarhei)
> - Enable GINVx support for I6400 and I6500 cores (Marcin)
> - Generalize PCI IDE controller models (Bernhard)

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.


r~