Changes v1->v2 (fixing CI failures in v1, added a couple of
extra patches in an attempt to avoid having to do a last
minute arm pullreq next week):
 * new patch to hopefully fix the build issue with the SVE/SME sysregs test
 * dropped the IC IVAU test case patch
 * new patch: fix over-length shift
 * new patches: define neoverse-v1

thanks
-- PMM

The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de:

  Merge tag 'pull-maintainer-ominbus-030723-1' of https://gitlab.com/stsquad/qemu into staging (2023-07-04 08:36:44 +0200)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230706

for you to fetch changes up to c41077235168140cdd4a34fce9bd95c3d30efe9c:

  target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case (2023-07-06 13:36:51 +0100)

----------------------------------------------------------------
target-arm queue:
 * Add raw_writes ops for register whose write induce TLB maintenance
 * hw/arm/sbsa-ref: use XHCI to replace EHCI
 * Avoid splitting Zregs across lines in dump
 * Dump ZA[] when active
 * Fix SME full tile indexing
 * Handle IC IVAU to improve compatibility with JITs
 * xlnx-canfd-test: Fix code coverity issues
 * gdbstub: Guard M-profile code with CONFIG_TCG
 * allwinner-sramc: Set class_size
 * target/xtensa: Assert that interrupt level is within bounds
 * Avoid over-length shift in arm_cpu_sve_finalize() error case
 * Define new 'neoverse-v1' CPU type

----------------------------------------------------------------
Akihiko Odaki (1):
      hw: arm: allwinner-sramc: Set class_size

Eric Auger (1):
      target/arm: Add raw_writes ops for register whose write induce TLB maintenance

Fabiano Rosas (1):
      target/arm: gdbstub: Guard M-profile code with CONFIG_TCG

John Högberg (1):
      target/arm: Handle IC IVAU to improve compatibility with JITs

Peter Maydell (5):
      tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1
      target/xtensa: Assert that interrupt level is within bounds
      target/arm: Suppress more TCG unimplemented features in ID registers
      target/arm: Define neoverse-v1
      target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case

Richard Henderson (3):
      target/arm: Avoid splitting Zregs across lines in dump
      target/arm: Dump ZA[] when active
      target/arm: Fix SME full tile indexing

Vikram Garhwal (1):
      tests/qtest: xlnx-canfd-test: Fix code coverity issues

Yuquan Wang (1):
      hw/arm/sbsa-ref: use XHCI to replace EHCI

 docs/system/arm/sbsa.rst          |   5 +-
 docs/system/arm/virt.rst          |   1 +
 hw/arm/sbsa-ref.c                 |  24 ++++---
 hw/arm/virt.c                     |   1 +
 hw/misc/allwinner-sramc.c         |   1 +
 target/arm/cpu.c                  |  98 +++++++++++++++++++++--------
 target/arm/cpu64.c                |   4 +-
 target/arm/gdbstub.c              |   4 ++
 target/arm/helper.c               |  70 +++++++++++++++++----
 target/arm/tcg/cpu64.c            | 128 ++++++++++++++++++++++++++++++++++++++
 target/arm/tcg/translate-sme.c    |  24 +++++--
 target/xtensa/exc_helper.c        |   3 +
 tests/qtest/xlnx-canfd-test.c     |  33 ++++------
 tests/tcg/aarch64/sme-outprod1.c  |  83 ++++++++++++++++++++++++
 tests/tcg/aarch64/sysregs.c       |  11 ++--
 hw/arm/Kconfig                    |   2 +-
 tests/tcg/aarch64/Makefile.target |  16 ++---
 17 files changed, 415 insertions(+), 93 deletions(-)
 create mode 100644 tests/tcg/aarch64/sme-outprod1.c

On 7/6/23 14:24, Peter Maydell wrote:
> Changes v1->v2 (fixing CI failures in v1, added a couple of
> extra patches in an attempt to avoid having to do a last
> minute arm pullreq next week):
>   * new patch to hopefully fix the build issue with the SVE/SME sysregs test
>   * dropped the IC IVAU test case patch
>   * new patch: fix over-length shift
>   * new patches: define neoverse-v1
> 
> thanks
> -- PMM
> 
> The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de:
> 
>    Merge tag 'pull-maintainer-ominbus-030723-1' ofhttps://gitlab.com/stsquad/qemu  into staging (2023-07-04 08:36:44 +0200)
> 
> are available in the Git repository at:
> 
>    https://git.linaro.org/people/pmaydell/qemu-arm.git  tags/pull-target-arm-20230706
> 
> for you to fetch changes up to c41077235168140cdd4a34fce9bd95c3d30efe9c:
> 
>    target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case (2023-07-06 13:36:51 +0100)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * Add raw_writes ops for register whose write induce TLB maintenance
>   * hw/arm/sbsa-ref: use XHCI to replace EHCI
>   * Avoid splitting Zregs across lines in dump
>   * Dump ZA[] when active
>   * Fix SME full tile indexing
>   * Handle IC IVAU to improve compatibility with JITs
>   * xlnx-canfd-test: Fix code coverity issues
>   * gdbstub: Guard M-profile code with CONFIG_TCG
>   * allwinner-sramc: Set class_size
>   * target/xtensa: Assert that interrupt level is within bounds
>   * Avoid over-length shift in arm_cpu_sve_finalize() error case
>   * Define new 'neoverse-v1' CPU type

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.


r~