[PULL 00/11] target-arm queue
[Qemu-devel] [PULL 00/28] target-arm queue
1
Just a collection of bug fixes this time around...
1
Arm queue. I still have a lot of stuff in my to-review queue, so
2
won't be long til the next one.
3
4
I've thrown in a couple of minor non-arm patches (a xen code
5
cleanup and a vl.c codestyle issue).
2
6
3
thanks
7
thanks
4
-- PMM
8
-- PMM
5
9
6
The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de:
10
The following changes since commit de44c044420d1139480fa50c2d5be19223391218:
7
11
8
Merge tag 'pull-maintainer-ominbus-030723-1' of https://gitlab.com/stsquad/qemu into staging (2023-07-04 08:36:44 +0200)
12
Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-testing-revivial-210618-2' into staging (2018-06-22 10:57:47 +0100)
9
13
10
are available in the Git repository at:
14
are available in the Git repository at:
11
15
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230704
16
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180622
13
17
14
for you to fetch changes up to 86a78272f094857b4eda79d721c116e93942aa9a:
18
for you to fetch changes up to 6dad8260e82b69bd278685ee25209f5824360455:
15
19
16
target/xtensa: Assert that interrupt level is within bounds (2023-07-04 14:27:08 +0100)
20
xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() (2018-06-22 13:28:42 +0100)
17
21
18
----------------------------------------------------------------
22
----------------------------------------------------------------
19
target-arm queue:
23
target-arm queue:
20
* Add raw_writes ops for register whose write induce TLB maintenance
24
* hw/intc/arm_gicv3: fix wrong values when reading IPRIORITYR
21
* hw/arm/sbsa-ref: use XHCI to replace EHCI
25
* target/arm: fix read of freed memory in kvm_arm_machine_init_done()
22
* Avoid splitting Zregs across lines in dump
26
* virt: support up to 512 CPUs
23
* Dump ZA[] when active
27
* virt: support 256MB ECAM PCI region (for more PCI devices)
24
* Fix SME full tile indexing
28
* xlnx-zynqmp: Use Cortex-R5F, not Cortex-R5
25
* Handle IC IVAU to improve compatibility with JITs
29
* mps2-tz: Implement and use the TrustZone Memory Protection Controller
26
* xlnx-canfd-test: Fix code coverity issues
30
* target/arm: enforce alignment checking for v6M cores
27
* gdbstub: Guard M-profile code with CONFIG_TCG
31
* xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom()
28
* allwinner-sramc: Set class_size
32
* vl.c: Don't zero-initialize statics for serial_hds
29
* target/xtensa: Assert that interrupt level is within bounds
30
33
31
----------------------------------------------------------------
34
----------------------------------------------------------------
32
Akihiko Odaki (1):
35
Amol Surati (1):
33
hw: arm: allwinner-sramc: Set class_size
36
hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR
34
37
35
Eric Auger (1):
38
Edgar E. Iglesias (2):
36
target/arm: Add raw_writes ops for register whose write induce TLB maintenance
39
target-arm: Add the Cortex-R5F
40
xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F
37
41
38
Fabiano Rosas (1):
42
Eric Auger (11):
39
target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
43
linux-headers: Update to kernel mainline commit b357bf602
44
target/arm: Allow KVM device address overwriting
45
hw/intc/arm_gicv3: Introduce redist-region-count array property
46
hw/intc/arm_gicv3_kvm: Get prepared to handle multiple redist regions
47
hw/arm/virt: GICv3 DT node with one or two redistributor regions
48
hw/arm/virt-acpi-build: Advertise one or two GICR structures
49
hw/arm/virt: Register two redistributor regions when necessary
50
hw/arm/virt: Add a new 256MB ECAM region
51
hw/arm/virt: Add virt-3.0 machine type
52
hw/arm/virt: Use 256MB ECAM region by default
53
hw/arm/virt: Increase max_cpus to 512
40
54
41
John Högberg (2):
55
Julia Suvorova (3):
42
target/arm: Handle IC IVAU to improve compatibility with JITs
56
target/arm: Minor cleanup for ARMv6-M 32-bit instructions
43
tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code
57
target/arm: Introduce ARM_FEATURE_M_MAIN
58
target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline
44
59
45
Peter Maydell (1):
60
Peter Maydell (10):
46
target/xtensa: Assert that interrupt level is within bounds
61
hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller
62
hw/misc/tz-mpc.c: Implement registers
63
hw/misc/tz-mpc.c: Implement correct blocked-access behaviour
64
hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate
65
hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS
66
hw/arm/iotkit: Instantiate MPC
67
hw/arm/iotkit: Wire up MPC interrupt lines
68
hw/arm/mps2-tz.c: Instantiate MPCs
69
vl.c: Don't zero-initialize statics for serial_hds
70
xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom()
47
71
48
Richard Henderson (3):
72
Zheng Xiang (1):
49
target/arm: Avoid splitting Zregs across lines in dump
73
target-arm: fix a segmentation fault due to illegal memory access
50
target/arm: Dump ZA[] when active
51
target/arm: Fix SME full tile indexing
52
74
53
Vikram Garhwal (1):
75
hw/misc/Makefile.objs | 1 +
54
tests/qtest: xlnx-canfd-test: Fix code coverity issues
76
hw/xen/xen_pt.h | 2 +-
77
include/hw/arm/iotkit.h | 8 +
78
include/hw/arm/virt.h | 19 +
79
include/hw/intc/arm_gicv3_common.h | 8 +-
80
include/hw/misc/iotkit-secctl.h | 8 +
81
include/hw/misc/tz-mpc.h | 80 +++
82
include/standard-headers/linux/pci_regs.h | 8 +
83
include/standard-headers/linux/virtio_gpu.h | 1 +
84
include/standard-headers/linux/virtio_net.h | 3 +
85
linux-headers/asm-arm/kvm.h | 1 +
86
linux-headers/asm-arm/unistd-common.h | 1 +
87
linux-headers/asm-arm64/kvm.h | 1 +
88
linux-headers/asm-generic/unistd.h | 4 +-
89
linux-headers/asm-powerpc/unistd.h | 1 +
90
linux-headers/asm-x86/unistd_32.h | 2 +
91
linux-headers/asm-x86/unistd_64.h | 2 +
92
linux-headers/asm-x86/unistd_x32.h | 2 +
93
linux-headers/linux/kvm.h | 5 +-
94
linux-headers/linux/psp-sev.h | 12 +
95
target/arm/cpu.h | 1 +
96
target/arm/kvm_arm.h | 3 +-
97
hw/arm/iotkit.c | 112 +++-
98
hw/arm/mps2-tz.c | 71 ++-
99
hw/arm/virt-acpi-build.c | 30 +-
100
hw/arm/virt.c | 100 +++-
101
hw/arm/xlnx-zcu102.c | 2 +-
102
hw/arm/xlnx-zynqmp.c | 2 +-
103
hw/intc/arm_gic_kvm.c | 4 +-
104
hw/intc/arm_gicv3.c | 12 +-
105
hw/intc/arm_gicv3_common.c | 38 +-
106
hw/intc/arm_gicv3_dist.c | 3 +-
107
hw/intc/arm_gicv3_its_kvm.c | 2 +-
108
hw/intc/arm_gicv3_kvm.c | 44 +-
109
hw/intc/arm_gicv3_redist.c | 3 +-
110
hw/misc/iotkit-secctl.c | 38 +-
111
hw/misc/tz-mpc.c | 628 +++++++++++++++++++++
112
hw/xen/xen_pt_graphics.c | 2 +-
113
hw/xen/xen_pt_load_rom.c | 6 +-
114
target/arm/cpu.c | 12 +
115
target/arm/kvm.c | 11 +-
116
target/arm/translate.c | 45 +-
117
vl.c | 4 +-
118
MAINTAINERS | 2 +
119
default-configs/arm-softmmu.mak | 1 +
120
hw/misc/trace-events | 8 +
121
.../LICENSES/exceptions/Linux-syscall-note | 2 +-
122
linux-headers/LICENSES/preferred/GPL-2.0 | 6 +
123
48 files changed, 1250 insertions(+), 111 deletions(-)
124
create mode 100644 include/hw/misc/tz-mpc.h
125
create mode 100644 hw/misc/tz-mpc.c
55
126
56
Yuquan Wang (1):
57
hw/arm/sbsa-ref: use XHCI to replace EHCI
58
59
docs/system/arm/sbsa.rst | 5 +-
60
hw/arm/sbsa-ref.c | 23 +++--
61
hw/misc/allwinner-sramc.c | 1 +
62
target/arm/cpu.c | 65 ++++++++-----
63
target/arm/gdbstub.c | 4 +
64
target/arm/helper.c | 70 +++++++++++---
65
target/arm/tcg/translate-sme.c | 24 +++--
66
target/xtensa/exc_helper.c | 3 +
67
tests/qtest/xlnx-canfd-test.c | 33 +++----
68
tests/tcg/aarch64/icivau.c | 189 ++++++++++++++++++++++++++++++++++++++
69
tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++
70
hw/arm/Kconfig | 2 +-
71
tests/tcg/aarch64/Makefile.target | 13 ++-
72
13 files changed, 436 insertions(+), 79 deletions(-)
73
create mode 100644 tests/tcg/aarch64/icivau.c
74
create mode 100644 tests/tcg/aarch64/sme-outprod1.c
75
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 01/28] hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR
1
From: Amol Surati <suratiamol@gmail.com>
1
2
3
When either GICD_IPRIORITYR or GICR_IPRIORITYR is read as a 32-bit
4
register, the post left-shift operator in the for loop causes an
5
extra shift after the least significant byte has been placed.
6
7
The 32-bit value actually returned is therefore the expected value
8
shifted left by 8 bits.
9
10
Signed-off-by: Amol Surati <suratiamol@gmail.com>
11
Message-id: 20180614054857.26248-1-suratiamol@gmail.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/intc/arm_gicv3_dist.c | 3 ++-
16
hw/intc/arm_gicv3_redist.c | 3 ++-
17
2 files changed, 4 insertions(+), 2 deletions(-)
18
19
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/intc/arm_gicv3_dist.c
22
+++ b/hw/intc/arm_gicv3_dist.c
23
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
24
int i, irq = offset - GICD_IPRIORITYR;
25
uint32_t value = 0;
26
27
- for (i = irq + 3; i >= irq; i--, value <<= 8) {
28
+ for (i = irq + 3; i >= irq; i--) {
29
+ value <<= 8;
30
value |= gicd_read_ipriorityr(s, attrs, i);
31
}
32
*data = value;
33
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/intc/arm_gicv3_redist.c
36
+++ b/hw/intc/arm_gicv3_redist.c
37
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
38
int i, irq = offset - GICR_IPRIORITYR;
39
uint32_t value = 0;
40
41
- for (i = irq + 3; i >= irq; i--, value <<= 8) {
42
+ for (i = irq + 3; i >= irq; i--) {
43
+ value <<= 8;
44
value |= gicr_read_ipriorityr(cs, attrs, i);
45
}
46
*data = value;
47
--
48
2.17.1
49
50
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 02/28] target/arm: Minor cleanup for ARMv6-M 32-bit instructions
1
From: Julia Suvorova <jusual@mail.ru>
1
2
3
The arrays were made static, "if" was simplified because V7M and V8M
4
define V6 feature.
5
6
Signed-off-by: Julia Suvorova <jusual@mail.ru>
7
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
8
Message-id: 20180618214604.6777-1-jusual@mail.ru
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate.c | 27 +++++++++++++--------------
13
1 file changed, 13 insertions(+), 14 deletions(-)
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
20
!arm_dc_feature(s, ARM_FEATURE_V7)) {
21
int i;
22
bool found = false;
23
- const uint32_t armv6m_insn[] = {0xf3808000 /* msr */,
24
- 0xf3b08040 /* dsb */,
25
- 0xf3b08050 /* dmb */,
26
- 0xf3b08060 /* isb */,
27
- 0xf3e08000 /* mrs */,
28
- 0xf000d000 /* bl */};
29
- const uint32_t armv6m_mask[] = {0xffe0d000,
30
- 0xfff0d0f0,
31
- 0xfff0d0f0,
32
- 0xfff0d0f0,
33
- 0xffe0d000,
34
- 0xf800d000};
35
+ static const uint32_t armv6m_insn[] = {0xf3808000 /* msr */,
36
+ 0xf3b08040 /* dsb */,
37
+ 0xf3b08050 /* dmb */,
38
+ 0xf3b08060 /* isb */,
39
+ 0xf3e08000 /* mrs */,
40
+ 0xf000d000 /* bl */};
41
+ static const uint32_t armv6m_mask[] = {0xffe0d000,
42
+ 0xfff0d0f0,
43
+ 0xfff0d0f0,
44
+ 0xfff0d0f0,
45
+ 0xffe0d000,
46
+ 0xf800d000};
47
48
for (i = 0; i < ARRAY_SIZE(armv6m_insn); i++) {
49
if ((insn & armv6m_mask[i]) == armv6m_insn[i]) {
50
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
51
break;
52
case 3: /* Special control operations. */
53
if (!arm_dc_feature(s, ARM_FEATURE_V7) &&
54
- !(arm_dc_feature(s, ARM_FEATURE_V6) &&
55
- arm_dc_feature(s, ARM_FEATURE_M))) {
56
+ !arm_dc_feature(s, ARM_FEATURE_M)) {
57
goto illegal_op;
58
}
59
op = (insn >> 4) & 0xf;
60
--
61
2.17.1
62
63
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 03/28] target-arm: fix a segmentation fault due to illegal memory access
1
From: Zheng Xiang <xiang.zheng@linaro.org>
1
2
3
The elements of kvm_devices_head list are freed in kvm_arm_machine_init_done(),
4
but we still access these illegal memory in kvm_arm_devlistener_del().
5
6
This will cause segment fault when booting guest with MALLOC_PERTURB_=1.
7
8
Signed-off-by: Zheng Xiang <xiang.zheng@linaro.org>
9
Message-id: 20180619075821.9884-1-zhengxiang9@huawei.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/kvm.c | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm.c
19
+++ b/target/arm/kvm.c
20
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_machine_init_done(Notifier *notifier, void *data)
21
kvm_arm_set_device_addr(kd);
22
}
23
memory_region_unref(kd->mr);
24
+ QSLIST_REMOVE_HEAD(&kvm_devices_head, entries);
25
g_free(kd);
26
}
27
memory_listener_unregister(&devlistener);
28
--
29
2.17.1
30
31
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 04/28] linux-headers: Update to kernel mainline commit b357bf602
1
1
From: Eric Auger <eric.auger@redhat.com>
2
3
Update our kernel headers to mainline commit
4
b357bf6023a948cf6a9472f07a1b0caac0e4f8e8
5
("Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm")
6
7
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 1529072910-16156-2-git-send-email-eric.auger@redhat.com
9
[PMM: clarified commit message]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/standard-headers/linux/pci_regs.h | 8 ++++++++
13
include/standard-headers/linux/virtio_gpu.h | 1 +
14
include/standard-headers/linux/virtio_net.h | 3 +++
15
linux-headers/asm-arm/kvm.h | 1 +
16
linux-headers/asm-arm/unistd-common.h | 1 +
17
linux-headers/asm-arm64/kvm.h | 1 +
18
linux-headers/asm-generic/unistd.h | 4 +++-
19
linux-headers/asm-powerpc/unistd.h | 1 +
20
linux-headers/asm-x86/unistd_32.h | 2 ++
21
linux-headers/asm-x86/unistd_64.h | 2 ++
22
linux-headers/asm-x86/unistd_x32.h | 2 ++
23
linux-headers/linux/kvm.h | 5 +++--
24
linux-headers/linux/psp-sev.h | 12 ++++++++++++
25
linux-headers/LICENSES/exceptions/Linux-syscall-note | 2 +-
26
linux-headers/LICENSES/preferred/GPL-2.0 | 6 ++++++
27
15 files changed, 47 insertions(+), 4 deletions(-)
28
29
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/standard-headers/linux/pci_regs.h
32
+++ b/include/standard-headers/linux/pci_regs.h
33
@@ -XXX,XX +XXX,XX @@
34
#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
35
#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
36
#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
37
+#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
38
+#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
39
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
40
#define PCI_EXP_DEVSTA        10    /* Device Status */
41
#define PCI_EXP_DEVSTA_CED    0x0001    /* Correctable Error Detected */
42
@@ -XXX,XX +XXX,XX @@
43
#define PCI_EXP_LNKCAP2_SLS_16_0GB    0x00000010 /* Supported Speed 16GT/s */
44
#define PCI_EXP_LNKCAP2_CROSSLINK    0x00000100 /* Crosslink supported */
45
#define PCI_EXP_LNKCTL2        48    /* Link Control 2 */
46
+#define PCI_EXP_LNKCTL2_TLS        0x000f
47
+#define PCI_EXP_LNKCTL2_TLS_2_5GT    0x0001 /* Supported Speed 2.5GT/s */
48
+#define PCI_EXP_LNKCTL2_TLS_5_0GT    0x0002 /* Supported Speed 5GT/s */
49
+#define PCI_EXP_LNKCTL2_TLS_8_0GT    0x0003 /* Supported Speed 8GT/s */
50
+#define PCI_EXP_LNKCTL2_TLS_16_0GT    0x0004 /* Supported Speed 16GT/s */
51
#define PCI_EXP_LNKSTA2        50    /* Link Status 2 */
52
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2    52    /* v2 endpoints with link end here */
53
#define PCI_EXP_SLTCAP2        52    /* Slot Capabilities 2 */
54
@@ -XXX,XX +XXX,XX @@
55
#define PCI_EXP_DPC_CAP_DL_ACTIVE    0x1000    /* ERR_COR signal on DL_Active supported */
56
57
#define PCI_EXP_DPC_CTL            6    /* DPC control */
58
+#define PCI_EXP_DPC_CTL_EN_FATAL     0x0001    /* Enable trigger on ERR_FATAL message */
59
#define PCI_EXP_DPC_CTL_EN_NONFATAL     0x0002    /* Enable trigger on ERR_NONFATAL message */
60
#define PCI_EXP_DPC_CTL_INT_EN     0x0008    /* DPC Interrupt Enable */
61
62
diff --git a/include/standard-headers/linux/virtio_gpu.h b/include/standard-headers/linux/virtio_gpu.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/standard-headers/linux/virtio_gpu.h
65
+++ b/include/standard-headers/linux/virtio_gpu.h
66
@@ -XXX,XX +XXX,XX @@ struct virtio_gpu_cmd_submit {
67
};
68
69
#define VIRTIO_GPU_CAPSET_VIRGL 1
70
+#define VIRTIO_GPU_CAPSET_VIRGL2 2
71
72
/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
73
struct virtio_gpu_get_capset_info {
74
diff --git a/include/standard-headers/linux/virtio_net.h b/include/standard-headers/linux/virtio_net.h
75
index XXXXXXX..XXXXXXX 100644
76
--- a/include/standard-headers/linux/virtio_net.h
77
+++ b/include/standard-headers/linux/virtio_net.h
78
@@ -XXX,XX +XXX,XX @@
79
                     * Steering */
80
#define VIRTIO_NET_F_CTRL_MAC_ADDR 23    /* Set MAC address */
81
82
+#define VIRTIO_NET_F_STANDBY     62    /* Act as standby for another device
83
+                     * with the same MAC.
84
+                     */
85
#define VIRTIO_NET_F_SPEED_DUPLEX 63    /* Device set linkspeed and duplex */
86
87
#ifndef VIRTIO_NET_NO_LEGACY
88
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
89
index XXXXXXX..XXXXXXX 100644
90
--- a/linux-headers/asm-arm/kvm.h
91
+++ b/linux-headers/asm-arm/kvm.h
92
@@ -XXX,XX +XXX,XX @@ struct kvm_regs {
93
#define KVM_VGIC_V3_ADDR_TYPE_DIST    2
94
#define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
95
#define KVM_VGIC_ITS_ADDR_TYPE        4
96
+#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION    5
97
98
#define KVM_VGIC_V3_DIST_SIZE        SZ_64K
99
#define KVM_VGIC_V3_REDIST_SIZE        (2 * SZ_64K)
100
diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h
101
index XXXXXXX..XXXXXXX 100644
102
--- a/linux-headers/asm-arm/unistd-common.h
103
+++ b/linux-headers/asm-arm/unistd-common.h
104
@@ -XXX,XX +XXX,XX @@
105
#define __NR_pkey_alloc (__NR_SYSCALL_BASE + 395)
106
#define __NR_pkey_free (__NR_SYSCALL_BASE + 396)
107
#define __NR_statx (__NR_SYSCALL_BASE + 397)
108
+#define __NR_rseq (__NR_SYSCALL_BASE + 398)
109
110
#endif /* _ASM_ARM_UNISTD_COMMON_H */
111
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
112
index XXXXXXX..XXXXXXX 100644
113
--- a/linux-headers/asm-arm64/kvm.h
114
+++ b/linux-headers/asm-arm64/kvm.h
115
@@ -XXX,XX +XXX,XX @@ struct kvm_regs {
116
#define KVM_VGIC_V3_ADDR_TYPE_DIST    2
117
#define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
118
#define KVM_VGIC_ITS_ADDR_TYPE        4
119
+#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION    5
120
121
#define KVM_VGIC_V3_DIST_SIZE        SZ_64K
122
#define KVM_VGIC_V3_REDIST_SIZE        (2 * SZ_64K)
123
diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h
124
index XXXXXXX..XXXXXXX 100644
125
--- a/linux-headers/asm-generic/unistd.h
126
+++ b/linux-headers/asm-generic/unistd.h
127
@@ -XXX,XX +XXX,XX @@ __SYSCALL(__NR_pkey_alloc, sys_pkey_alloc)
128
__SYSCALL(__NR_pkey_free, sys_pkey_free)
129
#define __NR_statx 291
130
__SYSCALL(__NR_statx, sys_statx)
131
+#define __NR_io_pgetevents 292
132
+__SC_COMP(__NR_io_pgetevents, sys_io_pgetevents, compat_sys_io_pgetevents)
133
134
#undef __NR_syscalls
135
-#define __NR_syscalls 292
136
+#define __NR_syscalls 293
137
138
/*
139
* 32 bit systems traditionally used different
140
diff --git a/linux-headers/asm-powerpc/unistd.h b/linux-headers/asm-powerpc/unistd.h
141
index XXXXXXX..XXXXXXX 100644
142
--- a/linux-headers/asm-powerpc/unistd.h
143
+++ b/linux-headers/asm-powerpc/unistd.h
144
@@ -XXX,XX +XXX,XX @@
145
#define __NR_pkey_alloc        384
146
#define __NR_pkey_free        385
147
#define __NR_pkey_mprotect    386
148
+#define __NR_rseq        387
149
150
#endif /* _ASM_POWERPC_UNISTD_H_ */
151
diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h
152
index XXXXXXX..XXXXXXX 100644
153
--- a/linux-headers/asm-x86/unistd_32.h
154
+++ b/linux-headers/asm-x86/unistd_32.h
155
@@ -XXX,XX +XXX,XX @@
156
#define __NR_pkey_free 382
157
#define __NR_statx 383
158
#define __NR_arch_prctl 384
159
+#define __NR_io_pgetevents 385
160
+#define __NR_rseq 386
161
162
#endif /* _ASM_X86_UNISTD_32_H */
163
diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/linux-headers/asm-x86/unistd_64.h
166
+++ b/linux-headers/asm-x86/unistd_64.h
167
@@ -XXX,XX +XXX,XX @@
168
#define __NR_pkey_alloc 330
169
#define __NR_pkey_free 331
170
#define __NR_statx 332
171
+#define __NR_io_pgetevents 333
172
+#define __NR_rseq 334
173
174
#endif /* _ASM_X86_UNISTD_64_H */
175
diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h
176
index XXXXXXX..XXXXXXX 100644
177
--- a/linux-headers/asm-x86/unistd_x32.h
178
+++ b/linux-headers/asm-x86/unistd_x32.h
179
@@ -XXX,XX +XXX,XX @@
180
#define __NR_pkey_alloc (__X32_SYSCALL_BIT + 330)
181
#define __NR_pkey_free (__X32_SYSCALL_BIT + 331)
182
#define __NR_statx (__X32_SYSCALL_BIT + 332)
183
+#define __NR_io_pgetevents (__X32_SYSCALL_BIT + 333)
184
+#define __NR_rseq (__X32_SYSCALL_BIT + 334)
185
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
186
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
187
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
188
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
189
index XXXXXXX..XXXXXXX 100644
190
--- a/linux-headers/linux/kvm.h
191
+++ b/linux-headers/linux/kvm.h
192
@@ -XXX,XX +XXX,XX @@ struct kvm_ioeventfd {
193
};
194
195
#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0)
196
-#define KVM_X86_DISABLE_EXITS_HTL (1 << 1)
197
+#define KVM_X86_DISABLE_EXITS_HLT (1 << 1)
198
#define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2)
199
#define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT | \
200
- KVM_X86_DISABLE_EXITS_HTL | \
201
+ KVM_X86_DISABLE_EXITS_HLT | \
202
KVM_X86_DISABLE_EXITS_PAUSE)
203
204
/* for KVM_ENABLE_CAP */
205
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
206
#define KVM_CAP_S390_BPB 152
207
#define KVM_CAP_GET_MSR_FEATURES 153
208
#define KVM_CAP_HYPERV_EVENTFD 154
209
+#define KVM_CAP_HYPERV_TLBFLUSH 155
210
211
#ifdef KVM_CAP_IRQ_ROUTING
212
213
diff --git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h
214
index XXXXXXX..XXXXXXX 100644
215
--- a/linux-headers/linux/psp-sev.h
216
+++ b/linux-headers/linux/psp-sev.h
217
@@ -XXX,XX +XXX,XX @@ enum {
218
    SEV_PDH_GEN,
219
    SEV_PDH_CERT_EXPORT,
220
    SEV_PEK_CERT_IMPORT,
221
+    SEV_GET_ID,
222
223
    SEV_MAX,
224
};
225
@@ -XXX,XX +XXX,XX @@ struct sev_user_data_pdh_cert_export {
226
    __u32 cert_chain_len;            /* In/Out */
227
} __attribute__((packed));
228
229
+/**
230
+ * struct sev_user_data_get_id - GET_ID command parameters
231
+ *
232
+ * @socket1: Buffer to pass unique ID of first socket
233
+ * @socket2: Buffer to pass unique ID of second socket
234
+ */
235
+struct sev_user_data_get_id {
236
+    __u8 socket1[64];            /* Out */
237
+    __u8 socket2[64];            /* Out */
238
+} __attribute__((packed));
239
+
240
/**
241
* struct sev_issue_cmd - SEV ioctl parameters
242
*
243
diff --git a/linux-headers/LICENSES/exceptions/Linux-syscall-note b/linux-headers/LICENSES/exceptions/Linux-syscall-note
244
index XXXXXXX..XXXXXXX 100644
245
--- a/linux-headers/LICENSES/exceptions/Linux-syscall-note
246
+++ b/linux-headers/LICENSES/exceptions/Linux-syscall-note
247
@@ -XXX,XX +XXX,XX @@
248
SPDX-Exception-Identifier: Linux-syscall-note
249
SPDX-URL: https://spdx.org/licenses/Linux-syscall-note.html
250
-SPDX-Licenses: GPL-2.0, GPL-2.0+, GPL-1.0+, LGPL-2.0, LGPL-2.0+, LGPL-2.1, LGPL-2.1+
251
+SPDX-Licenses: GPL-2.0, GPL-2.0+, GPL-1.0+, LGPL-2.0, LGPL-2.0+, LGPL-2.1, LGPL-2.1+, GPL-2.0-only, GPL-2.0-or-later
252
Usage-Guide:
253
This exception is used together with one of the above SPDX-Licenses
254
to mark user space API (uapi) header files so they can be included
255
diff --git a/linux-headers/LICENSES/preferred/GPL-2.0 b/linux-headers/LICENSES/preferred/GPL-2.0
256
index XXXXXXX..XXXXXXX 100644
257
--- a/linux-headers/LICENSES/preferred/GPL-2.0
258
+++ b/linux-headers/LICENSES/preferred/GPL-2.0
259
@@ -XXX,XX +XXX,XX @@
260
Valid-License-Identifier: GPL-2.0
261
+Valid-License-Identifier: GPL-2.0-only
262
Valid-License-Identifier: GPL-2.0+
263
+Valid-License-Identifier: GPL-2.0-or-later
264
SPDX-URL: https://spdx.org/licenses/GPL-2.0.html
265
Usage-Guide:
266
To use this license in source code, put one of the following SPDX
267
@@ -XXX,XX +XXX,XX @@ Usage-Guide:
268
guidelines in the licensing rules documentation.
269
For 'GNU General Public License (GPL) version 2 only' use:
270
SPDX-License-Identifier: GPL-2.0
271
+ or
272
+ SPDX-License-Identifier: GPL-2.0-only
273
For 'GNU General Public License (GPL) version 2 or any later version' use:
274
SPDX-License-Identifier: GPL-2.0+
275
+ or
276
+ SPDX-License-Identifier: GPL-2.0-or-later
277
License-Text:
278
279
         GNU GENERAL PUBLIC LICENSE
280
--
281
2.17.1
282
283
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 05/28] target/arm: Allow KVM device address overwriting
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attribute, the attribute
4
data pointed to by kvm_device_attr.addr is a OR of the
5
redistributor region address and other fields such as the index
6
of the redistributor region and the number of redistributors the
7
region can contain.
8
9
The existing machine init done notifier framework sets the address
10
field to the actual address of the device and does not allow to OR
11
this value with other fields.
12
13
This patch extends the KVMDevice struct with a new kda_addr_ormask
14
member. Its value is passed at registration time and OR'ed with the
15
resolved address on kvm_arm_set_device_addr().
16
17
Signed-off-by: Eric Auger <eric.auger@redhat.com>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: 1529072910-16156-3-git-send-email-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
target/arm/kvm_arm.h | 3 ++-
23
hw/intc/arm_gic_kvm.c | 4 ++--
24
hw/intc/arm_gicv3_its_kvm.c | 2 +-
25
hw/intc/arm_gicv3_kvm.c | 4 ++--
26
target/arm/kvm.c | 10 +++++++++-
27
5 files changed, 16 insertions(+), 7 deletions(-)
28
29
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/kvm_arm.h
32
+++ b/target/arm/kvm_arm.h
33
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs);
34
* @group: device control API group for setting addresses
35
* @attr: device control API address type
36
* @dev_fd: device control device file descriptor (or -1 if not supported)
37
+ * @addr_ormask: value to be OR'ed with resolved address
38
*
39
* Remember the memory region @mr, and when it is mapped by the
40
* machine model, tell the kernel that base address using the
41
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs);
42
* address at the point where machine init is complete.
43
*/
44
void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
45
- uint64_t attr, int dev_fd);
46
+ uint64_t attr, int dev_fd, uint64_t addr_ormask);
47
48
/**
49
* kvm_arm_init_cpreg_list:
50
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/intc/arm_gic_kvm.c
53
+++ b/hw/intc/arm_gic_kvm.c
54
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
55
| KVM_VGIC_V2_ADDR_TYPE_DIST,
56
KVM_DEV_ARM_VGIC_GRP_ADDR,
57
KVM_VGIC_V2_ADDR_TYPE_DIST,
58
- s->dev_fd);
59
+ s->dev_fd, 0);
60
/* CPU interface for current core. Unlike arm_gic, we don't
61
* provide the "interface for core #N" memory regions, because
62
* cores with a VGIC don't have those.
63
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
64
| KVM_VGIC_V2_ADDR_TYPE_CPU,
65
KVM_DEV_ARM_VGIC_GRP_ADDR,
66
KVM_VGIC_V2_ADDR_TYPE_CPU,
67
- s->dev_fd);
68
+ s->dev_fd, 0);
69
70
if (kvm_has_gsi_routing()) {
71
/* set up irq routing */
72
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/intc/arm_gicv3_its_kvm.c
75
+++ b/hw/intc/arm_gicv3_its_kvm.c
76
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
77
78
/* register the base address */
79
kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
80
- KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd);
81
+ KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
82
83
gicv3_its_init_mmio(s, NULL);
84
85
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/intc/arm_gicv3_kvm.c
88
+++ b/hw/intc/arm_gicv3_kvm.c
89
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
90
KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
91
92
kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
93
- KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd);
94
+ KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
95
kvm_arm_register_device(&s->iomem_redist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
96
- KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd);
97
+ KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
98
99
if (kvm_has_gsi_routing()) {
100
/* set up irq routing */
101
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
102
index XXXXXXX..XXXXXXX 100644
103
--- a/target/arm/kvm.c
104
+++ b/target/arm/kvm.c
105
@@ -XXX,XX +XXX,XX @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
106
* We use a MemoryListener to track mapping and unmapping of
107
* the regions during board creation, so the board models don't
108
* need to do anything special for the KVM case.
109
+ *
110
+ * Sometimes the address must be OR'ed with some other fields
111
+ * (for example for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION).
112
+ * @kda_addr_ormask aims at storing the value of those fields.
113
*/
114
typedef struct KVMDevice {
115
struct kvm_arm_device_addr kda;
116
struct kvm_device_attr kdattr;
117
+ uint64_t kda_addr_ormask;
118
MemoryRegion *mr;
119
QSLIST_ENTRY(KVMDevice) entries;
120
int dev_fd;
121
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_set_device_addr(KVMDevice *kd)
122
*/
123
if (kd->dev_fd >= 0) {
124
uint64_t addr = kd->kda.addr;
125
+
126
+ addr |= kd->kda_addr_ormask;
127
attr->addr = (uintptr_t)&addr;
128
ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
129
} else {
130
@@ -XXX,XX +XXX,XX @@ static Notifier notify = {
131
};
132
133
void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
134
- uint64_t attr, int dev_fd)
135
+ uint64_t attr, int dev_fd, uint64_t addr_ormask)
136
{
137
KVMDevice *kd;
138
139
@@ -XXX,XX +XXX,XX @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
140
kd->kdattr.group = group;
141
kd->kdattr.attr = attr;
142
kd->dev_fd = dev_fd;
143
+ kd->kda_addr_ormask = addr_ormask;
144
QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
145
memory_region_ref(kd->mr);
146
}
147
--
148
2.17.1
149
150
diff view generated by jsdifflib
[PULL 01/11] target/arm: Add raw_writes ops for register whose write induce TLB maintenance
[Qemu-devel] [PULL 06/28] hw/intc/arm_gicv3: Introduce redist-region-count array property
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Eric Auger <eric.auger@redhat.com>
2
2
3
Some registers whose 'cooked' writefns induce TLB maintenance do
3
To prepare for multiple redistributor regions, we introduce
4
not have raw_writefn ops defined. If only the writefn ops is set
4
an array of uint32_t properties that stores the redistributor
5
(ie. no raw_writefn is provided), it is assumed the cooked also
5
count of each redistributor region.
6
work as the raw one. For those registers it is not obvious the
6
7
tlb_flush works on KVM mode so better/safer setting the raw write.
7
Non accelerated VGICv3 only supports a single redistributor region.
8
The capacity of all redist regions is checked against the number of
9
vcpus.
10
11
Machvirt is updated to set those properties, ie. a single
12
redistributor region with count set to the number of vcpus
13
capped by 123.
8
14
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
15
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Jones <drjones@redhat.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 1529072910-16156-4-git-send-email-eric.auger@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
19
---
14
target/arm/helper.c | 23 +++++++++++++----------
20
include/hw/intc/arm_gicv3_common.h | 8 +++++--
15
1 file changed, 13 insertions(+), 10 deletions(-)
21
hw/arm/virt.c | 11 ++++++++-
16
22
hw/intc/arm_gicv3.c | 12 +++++++++-
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
hw/intc/arm_gicv3_common.c | 38 ++++++++++++++++++++++++++----
18
index XXXXXXX..XXXXXXX 100644
24
hw/intc/arm_gicv3_kvm.c | 9 +++++--
19
--- a/target/arm/helper.c
25
5 files changed, 67 insertions(+), 11 deletions(-)
20
+++ b/target/arm/helper.c
26
21
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
27
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
22
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
28
index XXXXXXX..XXXXXXX 100644
23
.access = PL1_RW, .accessfn = access_tvm_trvm,
29
--- a/include/hw/intc/arm_gicv3_common.h
24
.fgt = FGT_TTBR0_EL1,
30
+++ b/include/hw/intc/arm_gicv3_common.h
25
- .writefn = vmsa_ttbr_write, .resetvalue = 0,
31
@@ -XXX,XX +XXX,XX @@
26
+ .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
32
#define GICV3_MAXIRQ 1020
27
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
33
#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
28
offsetof(CPUARMState, cp15.ttbr0_ns) } },
34
29
{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
35
+#define GICV3_REDIST_SIZE 0x20000
30
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
36
+
31
.access = PL1_RW, .accessfn = access_tvm_trvm,
37
/* Number of SGI target-list bits */
32
.fgt = FGT_TTBR1_EL1,
38
#define GICV3_TARGETLIST_BITS 16
33
- .writefn = vmsa_ttbr_write, .resetvalue = 0,
39
34
+ .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
40
@@ -XXX,XX +XXX,XX @@ struct GICv3State {
35
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
41
/*< public >*/
36
offsetof(CPUARMState, cp15.ttbr1_ns) } },
42
37
{ .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
43
MemoryRegion iomem_dist; /* Distributor */
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
44
- MemoryRegion iomem_redist; /* Redistributors */
39
.type = ARM_CP_64BIT | ARM_CP_ALIAS,
45
+ MemoryRegion *iomem_redist; /* Redistributor Regions */
40
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
46
+ uint32_t *redist_region_count; /* redistributor count within each region */
41
offsetof(CPUARMState, cp15.ttbr0_ns) },
47
+ uint32_t nb_redist_regions; /* number of redist regions */
42
- .writefn = vmsa_ttbr_write, },
48
43
+ .writefn = vmsa_ttbr_write, .raw_writefn = raw_write },
49
uint32_t num_cpu;
44
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
50
uint32_t num_irq;
45
.access = PL1_RW, .accessfn = access_tvm_trvm,
51
@@ -XXX,XX +XXX,XX @@ typedef struct ARMGICv3CommonClass {
46
.type = ARM_CP_64BIT | ARM_CP_ALIAS,
52
} ARMGICv3CommonClass;
47
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
53
48
offsetof(CPUARMState, cp15.ttbr1_ns) },
54
void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
49
- .writefn = vmsa_ttbr_write, },
55
- const MemoryRegionOps *ops);
50
+ .writefn = vmsa_ttbr_write, .raw_writefn = raw_write },
56
+ const MemoryRegionOps *ops, Error **errp);
57
58
#endif
59
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/virt.c
62
+++ b/hw/arm/virt.c
63
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
64
if (!kvm_irqchip_in_kernel()) {
65
qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
66
}
67
+
68
+ if (type == 3) {
69
+ uint32_t redist0_capacity =
70
+ vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
71
+ uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
72
+
73
+ qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
74
+ qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
75
+ }
76
qdev_init_nofail(gicdev);
77
gicbusdev = SYS_BUS_DEVICE(gicdev);
78
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
79
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
80
* many redistributors we can fit into the memory map.
81
*/
82
if (vms->gic_version == 3) {
83
- virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000;
84
+ virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
85
} else {
86
virt_max_cpus = GIC_NCPU;
87
}
88
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/hw/intc/arm_gicv3.c
91
+++ b/hw/intc/arm_gicv3.c
92
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
93
return;
94
}
95
96
- gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
97
+ if (s->nb_redist_regions != 1) {
98
+ error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
99
+ s->nb_redist_regions);
100
+ return;
101
+ }
102
+
103
+ gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);
104
+ if (local_err) {
105
+ error_propagate(errp, local_err);
106
+ return;
107
+ }
108
109
gicv3_init_cpuif(s);
110
}
111
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/hw/intc/arm_gicv3_common.c
114
+++ b/hw/intc/arm_gicv3_common.c
115
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
51
};
116
};
52
117
53
static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
118
void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
54
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
119
- const MemoryRegionOps *ops)
55
.type = ARM_CP_IO,
120
+ const MemoryRegionOps *ops, Error **errp)
56
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
121
{
57
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
122
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
58
- .writefn = hcr_write },
123
+ int rdist_capacity = 0;
59
+ .writefn = hcr_write, .raw_writefn = raw_write },
124
int i;
60
{ .name = "HCR", .state = ARM_CP_STATE_AA32,
125
61
.type = ARM_CP_ALIAS | ARM_CP_IO,
126
+ for (i = 0; i < s->nb_redist_regions; i++) {
62
.cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
127
+ rdist_capacity += s->redist_region_count[i];
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
128
+ }
64
{ .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
129
+ if (rdist_capacity < s->num_cpu) {
65
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
130
+ error_setg(errp, "Capacity of the redist regions(%d) "
66
.access = PL2_RW, .writefn = vmsa_tcr_el12_write,
131
+ "is less than number of vcpus(%d)",
67
+ .raw_writefn = raw_write,
132
+ rdist_capacity, s->num_cpu);
68
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
133
+ return;
69
{ .name = "VTCR", .state = ARM_CP_STATE_AA32,
134
+ }
70
.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
135
+
71
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
136
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
72
.type = ARM_CP_64BIT | ARM_CP_ALIAS,
137
* GPIO array layout is thus:
73
.access = PL2_RW, .accessfn = access_el3_aa32ns,
138
* [0..N-1] spi
74
.fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
139
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
75
- .writefn = vttbr_write },
140
76
+ .writefn = vttbr_write, .raw_writefn = raw_write },
141
memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
77
{ .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
142
"gicv3_dist", 0x10000);
78
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
143
- memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
79
- .access = PL2_RW, .writefn = vttbr_write,
144
- "gicv3_redist", 0x20000 * s->num_cpu);
80
+ .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write,
145
-
81
.fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
146
sysbus_init_mmio(sbd, &s->iomem_dist);
82
{ .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
147
- sysbus_init_mmio(sbd, &s->iomem_redist);
83
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
148
+
84
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
149
+ s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
85
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
150
+ for (i = 0; i < s->nb_redist_regions; i++) {
86
{ .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
151
+ char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
87
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
152
+
88
- .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
153
+ memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
89
+ .access = PL2_RW, .resetvalue = 0,
154
+ ops ? &ops[1] : NULL, s, name,
90
+ .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write,
155
+ s->redist_region_count[i] * GICV3_REDIST_SIZE);
91
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
156
+ sysbus_init_mmio(sbd, &s->iomem_redist[i]);
92
{ .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
157
+ g_free(name);
93
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
158
+ }
94
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
159
}
95
{ .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
160
96
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
161
static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
97
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
162
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
98
- .resetfn = scr_reset, .writefn = scr_write },
163
}
99
+ .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write },
164
}
100
{ .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
165
101
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
166
+static void arm_gicv3_finalize(Object *obj)
102
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
167
+{
103
.fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
168
+ GICv3State *s = ARM_GICV3_COMMON(obj);
104
- .writefn = scr_write },
169
+
105
+ .writefn = scr_write, .raw_writefn = raw_write },
170
+ g_free(s->redist_region_count);
106
{ .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
171
+}
107
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
172
+
108
.access = PL3_RW, .resetvalue = 0,
173
static void arm_gicv3_common_reset(DeviceState *dev)
109
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
174
{
110
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
175
GICv3State *s = ARM_GICV3_COMMON(dev);
111
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
176
@@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = {
112
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
177
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
113
+ .raw_writefn = raw_write,
178
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
114
.fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
179
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
115
#ifndef CONFIG_USER_ONLY
180
+ DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
116
{ .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
181
+ redist_region_count, qdev_prop_uint32, uint32_t),
182
DEFINE_PROP_END_OF_LIST(),
183
};
184
185
@@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_gicv3_common_type = {
186
.instance_size = sizeof(GICv3State),
187
.class_size = sizeof(ARMGICv3CommonClass),
188
.class_init = arm_gicv3_common_class_init,
189
+ .instance_finalize = arm_gicv3_finalize,
190
.abstract = true,
191
.interfaces = (InterfaceInfo []) {
192
{ TYPE_ARM_LINUX_BOOT_IF },
193
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
194
index XXXXXXX..XXXXXXX 100644
195
--- a/hw/intc/arm_gicv3_kvm.c
196
+++ b/hw/intc/arm_gicv3_kvm.c
197
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
198
return;
199
}
200
201
- gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
202
+ gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);
203
+ if (local_err) {
204
+ error_propagate(errp, local_err);
205
+ return;
206
+ }
207
208
for (i = 0; i < s->num_cpu; i++) {
209
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
210
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
211
212
kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
213
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
214
- kvm_arm_register_device(&s->iomem_redist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
215
+ kvm_arm_register_device(&s->iomem_redist[0], -1,
216
+ KVM_DEV_ARM_VGIC_GRP_ADDR,
217
KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
218
219
if (kvm_has_gsi_routing()) {
117
--
220
--
118
2.34.1
221
2.17.1
222
223
diff view generated by jsdifflib
[PULL 06/11] target/arm: Handle IC IVAU to improve compatibility with JITs
[Qemu-devel] [PULL 07/28] hw/intc/arm_gicv3_kvm: Get prepared to handle multiple redist regions
1
From: John Högberg <john.hogberg@ericsson.com>
1
From: Eric Auger <eric.auger@redhat.com>
2
2
3
Unlike architectures with precise self-modifying code semantics
3
Let's check if KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION is supported.
4
(e.g. x86) ARM processors do not maintain coherency for instruction
4
If not, we check the number of redist region is equal to 1 and use the
5
execution and memory, requiring an instruction synchronization
5
legacy KVM_VGIC_V3_ADDR_TYPE_REDIST attribute. Otherwise we use
6
barrier on every core that will execute the new code, and on many
6
the new attribute and allow to register multiple regions to the
7
models also the explicit use of cache management instructions.
7
KVM device.
8
8
9
While this is required to make JITs work on actual hardware, QEMU
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
has gotten away with not handling this since it does not emulate
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
caches, and unconditionally invalidates code whenever the softmmu
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
or the user-mode page protection logic detects that code has been
12
Message-id: 1529072910-16156-5-git-send-email-eric.auger@redhat.com
13
modified.
14
15
Unfortunately the latter does not work in the face of dual-mapped
16
code (a common W^X workaround), where one page is executable and
17
the other is writable: user-mode has no way to connect one with the
18
other as that is only known to the kernel and the emulated
19
application.
20
21
This commit works around the issue by telling software that
22
instruction cache invalidation is required by clearing the
23
CPR_EL0.DIC flag (regardless of whether the emulated processor
24
needs it), and then invalidating code in IC IVAU instructions.
25
26
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034
27
28
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
29
Signed-off-by: John Högberg <john.hogberg@ericsson.com>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht
32
[PMM: removed unnecessary AArch64 feature check; moved
33
"clear CTR_EL1.DIC" code up a bit so it's not in the middle
34
of the vfp/neon related tests]
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
---
14
---
37
target/arm/cpu.c | 11 +++++++++++
15
hw/intc/arm_gicv3_kvm.c | 37 ++++++++++++++++++++++++++++++++++---
38
target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++---
16
1 file changed, 34 insertions(+), 3 deletions(-)
39
2 files changed, 55 insertions(+), 3 deletions(-)
40
17
41
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
42
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/cpu.c
20
--- a/hw/intc/arm_gicv3_kvm.c
44
+++ b/target/arm/cpu.c
21
+++ b/hw/intc/arm_gicv3_kvm.c
45
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
22
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
23
{
24
GICv3State *s = KVM_ARM_GICV3(dev);
25
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
26
+ bool multiple_redist_region_allowed;
27
Error *local_err = NULL;
28
int i;
29
30
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
46
return;
31
return;
47
}
32
}
48
33
49
+#ifdef CONFIG_USER_ONLY
34
+ multiple_redist_region_allowed =
50
+ /*
35
+ kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
51
+ * User mode relies on IC IVAU instructions to catch modification of
36
+ KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION);
52
+ * dual-mapped code.
53
+ *
54
+ * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
55
+ * IC IVAU even if the emulated processor does not normally require it.
56
+ */
57
+ cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
58
+#endif
59
+
37
+
60
if (arm_feature(env, ARM_FEATURE_AARCH64) &&
38
+ if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) {
61
cpu->has_vfp != cpu->has_neon) {
39
+ error_setg(errp, "Multiple VGICv3 redistributor regions are not "
62
/*
40
+ "supported by this host kernel");
63
diff --git a/target/arm/helper.c b/target/arm/helper.c
41
+ error_append_hint(errp, "A maximum of %d VCPUs can be used",
64
index XXXXXXX..XXXXXXX 100644
42
+ s->redist_region_count[0]);
65
--- a/target/arm/helper.c
43
+ return;
66
+++ b/target/arm/helper.c
44
+ }
67
@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
68
}
69
}
70
71
+#ifdef CONFIG_USER_ONLY
72
+/*
73
+ * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
74
+ * code to get around W^X restrictions, where one region is writable and the
75
+ * other is executable.
76
+ *
77
+ * Since the executable region is never written to we cannot detect code
78
+ * changes when running in user mode, and rely on the emulated JIT telling us
79
+ * that the code has changed by executing this instruction.
80
+ */
81
+static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri,
82
+ uint64_t value)
83
+{
84
+ uint64_t icache_line_mask, start_address, end_address;
85
+ const ARMCPU *cpu;
86
+
45
+
87
+ cpu = env_archcpu(env);
46
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
47
0, &s->num_irq, true, &error_abort);
48
49
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
50
51
kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
52
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
53
- kvm_arm_register_device(&s->iomem_redist[0], -1,
54
- KVM_DEV_ARM_VGIC_GRP_ADDR,
55
- KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
88
+
56
+
89
+ icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1;
57
+ if (!multiple_redist_region_allowed) {
90
+ start_address = value & ~icache_line_mask;
58
+ kvm_arm_register_device(&s->iomem_redist[0], -1,
91
+ end_address = value | icache_line_mask;
59
+ KVM_DEV_ARM_VGIC_GRP_ADDR,
60
+ KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
61
+ } else {
62
+ /* we register regions in reverse order as "devices" are inserted at
63
+ * the head of a QSLIST and the list is then popped from the head
64
+ * onwards by kvm_arm_machine_init_done()
65
+ */
66
+ for (i = s->nb_redist_regions - 1; i >= 0; i--) {
67
+ /* Address mask made of the rdist region index and count */
68
+ uint64_t addr_ormask =
69
+ i | ((uint64_t)s->redist_region_count[i] << 52);
92
+
70
+
93
+ mmap_lock();
71
+ kvm_arm_register_device(&s->iomem_redist[i], -1,
94
+
72
+ KVM_DEV_ARM_VGIC_GRP_ADDR,
95
+ tb_invalidate_phys_range(start_address, end_address);
73
+ KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,
96
+
74
+ s->dev_fd, addr_ormask);
97
+ mmap_unlock();
75
+ }
98
+}
76
+ }
99
+#endif
77
100
+
78
if (kvm_has_gsi_routing()) {
101
static const ARMCPRegInfo v8_cp_reginfo[] = {
79
/* set up irq routing */
102
/*
103
* Minimal set of EL0-visible registers. This will need to be expanded
104
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
105
{ .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
106
.opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
107
.access = PL1_R, .type = ARM_CP_CURRENTEL },
108
- /* Cache ops: all NOPs since we don't emulate caches */
109
+ /*
110
+ * Instruction cache ops. All of these except `IC IVAU` NOP because we
111
+ * don't emulate caches.
112
+ */
113
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
114
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
115
.access = PL1_W, .type = ARM_CP_NOP,
116
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
117
.accessfn = access_tocu },
118
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
119
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
120
- .access = PL0_W, .type = ARM_CP_NOP,
121
+ .access = PL0_W,
122
.fgt = FGT_ICIVAU,
123
- .accessfn = access_tocu },
124
+ .accessfn = access_tocu,
125
+#ifdef CONFIG_USER_ONLY
126
+ .type = ARM_CP_NO_RAW,
127
+ .writefn = ic_ivau_write
128
+#else
129
+ .type = ARM_CP_NOP
130
+#endif
131
+ },
132
+ /* Cache ops: all NOPs since we don't emulate caches */
133
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
134
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
135
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
136
--
80
--
137
2.34.1
81
2.17.1
138
82
139
83
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 08/28] hw/arm/virt: GICv3 DT node with one or two redistributor regions
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
This patch allows the creation of a GICv3 node with 1 or 2
4
redistributor regions depending on the number of smu_cpus.
5
The second redistributor region is located just after the
6
existing RAM region, at 256GB and contains up to up to 512 vcpus.
7
8
Please refer to kernel documentation for further node details:
9
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
10
11
Signed-off-by: Eric Auger <eric.auger@redhat.com>
12
Reviewed-by: Andrew Jones <drjones@redhat.com>
13
Message-id: 1529072910-16156-6-git-send-email-eric.auger@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/virt.h | 14 ++++++++++++++
17
hw/arm/virt.c | 29 ++++++++++++++++++++++++-----
18
2 files changed, 38 insertions(+), 5 deletions(-)
19
20
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/virt.h
23
+++ b/include/hw/arm/virt.h
24
@@ -XXX,XX +XXX,XX @@
25
#include "qemu/notify.h"
26
#include "hw/boards.h"
27
#include "hw/arm/arm.h"
28
+#include "sysemu/kvm.h"
29
+#include "hw/intc/arm_gicv3_common.h"
30
31
#define NUM_GICV2M_SPIS 64
32
#define NUM_VIRTIO_TRANSPORTS 32
33
@@ -XXX,XX +XXX,XX @@ enum {
34
VIRT_GIC_V2M,
35
VIRT_GIC_ITS,
36
VIRT_GIC_REDIST,
37
+ VIRT_GIC_REDIST2,
38
VIRT_SMMU,
39
VIRT_UART,
40
VIRT_MMIO,
41
@@ -XXX,XX +XXX,XX @@ typedef struct {
42
43
void virt_acpi_setup(VirtMachineState *vms);
44
45
+/* Return the number of used redistributor regions */
46
+static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
47
+{
48
+ uint32_t redist0_capacity =
49
+ vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
50
+
51
+ assert(vms->gic_version == 3);
52
+
53
+ return vms->smp_cpus > redist0_capacity ? 2 : 1;
54
+}
55
+
56
#endif /* QEMU_ARM_VIRT_H */
57
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/virt.c
60
+++ b/hw/arm/virt.c
61
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry a15memmap[] = {
62
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
63
[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
64
[VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
65
+ /* Additional 64 MB redist region (can contain up to 512 redistributors) */
66
+ [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
67
/* Second PCIe window, 512GB wide at the 512GB boundary */
68
[VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
69
};
70
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
71
qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2);
72
qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0);
73
if (vms->gic_version == 3) {
74
+ int nb_redist_regions = virt_gicv3_redist_region_count(vms);
75
+
76
qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible",
77
"arm,gic-v3");
78
- qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
79
- 2, vms->memmap[VIRT_GIC_DIST].base,
80
- 2, vms->memmap[VIRT_GIC_DIST].size,
81
- 2, vms->memmap[VIRT_GIC_REDIST].base,
82
- 2, vms->memmap[VIRT_GIC_REDIST].size);
83
+
84
+ qemu_fdt_setprop_cell(vms->fdt, "/intc",
85
+ "#redistributor-regions", nb_redist_regions);
86
+
87
+ if (nb_redist_regions == 1) {
88
+ qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
89
+ 2, vms->memmap[VIRT_GIC_DIST].base,
90
+ 2, vms->memmap[VIRT_GIC_DIST].size,
91
+ 2, vms->memmap[VIRT_GIC_REDIST].base,
92
+ 2, vms->memmap[VIRT_GIC_REDIST].size);
93
+ } else {
94
+ qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
95
+ 2, vms->memmap[VIRT_GIC_DIST].base,
96
+ 2, vms->memmap[VIRT_GIC_DIST].size,
97
+ 2, vms->memmap[VIRT_GIC_REDIST].base,
98
+ 2, vms->memmap[VIRT_GIC_REDIST].size,
99
+ 2, vms->memmap[VIRT_GIC_REDIST2].base,
100
+ 2, vms->memmap[VIRT_GIC_REDIST2].size);
101
+ }
102
+
103
if (vms->virt) {
104
qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts",
105
GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ,
106
--
107
2.17.1
108
109
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 09/28] hw/arm/virt-acpi-build: Advertise one or two GICR structures
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
Depending on the number of smp_cpus we now register one or two
4
GICR structures.
5
6
Signed-off-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 1529072910-16156-7-git-send-email-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/virt-acpi-build.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt-acpi-build.c
17
+++ b/hw/arm/virt-acpi-build.c
18
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
19
20
if (vms->gic_version == 3) {
21
AcpiMadtGenericTranslator *gic_its;
22
+ int nb_redist_regions = virt_gicv3_redist_region_count(vms);
23
AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
24
sizeof *gicr);
25
26
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
27
gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
28
gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
29
30
+ if (nb_redist_regions == 2) {
31
+ gicr = acpi_data_push(table_data, sizeof(*gicr));
32
+ gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
33
+ gicr->length = sizeof(*gicr);
34
+ gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST2].base);
35
+ gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST2].size);
36
+ }
37
+
38
if (its_class_name() && !vmc->no_its) {
39
gic_its = acpi_data_push(table_data, sizeof *gic_its);
40
gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
41
--
42
2.17.1
43
44
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 10/28] hw/arm/virt: Register two redistributor regions when necessary
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
With a VGICv3 KVM device, if the number of vcpus exceeds the
4
capacity of the legacy redistributor region (123 redistributors),
5
we now attempt to register a second redistributor region. Up to
6
512 redistributors can fit in this latter on top of the 123 allowed
7
by the legacy redistributor region.
8
9
Registering this second redistributor region is possible if the
10
host kernel supports the following VGICv3 KVM device group/attribute:
11
KVM_DEV_ARM_VGIC_GRP_ADDR/KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION.
12
13
In case the host kernel does not support the registration of several
14
redistributor regions and the requested number of vcpus exceeds the
15
capacity of the legacy redistributor region, the GICv3 device
16
initialization fails with a proper error message and qemu exits.
17
18
At the moment the max number of vcpus still is capped by the
19
virt machine class max_cpus.
20
21
Signed-off-by: Eric Auger <eric.auger@redhat.com>
22
Reviewed-by: Andrew Jones <drjones@redhat.com>
23
Message-id: 1529072910-16156-8-git-send-email-eric.auger@redhat.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
hw/arm/virt.c | 18 +++++++++++++++++-
27
1 file changed, 17 insertions(+), 1 deletion(-)
28
29
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/virt.c
32
+++ b/hw/arm/virt.c
33
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
34
SysBusDevice *gicbusdev;
35
const char *gictype;
36
int type = vms->gic_version, i;
37
+ uint32_t nb_redist_regions = 0;
38
39
gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
40
41
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
42
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
43
uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
44
45
- qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
46
+ nb_redist_regions = virt_gicv3_redist_region_count(vms);
47
+
48
+ qdev_prop_set_uint32(gicdev, "len-redist-region-count",
49
+ nb_redist_regions);
50
qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
51
+
52
+ if (nb_redist_regions == 2) {
53
+ uint32_t redist1_capacity =
54
+ vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
55
+
56
+ qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
57
+ MIN(smp_cpus - redist0_count, redist1_capacity));
58
+ }
59
}
60
qdev_init_nofail(gicdev);
61
gicbusdev = SYS_BUS_DEVICE(gicdev);
62
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
63
if (type == 3) {
64
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
65
+ if (nb_redist_regions == 2) {
66
+ sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].base);
67
+ }
68
} else {
69
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
70
}
71
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
72
*/
73
if (vms->gic_version == 3) {
74
virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
75
+ virt_max_cpus += vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
76
} else {
77
virt_max_cpus = GIC_NCPU;
78
}
79
--
80
2.17.1
81
82
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 11/28] hw/arm/virt: Add a new 256MB ECAM region
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
This patch defines a new ECAM region located after the 256GB limit.
4
5
The virt machine state is augmented with a new highmem_ecam field
6
which guards the usage of this new ECAM region instead of the legacy
7
16MB one. With the highmem ECAM region, up to 256 PCIe buses can be
8
used.
9
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
12
Reviewed-by: Andrew Jones <drjones@redhat.com>
13
Message-id: 1529072910-16156-9-git-send-email-eric.auger@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/virt.h | 4 ++++
17
hw/arm/virt-acpi-build.c | 21 +++++++++++++--------
18
hw/arm/virt.c | 12 ++++++++----
19
3 files changed, 25 insertions(+), 12 deletions(-)
20
21
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/virt.h
24
+++ b/include/hw/arm/virt.h
25
@@ -XXX,XX +XXX,XX @@ enum {
26
VIRT_PCIE_MMIO,
27
VIRT_PCIE_PIO,
28
VIRT_PCIE_ECAM,
29
+ VIRT_PCIE_ECAM_HIGH,
30
VIRT_PLATFORM_BUS,
31
VIRT_PCIE_MMIO_HIGH,
32
VIRT_GPIO,
33
@@ -XXX,XX +XXX,XX @@ typedef struct {
34
FWCfgState *fw_cfg;
35
bool secure;
36
bool highmem;
37
+ bool highmem_ecam;
38
bool its;
39
bool virt;
40
int32_t gic_version;
41
@@ -XXX,XX +XXX,XX @@ typedef struct {
42
int psci_conduit;
43
} VirtMachineState;
44
45
+#define VIRT_ECAM_ID(high) (high ? VIRT_PCIE_ECAM_HIGH : VIRT_PCIE_ECAM)
46
+
47
#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
48
#define VIRT_MACHINE(obj) \
49
OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
50
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/arm/virt-acpi-build.c
53
+++ b/hw/arm/virt-acpi-build.c
54
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_virtio(Aml *scope,
55
}
56
57
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
58
- uint32_t irq, bool use_highmem)
59
+ uint32_t irq, bool use_highmem, bool highmem_ecam)
60
{
61
+ int ecam_id = VIRT_ECAM_ID(highmem_ecam);
62
Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
63
int i, bus_no;
64
hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
65
hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
66
hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
67
hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
68
- hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
69
- hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
70
+ hwaddr base_ecam = memmap[ecam_id].base;
71
+ hwaddr size_ecam = memmap[ecam_id].size;
72
int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
73
74
Aml *dev = aml_device("%s", "PCI0");
75
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
76
aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
77
78
/* Declare the PCI Routing Table. */
79
- Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
80
+ Aml *rt_pkg = aml_varpackage(nr_pcie_buses * PCI_NUM_PINS);
81
for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
82
for (i = 0; i < PCI_NUM_PINS; i++) {
83
int gsi = (i + bus_no) % PCI_NUM_PINS;
84
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
85
Aml *dev_res0 = aml_device("%s", "RES0");
86
aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
87
crs = aml_resource_template();
88
- aml_append(crs, aml_memory32_fixed(base_ecam, size_ecam, AML_READ_WRITE));
89
+ aml_append(crs,
90
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
91
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
92
+ base_ecam + size_ecam - 1, 0x0000, size_ecam));
93
aml_append(dev_res0, aml_name_decl("_CRS", crs));
94
aml_append(dev, dev_res0);
95
aml_append(scope, dev);
96
@@ -XXX,XX +XXX,XX @@ build_mcfg(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
97
{
98
AcpiTableMcfg *mcfg;
99
const MemMapEntry *memmap = vms->memmap;
100
+ int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
101
int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
102
int mcfg_start = table_data->len;
103
104
mcfg = acpi_data_push(table_data, len);
105
- mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
106
+ mcfg->allocation[0].address = cpu_to_le64(memmap[ecam_id].base);
107
108
/* Only a single allocation so no need to play with segments */
109
mcfg->allocation[0].pci_segment = cpu_to_le16(0);
110
mcfg->allocation[0].start_bus_number = 0;
111
- mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
112
+ mcfg->allocation[0].end_bus_number = (memmap[ecam_id].size
113
/ PCIE_MMCFG_SIZE_MIN) - 1;
114
115
build_header(linker, table_data, (void *)(table_data->data + mcfg_start),
116
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
117
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
118
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
119
acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
120
- vms->highmem);
121
+ vms->highmem, vms->highmem_ecam);
122
acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
123
(irqmap[VIRT_GPIO] + ARM_SPI_BASE));
124
acpi_dsdt_add_power_button(scope);
125
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/hw/arm/virt.c
128
+++ b/hw/arm/virt.c
129
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry a15memmap[] = {
130
[VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
131
/* Additional 64 MB redist region (can contain up to 512 redistributors) */
132
[VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
133
+ [VIRT_PCIE_ECAM_HIGH] = { 0x4010000000ULL, 0x10000000 },
134
/* Second PCIe window, 512GB wide at the 512GB boundary */
135
[VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
136
};
137
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
138
hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size;
139
hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
140
hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
141
- hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base;
142
- hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size;
143
+ hwaddr base_ecam, size_ecam;
144
hwaddr base = base_mmio;
145
- int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
146
+ int nr_pcie_buses;
147
int irq = vms->irqmap[VIRT_PCIE];
148
MemoryRegion *mmio_alias;
149
MemoryRegion *mmio_reg;
150
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
151
MemoryRegion *ecam_reg;
152
DeviceState *dev;
153
char *nodename;
154
- int i;
155
+ int i, ecam_id;
156
PCIHostState *pci;
157
158
dev = qdev_create(NULL, TYPE_GPEX_HOST);
159
qdev_init_nofail(dev);
160
161
+ ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
162
+ base_ecam = vms->memmap[ecam_id].base;
163
+ size_ecam = vms->memmap[ecam_id].size;
164
+ nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
165
/* Map only the first size_ecam bytes of ECAM space */
166
ecam_alias = g_new0(MemoryRegion, 1);
167
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
168
--
169
2.17.1
170
171
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 12/28] hw/arm/virt: Add virt-3.0 machine type
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
Add virt-3.0 machine type.
4
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 1529072910-16156-10-git-send-email-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/virt.c | 15 +++++++++++++--
12
1 file changed, 13 insertions(+), 2 deletions(-)
13
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
17
+++ b/hw/arm/virt.c
18
@@ -XXX,XX +XXX,XX @@ type_init(machvirt_machine_init);
19
#define VIRT_COMPAT_2_12 \
20
HW_COMPAT_2_12
21
22
-static void virt_2_12_instance_init(Object *obj)
23
+static void virt_3_0_instance_init(Object *obj)
24
{
25
VirtMachineState *vms = VIRT_MACHINE(obj);
26
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
27
@@ -XXX,XX +XXX,XX @@ static void virt_2_12_instance_init(Object *obj)
28
vms->irqmap = a15irqmap;
29
}
30
31
+static void virt_machine_3_0_options(MachineClass *mc)
32
+{
33
+}
34
+DEFINE_VIRT_MACHINE_AS_LATEST(3, 0)
35
+
36
+static void virt_2_12_instance_init(Object *obj)
37
+{
38
+ virt_3_0_instance_init(obj);
39
+}
40
+
41
static void virt_machine_2_12_options(MachineClass *mc)
42
{
43
+ virt_machine_3_0_options(mc);
44
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12);
45
}
46
-DEFINE_VIRT_MACHINE_AS_LATEST(2, 12)
47
+DEFINE_VIRT_MACHINE(2, 12)
48
49
#define VIRT_COMPAT_2_11 \
50
HW_COMPAT_2_11
51
--
52
2.17.1
53
54
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 13/28] hw/arm/virt: Use 256MB ECAM region by default
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
With this patch, virt-3.0 machine uses a new 256MB ECAM region
4
by default instead of the legacy 16MB one, if highmem is set
5
(LPAE supported by the guest) and (!firmware_loaded || aarch64).
6
7
Indeed aarch32 mode FW may not support this high ECAM region.
8
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Message-id: 1529072910-16156-11-git-send-email-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/arm/virt.h | 1 +
16
hw/arm/virt.c | 10 ++++++++++
17
2 files changed, 11 insertions(+)
18
19
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/virt.h
22
+++ b/include/hw/arm/virt.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
bool no_pmu;
25
bool claim_edge_triggered_timers;
26
bool smbios_old_sys_ver;
27
+ bool no_highmem_ecam;
28
} VirtMachineClass;
29
30
typedef struct {
31
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/virt.c
34
+++ b/hw/arm/virt.c
35
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
36
int n, virt_max_cpus;
37
MemoryRegion *ram = g_new(MemoryRegion, 1);
38
bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
39
+ bool aarch64 = true;
40
41
/* We can probe only here because during property set
42
* KVM is not available yet
43
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
44
numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
45
&error_fatal);
46
47
+ aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
48
+
49
if (!vms->secure) {
50
object_property_set_bool(cpuobj, false, "has_el3", NULL);
51
}
52
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
53
create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
54
}
55
56
+ vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
57
+
58
create_rtc(vms, pic);
59
60
create_pcie(vms, pic);
61
@@ -XXX,XX +XXX,XX @@ static void virt_3_0_instance_init(Object *obj)
62
"Set GIC version. "
63
"Valid values are 2, 3 and host", NULL);
64
65
+ vms->highmem_ecam = !vmc->no_highmem_ecam;
66
+
67
if (vmc->no_its) {
68
vms->its = false;
69
} else {
70
@@ -XXX,XX +XXX,XX @@ static void virt_2_12_instance_init(Object *obj)
71
72
static void virt_machine_2_12_options(MachineClass *mc)
73
{
74
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
75
+
76
virt_machine_3_0_options(mc);
77
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12);
78
+ vmc->no_highmem_ecam = true;
79
}
80
DEFINE_VIRT_MACHINE(2, 12)
81
82
--
83
2.17.1
84
85
diff view generated by jsdifflib
[PULL 10/11] hw: arm: allwinner-sramc: Set class_size
[Qemu-devel] [PULL 14/28] hw/arm/virt: Increase max_cpus to 512
1
From: Akihiko Odaki <akihiko.odaki@daynix.com>
1
From: Eric Auger <eric.auger@redhat.com>
2
2
3
AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
3
virt 3.0 now allows up to 512 vcpus whereas for earlier machine
4
advertised accordingly.
4
types, max_cpus was set to 255 and any attempt to start the
5
machine with vcpus > 255 was rejected at a very early stage,
6
in vl.c/main level.
5
7
6
Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for R40")
8
512 is the max supported by KVM. Anyway the actual vcpu count
7
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
9
that can be achieved depends on other parameters such as the
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
acceleration mode, the vgic version, the host kernel version.
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Those are discovered later on.
10
Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com
12
13
Signed-off-by: Eric Auger <eric.auger@redhat.com>
14
Reviewed-by: Andrew Jones <drjones@redhat.com>
15
Message-id: 1529072910-16156-12-git-send-email-eric.auger@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
17
---
13
hw/misc/allwinner-sramc.c | 1 +
18
hw/arm/virt.c | 7 ++++---
14
1 file changed, 1 insertion(+)
19
1 file changed, 4 insertions(+), 3 deletions(-)
15
20
16
diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c
21
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/misc/allwinner-sramc.c
23
--- a/hw/arm/virt.c
19
+++ b/hw/misc/allwinner-sramc.c
24
+++ b/hw/arm/virt.c
20
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_sramc_info = {
25
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
21
.parent = TYPE_SYS_BUS_DEVICE,
26
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
22
.instance_init = allwinner_sramc_init,
27
23
.instance_size = sizeof(AwSRAMCState),
28
mc->init = machvirt_init;
24
+ .class_size = sizeof(AwSRAMCClass),
29
- /* Start max_cpus at the maximum QEMU supports. We'll further restrict
25
.class_init = allwinner_sramc_class_init,
30
- * it later in machvirt_init, where we have more information about the
26
};
31
+ /* Start with max_cpus set to 512, which is the maximum supported by KVM.
32
+ * The value may be reduced later when we have more information about the
33
* configuration of the particular instance.
34
*/
35
- mc->max_cpus = 255;
36
+ mc->max_cpus = 512;
37
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
38
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
39
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
40
@@ -XXX,XX +XXX,XX @@ static void virt_machine_2_12_options(MachineClass *mc)
41
virt_machine_3_0_options(mc);
42
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12);
43
vmc->no_highmem_ecam = true;
44
+ mc->max_cpus = 255;
45
}
46
DEFINE_VIRT_MACHINE(2, 12)
27
47
28
--
48
--
29
2.34.1
49
2.17.1
30
50
31
51
diff view generated by jsdifflib
[PULL 04/11] target/arm: Dump ZA[] when active
[Qemu-devel] [PULL 15/28] target-arm: Add the Cortex-R5F
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
2
3
Always print each matrix row whole, one per line, so that we
3
Add the Cortex-R5F with the optional FPU enabled.
4
get the entire matrix in the proper shape.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
7
Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Message-id: 20180529124707.3025-2-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/cpu.c | 18 ++++++++++++++++++
13
target/arm/cpu.c | 9 +++++++++
12
1 file changed, 18 insertions(+)
14
1 file changed, 9 insertions(+)
13
15
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
18
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
20
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
19
i, q[1], q[0], (i & 1 ? "\n" : " "));
21
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
20
}
22
}
21
}
23
24
+static void cortex_r5f_initfn(Object *obj)
25
+{
26
+ ARMCPU *cpu = ARM_CPU(obj);
22
+
27
+
23
+ if (cpu_isar_feature(aa64_sme, cpu) &&
28
+ cortex_r5_initfn(obj);
24
+ FIELD_EX64(env->svcr, SVCR, ZA) &&
29
+ set_feature(&cpu->env, ARM_FEATURE_VFP3);
25
+ sme_exception_el(env, el) == 0) {
30
+}
26
+ int zcr_len = sve_vqm1_for_el_sm(env, el, true);
27
+ int svl = (zcr_len + 1) * 16;
28
+ int svl_lg10 = svl < 100 ? 2 : 3;
29
+
31
+
30
+ for (i = 0; i < svl; i++) {
32
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
31
+ qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
33
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
32
+ for (j = zcr_len; j >= 0; --j) {
34
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
35
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
34
+ env->zarray[i].d[2 * j + 1],
36
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
35
+ env->zarray[i].d[2 * j],
37
.class_init = arm_v7m_class_init },
36
+ j ? ':' : '\n');
38
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
37
+ }
39
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
38
+ }
40
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
39
+ }
41
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
40
}
42
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
41
42
#else
43
--
43
--
44
2.34.1
44
2.17.1
45
46
diff view generated by jsdifflib
[PULL 02/11] hw/arm/sbsa-ref: use XHCI to replace EHCI
[Qemu-devel] [PULL 16/28] xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F
1
From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
2
3
The current sbsa-ref cannot use EHCI controller which is only
3
The ZynqMP has Cortex-R5Fs with the optional FPU enabled.
4
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
5
Hence, this uses XHCI to provide a usb controller with 64-bit
6
DMA capablity instead of EHCI.
7
4
8
We bump the platform version to 0.3 with this change. Although the
5
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
9
hardware at the USB controller address changes, the firmware and
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Linux can both cope with this -- on an older non-XHCI-aware
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
firmware/kernel setup the probe routine simply fails and the guest
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
proceeds without any USB. (This isn't a loss of functionality,
9
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
because the old USB controller never worked in the first place.) So
10
Message-id: 20180529124707.3025-3-edgar.iglesias@gmail.com
14
we can call this a backwards-compatible change and only bump the
15
minor version.
16
17
Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
18
Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn
19
[PMM: tweaked commit message; add line to docs about what
20
changes in platform version 0.3]
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
12
---
24
docs/system/arm/sbsa.rst | 5 ++++-
13
hw/arm/xlnx-zcu102.c | 2 +-
25
hw/arm/sbsa-ref.c | 23 +++++++++++++----------
14
hw/arm/xlnx-zynqmp.c | 2 +-
26
hw/arm/Kconfig | 2 +-
15
2 files changed, 2 insertions(+), 2 deletions(-)
27
3 files changed, 18 insertions(+), 12 deletions(-)
28
16
29
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
17
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
30
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
31
--- a/docs/system/arm/sbsa.rst
19
--- a/hw/arm/xlnx-zcu102.c
32
+++ b/docs/system/arm/sbsa.rst
20
+++ b/hw/arm/xlnx-zcu102.c
33
@@ -XXX,XX +XXX,XX @@ The ``sbsa-ref`` board supports:
21
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
34
- A configurable number of AArch64 CPUs
22
{
35
- GIC version 3
23
MachineClass *mc = MACHINE_CLASS(oc);
36
- System bus AHCI controller
24
37
- - System bus EHCI controller
25
- mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5s based on " \
38
+ - System bus XHCI controller
26
+ mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
39
- CDROM and hard disc on AHCI bus
27
"the value of smp";
40
- E1000E ethernet card on PCIe bus
28
mc->init = xlnx_zcu102_init;
41
- Bochs display adapter on PCIe bus
29
mc->block_default_type = IF_IDE;
42
@@ -XXX,XX +XXX,XX @@ Platform version changes:
30
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
43
44
0.2
45
GIC ITS information is present in devicetree.
46
+
47
+0.3
48
+ The USB controller is an XHCI device, not EHCI
49
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
50
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/arm/sbsa-ref.c
32
--- a/hw/arm/xlnx-zynqmp.c
52
+++ b/hw/arm/sbsa-ref.c
33
+++ b/hw/arm/xlnx-zynqmp.c
53
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
54
#include "hw/pci-host/gpex.h"
35
char *name;
55
#include "hw/qdev-properties.h"
36
56
#include "hw/usb.h"
37
object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
57
+#include "hw/usb/xhci.h"
38
- "cortex-r5-" TYPE_ARM_CPU);
58
#include "hw/char/pl011.h"
39
+ "cortex-r5f-" TYPE_ARM_CPU);
59
#include "hw/watchdog/sbsa_gwdt.h"
40
object_property_add_child(OBJECT(s), "rpu-cpu[*]",
60
#include "net/net.h"
41
OBJECT(&s->rpu_cpu[i]), &error_abort);
61
@@ -XXX,XX +XXX,XX @@ enum {
62
SBSA_SECURE_UART_MM,
63
SBSA_SECURE_MEM,
64
SBSA_AHCI,
65
- SBSA_EHCI,
66
+ SBSA_XHCI,
67
};
68
69
struct SBSAMachineState {
70
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
71
[SBSA_SMMU] = { 0x60050000, 0x00020000 },
72
/* Space here reserved for more SMMUs */
73
[SBSA_AHCI] = { 0x60100000, 0x00010000 },
74
- [SBSA_EHCI] = { 0x60110000, 0x00010000 },
75
+ [SBSA_XHCI] = { 0x60110000, 0x00010000 },
76
/* Space here reserved for other devices */
77
[SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
78
/* 32-bit address PCIE MMIO space */
79
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
80
[SBSA_SECURE_UART] = 8,
81
[SBSA_SECURE_UART_MM] = 9,
82
[SBSA_AHCI] = 10,
83
- [SBSA_EHCI] = 11,
84
+ [SBSA_XHCI] = 11,
85
[SBSA_SMMU] = 12, /* ... to 15 */
86
[SBSA_GWDT_WS0] = 16,
87
};
88
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
89
* fw compatibility.
90
*/
91
qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
92
- qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2);
93
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3);
94
95
if (ms->numa_state->have_numa_distance) {
96
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
97
@@ -XXX,XX +XXX,XX @@ static void create_ahci(const SBSAMachineState *sms)
98
}
99
}
100
101
-static void create_ehci(const SBSAMachineState *sms)
102
+static void create_xhci(const SBSAMachineState *sms)
103
{
104
- hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
105
- int irq = sbsa_ref_irqmap[SBSA_EHCI];
106
+ hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
107
+ int irq = sbsa_ref_irqmap[SBSA_XHCI];
108
+ DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
109
110
- sysbus_create_simple("platform-ehci-usb", base,
111
- qdev_get_gpio_in(sms->gic, irq));
112
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
113
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
114
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
115
}
116
117
static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
118
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
119
120
create_ahci(sms);
121
122
- create_ehci(sms);
123
+ create_xhci(sms);
124
125
create_pcie(sms);
126
127
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
128
index XXXXXXX..XXXXXXX 100644
129
--- a/hw/arm/Kconfig
130
+++ b/hw/arm/Kconfig
131
@@ -XXX,XX +XXX,XX @@ config SBSA_REF
132
select PL011 # UART
133
select PL031 # RTC
134
select PL061 # GPIO
135
- select USB_EHCI_SYSBUS
136
+ select USB_XHCI_SYSBUS
137
select WDT_SBSA
138
select BOCHS_DISPLAY
139
42
140
--
43
--
141
2.34.1
44
2.17.1
45
46
diff view generated by jsdifflib
[PULL 05/11] target/arm: Fix SME full tile indexing
[Qemu-devel] [PULL 17/28] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the Arm TrustZone Memory Protection Controller, which sits
2
in front of RAM and allows secure software to configure it to either
3
pass through or reject transactions.
2
4
3
For the outer product set of insns, which take an entire matrix
5
We implement the MPC as a QEMU IOMMU, which will direct transactions
4
tile as output, the argument is not a combined tile+column.
6
either through to the devices and memory behind it or to a special
5
Therefore using get_tile_rowcol was incorrect, as we extracted
7
"never works" AddressSpace if they are blocked.
6
the tile number from itself.
7
8
8
The test case relies only on assembler support for SME, since
9
This initial commit implements the skeleton of the device:
9
no release of GCC recognizes -march=armv9-a+sme yet.
10
* it always permits accesses
11
* it doesn't implement most of the registers
12
* it doesn't implement the interrupt or other behaviour
13
for blocked transactions
10
14
11
Cc: qemu-stable@nongnu.org
12
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Message-id: 20180620132032.28865-2-peter.maydell@linaro.org
17
---
19
---
18
target/arm/tcg/translate-sme.c | 24 ++++++---
20
hw/misc/Makefile.objs | 1 +
19
tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++++++++++++++++
21
include/hw/misc/tz-mpc.h | 70 ++++++
20
tests/tcg/aarch64/Makefile.target | 10 ++--
22
hw/misc/tz-mpc.c | 399 ++++++++++++++++++++++++++++++++
21
3 files changed, 108 insertions(+), 9 deletions(-)
23
MAINTAINERS | 2 +
22
create mode 100644 tests/tcg/aarch64/sme-outprod1.c
24
default-configs/arm-softmmu.mak | 1 +
25
hw/misc/trace-events | 7 +
26
6 files changed, 480 insertions(+)
27
create mode 100644 include/hw/misc/tz-mpc.h
28
create mode 100644 hw/misc/tz-mpc.c
23
29
24
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
30
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
25
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/tcg/translate-sme.c
32
--- a/hw/misc/Makefile.objs
27
+++ b/target/arm/tcg/translate-sme.c
33
+++ b/hw/misc/Makefile.objs
28
@@ -XXX,XX +XXX,XX @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
34
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o
29
return addr;
35
obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o
30
}
36
obj-$(CONFIG_MPS2_SCC) += mps2-scc.o
31
37
32
+/*
38
+obj-$(CONFIG_TZ_MPC) += tz-mpc.o
33
+ * Resolve tile.size[0] to a host pointer.
39
obj-$(CONFIG_TZ_PPC) += tz-ppc.o
34
+ * Used by e.g. outer product insns where we require the entire tile.
40
obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
35
+ */
41
36
+static TCGv_ptr get_tile(DisasContext *s, int esz, int tile)
42
diff --git a/include/hw/misc/tz-mpc.h b/include/hw/misc/tz-mpc.h
37
+{
38
+ TCGv_ptr addr = tcg_temp_new_ptr();
39
+ int offset;
40
+
41
+ offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray);
42
+
43
+ tcg_gen_addi_ptr(addr, cpu_env, offset);
44
+ return addr;
45
+}
46
+
47
static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
48
{
49
if (!dc_isar_feature(aa64_sme, s)) {
50
@@ -XXX,XX +XXX,XX @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
51
return true;
52
}
53
54
- /* Sum XZR+zad to find ZAd. */
55
- za = get_tile_rowcol(s, esz, 31, a->zad, false);
56
+ za = get_tile(s, esz, a->zad);
57
zn = vec_full_reg_ptr(s, a->zn);
58
pn = pred_full_reg_ptr(s, a->pn);
59
pm = pred_full_reg_ptr(s, a->pm);
60
@@ -XXX,XX +XXX,XX @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
61
return true;
62
}
63
64
- /* Sum XZR+zad to find ZAd. */
65
- za = get_tile_rowcol(s, esz, 31, a->zad, false);
66
+ za = get_tile(s, esz, a->zad);
67
zn = vec_full_reg_ptr(s, a->zn);
68
zm = vec_full_reg_ptr(s, a->zm);
69
pn = pred_full_reg_ptr(s, a->pn);
70
@@ -XXX,XX +XXX,XX @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
71
return true;
72
}
73
74
- /* Sum XZR+zad to find ZAd. */
75
- za = get_tile_rowcol(s, esz, 31, a->zad, false);
76
+ za = get_tile(s, esz, a->zad);
77
zn = vec_full_reg_ptr(s, a->zn);
78
zm = vec_full_reg_ptr(s, a->zm);
79
pn = pred_full_reg_ptr(s, a->pn);
80
diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c
81
new file mode 100644
43
new file mode 100644
82
index XXXXXXX..XXXXXXX
44
index XXXXXXX..XXXXXXX
83
--- /dev/null
45
--- /dev/null
84
+++ b/tests/tcg/aarch64/sme-outprod1.c
46
+++ b/include/hw/misc/tz-mpc.h
85
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@
86
+/*
48
+/*
87
+ * SME outer product, 1 x 1.
49
+ * ARM AHB5 TrustZone Memory Protection Controller emulation
88
+ * SPDX-License-Identifier: GPL-2.0-or-later
50
+ *
51
+ * Copyright (c) 2018 Linaro Limited
52
+ * Written by Peter Maydell
53
+ *
54
+ * This program is free software; you can redistribute it and/or modify
55
+ * it under the terms of the GNU General Public License version 2 or
56
+ * (at your option) any later version.
89
+ */
57
+ */
90
+
58
+
91
+#include <stdio.h>
59
+/* This is a model of the TrustZone memory protection controller (MPC).
92
+
60
+ * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
93
+extern void foo(float *dst);
61
+ * (DDI 0571G):
94
+
62
+ * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
95
+asm(
63
+ *
96
+"    .arch_extension sme\n"
64
+ * The MPC sits in front of memory and allows secure software to
97
+"    .type foo, @function\n"
65
+ * configure it to either pass through or reject transactions.
98
+"foo:\n"
66
+ * Rejected transactions may be configured to either be aborted, or to
99
+"    stp x29, x30, [sp, -80]!\n"
67
+ * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
100
+"    mov x29, sp\n"
68
+ *
101
+"    stp d8, d9, [sp, 16]\n"
69
+ * The MPC has a register interface which the guest uses to configure it.
102
+"    stp d10, d11, [sp, 32]\n"
70
+ *
103
+"    stp d12, d13, [sp, 48]\n"
71
+ * QEMU interface:
104
+"    stp d14, d15, [sp, 64]\n"
72
+ * + sysbus MMIO region 0: MemoryRegion for the MPC's config registers
105
+"    smstart\n"
73
+ * + sysbus MMIO region 1: MemoryRegion for the upstream end of the MPC
106
+"    ptrue p0.s, vl4\n"
74
+ * + Property "downstream": MemoryRegion defining the downstream memory
107
+"    fmov z0.s, #1.0\n"
75
+ * + Named GPIO output "irq": set for a transaction-failed interrupt
76
+ */
77
+
78
+#ifndef TZ_MPC_H
79
+#define TZ_MPC_H
80
+
81
+#include "hw/sysbus.h"
82
+
83
+#define TYPE_TZ_MPC "tz-mpc"
84
+#define TZ_MPC(obj) OBJECT_CHECK(TZMPC, (obj), TYPE_TZ_MPC)
85
+
86
+#define TZ_NUM_PORTS 16
87
+
88
+#define TYPE_TZ_MPC_IOMMU_MEMORY_REGION "tz-mpc-iommu-memory-region"
89
+
90
+typedef struct TZMPC TZMPC;
91
+
92
+struct TZMPC {
93
+ /*< private >*/
94
+ SysBusDevice parent_obj;
95
+
96
+ /*< public >*/
97
+
98
+ qemu_irq irq;
99
+
100
+ /* Properties */
101
+ MemoryRegion *downstream;
102
+
103
+ hwaddr blocksize;
104
+ uint32_t blk_max;
105
+
106
+ /* MemoryRegions exposed to user */
107
+ MemoryRegion regmr;
108
+ IOMMUMemoryRegion upstream;
109
+
110
+ /* MemoryRegion used internally */
111
+ MemoryRegion blocked_io;
112
+
113
+ AddressSpace downstream_as;
114
+ AddressSpace blocked_io_as;
115
+};
116
+
117
+#endif
118
diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c
119
new file mode 100644
120
index XXXXXXX..XXXXXXX
121
--- /dev/null
122
+++ b/hw/misc/tz-mpc.c
123
@@ -XXX,XX +XXX,XX @@
108
+/*
124
+/*
109
+ * An outer product of a vector of 1.0 by itself should be a matrix of 1.0.
125
+ * ARM AHB5 TrustZone Memory Protection Controller emulation
110
+ * Note that we are using tile 1 here (za1.s) rather than tile 0.
126
+ *
127
+ * Copyright (c) 2018 Linaro Limited
128
+ * Written by Peter Maydell
129
+ *
130
+ * This program is free software; you can redistribute it and/or modify
131
+ * it under the terms of the GNU General Public License version 2 or
132
+ * (at your option) any later version.
111
+ */
133
+ */
112
+"    zero {za}\n"
134
+
113
+"    fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n"
135
+#include "qemu/osdep.h"
114
+/*
136
+#include "qemu/log.h"
115
+ * Read the first 4x4 sub-matrix of elements from tile 1:
137
+#include "qapi/error.h"
116
+ * Note that za1h should be interchangable here.
138
+#include "trace.h"
139
+#include "hw/sysbus.h"
140
+#include "hw/registerfields.h"
141
+#include "hw/misc/tz-mpc.h"
142
+
143
+/* Our IOMMU has two IOMMU indexes, one for secure transactions and one for
144
+ * non-secure transactions.
117
+ */
145
+ */
118
+"    mov w12, #0\n"
146
+enum {
119
+"    mova z0.s, p0/m, za1v.s[w12, #0]\n"
147
+ IOMMU_IDX_S,
120
+"    mova z1.s, p0/m, za1v.s[w12, #1]\n"
148
+ IOMMU_IDX_NS,
121
+"    mova z2.s, p0/m, za1v.s[w12, #2]\n"
149
+ IOMMU_NUM_INDEXES,
122
+"    mova z3.s, p0/m, za1v.s[w12, #3]\n"
150
+};
123
+/*
151
+
124
+ * And store them to the input pointer (dst in the C code):
152
+/* Config registers */
125
+ */
153
+REG32(CTRL, 0x00)
126
+"    st1w {z0.s}, p0, [x0]\n"
154
+REG32(BLK_MAX, 0x10)
127
+"    add x0, x0, #16\n"
155
+REG32(BLK_CFG, 0x14)
128
+"    st1w {z1.s}, p0, [x0]\n"
156
+REG32(BLK_IDX, 0x18)
129
+"    add x0, x0, #16\n"
157
+REG32(BLK_LUT, 0x1c)
130
+"    st1w {z2.s}, p0, [x0]\n"
158
+REG32(INT_STAT, 0x20)
131
+"    add x0, x0, #16\n"
159
+REG32(INT_CLEAR, 0x24)
132
+"    st1w {z3.s}, p0, [x0]\n"
160
+REG32(INT_EN, 0x28)
133
+"    smstop\n"
161
+REG32(INT_INFO1, 0x2c)
134
+"    ldp d8, d9, [sp, 16]\n"
162
+REG32(INT_INFO2, 0x30)
135
+"    ldp d10, d11, [sp, 32]\n"
163
+REG32(INT_SET, 0x34)
136
+"    ldp d12, d13, [sp, 48]\n"
164
+REG32(PIDR4, 0xfd0)
137
+"    ldp d14, d15, [sp, 64]\n"
165
+REG32(PIDR5, 0xfd4)
138
+"    ldp x29, x30, [sp], 80\n"
166
+REG32(PIDR6, 0xfd8)
139
+"    ret\n"
167
+REG32(PIDR7, 0xfdc)
140
+"    .size foo, . - foo"
168
+REG32(PIDR0, 0xfe0)
141
+);
169
+REG32(PIDR1, 0xfe4)
142
+
170
+REG32(PIDR2, 0xfe8)
143
+int main()
171
+REG32(PIDR3, 0xfec)
144
+{
172
+REG32(CIDR0, 0xff0)
145
+ float dst[16];
173
+REG32(CIDR1, 0xff4)
146
+ int i, j;
174
+REG32(CIDR2, 0xff8)
147
+
175
+REG32(CIDR3, 0xffc)
148
+ foo(dst);
176
+
149
+
177
+static const uint8_t tz_mpc_idregs[] = {
150
+ for (i = 0; i < 16; i++) {
178
+ 0x04, 0x00, 0x00, 0x00,
151
+ if (dst[i] != 1.0f) {
179
+ 0x60, 0xb8, 0x1b, 0x00,
180
+ 0x0d, 0xf0, 0x05, 0xb1,
181
+};
182
+
183
+static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr,
184
+ uint64_t *pdata,
185
+ unsigned size, MemTxAttrs attrs)
186
+{
187
+ uint64_t r;
188
+ uint32_t offset = addr & ~0x3;
189
+
190
+ if (!attrs.secure && offset < A_PIDR4) {
191
+ /* NS accesses can only see the ID registers */
192
+ qemu_log_mask(LOG_GUEST_ERROR,
193
+ "TZ MPC register read: NS access to offset 0x%x\n",
194
+ offset);
195
+ r = 0;
196
+ goto read_out;
197
+ }
198
+
199
+ switch (offset) {
200
+ case A_PIDR4:
201
+ case A_PIDR5:
202
+ case A_PIDR6:
203
+ case A_PIDR7:
204
+ case A_PIDR0:
205
+ case A_PIDR1:
206
+ case A_PIDR2:
207
+ case A_PIDR3:
208
+ case A_CIDR0:
209
+ case A_CIDR1:
210
+ case A_CIDR2:
211
+ case A_CIDR3:
212
+ r = tz_mpc_idregs[(offset - A_PIDR4) / 4];
213
+ break;
214
+ case A_INT_CLEAR:
215
+ case A_INT_SET:
216
+ qemu_log_mask(LOG_GUEST_ERROR,
217
+ "TZ MPC register read: write-only offset 0x%x\n",
218
+ offset);
219
+ r = 0;
220
+ break;
221
+ default:
222
+ qemu_log_mask(LOG_GUEST_ERROR,
223
+ "TZ MPC register read: bad offset 0x%x\n", offset);
224
+ r = 0;
225
+ break;
226
+ }
227
+
228
+ if (size != 4) {
229
+ /* None of our registers are read-sensitive (except BLK_LUT,
230
+ * which can special case the "size not 4" case), so just
231
+ * pull the right bytes out of the word read result.
232
+ */
233
+ r = extract32(r, (addr & 3) * 8, size * 8);
234
+ }
235
+
236
+read_out:
237
+ trace_tz_mpc_reg_read(addr, r, size);
238
+ *pdata = r;
239
+ return MEMTX_OK;
240
+}
241
+
242
+static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
243
+ uint64_t value,
244
+ unsigned size, MemTxAttrs attrs)
245
+{
246
+ uint32_t offset = addr & ~0x3;
247
+
248
+ trace_tz_mpc_reg_write(addr, value, size);
249
+
250
+ if (!attrs.secure && offset < A_PIDR4) {
251
+ /* NS accesses can only see the ID registers */
252
+ qemu_log_mask(LOG_GUEST_ERROR,
253
+ "TZ MPC register write: NS access to offset 0x%x\n",
254
+ offset);
255
+ return MEMTX_OK;
256
+ }
257
+
258
+ if (size != 4) {
259
+ /* Expand the byte or halfword write to a full word size.
260
+ * In most cases we can do this with zeroes; the exceptions
261
+ * are CTRL, BLK_IDX and BLK_LUT.
262
+ */
263
+ uint32_t oldval;
264
+
265
+ switch (offset) {
266
+ /* As we add support for registers which need expansions
267
+ * other than zeroes we'll fill in cases here.
268
+ */
269
+ default:
270
+ oldval = 0;
152
+ break;
271
+ break;
153
+ }
272
+ }
154
+ }
273
+ value = deposit32(oldval, (addr & 3) * 8, size * 8, value);
155
+
274
+ }
156
+ if (i == 16) {
275
+
157
+ return 0; /* success */
276
+ switch (offset) {
158
+ }
277
+ case A_PIDR4:
159
+
278
+ case A_PIDR5:
160
+ /* failure */
279
+ case A_PIDR6:
161
+ for (i = 0; i < 4; ++i) {
280
+ case A_PIDR7:
162
+ for (j = 0; j < 4; ++j) {
281
+ case A_PIDR0:
163
+ printf("%f ", (double)dst[i * 4 + j]);
282
+ case A_PIDR1:
164
+ }
283
+ case A_PIDR2:
165
+ printf("\n");
284
+ case A_PIDR3:
166
+ }
285
+ case A_CIDR0:
167
+ return 1;
286
+ case A_CIDR1:
168
+}
287
+ case A_CIDR2:
169
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
288
+ case A_CIDR3:
289
+ qemu_log_mask(LOG_GUEST_ERROR,
290
+ "TZ MPC register write: read-only offset 0x%x\n", offset);
291
+ break;
292
+ default:
293
+ qemu_log_mask(LOG_GUEST_ERROR,
294
+ "TZ MPC register write: bad offset 0x%x\n", offset);
295
+ break;
296
+ }
297
+
298
+ return MEMTX_OK;
299
+}
300
+
301
+static const MemoryRegionOps tz_mpc_reg_ops = {
302
+ .read_with_attrs = tz_mpc_reg_read,
303
+ .write_with_attrs = tz_mpc_reg_write,
304
+ .endianness = DEVICE_LITTLE_ENDIAN,
305
+ .valid.min_access_size = 1,
306
+ .valid.max_access_size = 4,
307
+ .impl.min_access_size = 1,
308
+ .impl.max_access_size = 4,
309
+};
310
+
311
+/* Accesses only reach these read and write functions if the MPC is
312
+ * blocking them; non-blocked accesses go directly to the downstream
313
+ * memory region without passing through this code.
314
+ */
315
+static MemTxResult tz_mpc_mem_blocked_read(void *opaque, hwaddr addr,
316
+ uint64_t *pdata,
317
+ unsigned size, MemTxAttrs attrs)
318
+{
319
+ trace_tz_mpc_mem_blocked_read(addr, size, attrs.secure);
320
+
321
+ *pdata = 0;
322
+ return MEMTX_OK;
323
+}
324
+
325
+static MemTxResult tz_mpc_mem_blocked_write(void *opaque, hwaddr addr,
326
+ uint64_t value,
327
+ unsigned size, MemTxAttrs attrs)
328
+{
329
+ trace_tz_mpc_mem_blocked_write(addr, value, size, attrs.secure);
330
+
331
+ return MEMTX_OK;
332
+}
333
+
334
+static const MemoryRegionOps tz_mpc_mem_blocked_ops = {
335
+ .read_with_attrs = tz_mpc_mem_blocked_read,
336
+ .write_with_attrs = tz_mpc_mem_blocked_write,
337
+ .endianness = DEVICE_LITTLE_ENDIAN,
338
+ .valid.min_access_size = 1,
339
+ .valid.max_access_size = 8,
340
+ .impl.min_access_size = 1,
341
+ .impl.max_access_size = 8,
342
+};
343
+
344
+static IOMMUTLBEntry tz_mpc_translate(IOMMUMemoryRegion *iommu,
345
+ hwaddr addr, IOMMUAccessFlags flags,
346
+ int iommu_idx)
347
+{
348
+ TZMPC *s = TZ_MPC(container_of(iommu, TZMPC, upstream));
349
+ bool ok;
350
+
351
+ IOMMUTLBEntry ret = {
352
+ .iova = addr & ~(s->blocksize - 1),
353
+ .translated_addr = addr & ~(s->blocksize - 1),
354
+ .addr_mask = s->blocksize - 1,
355
+ .perm = IOMMU_RW,
356
+ };
357
+
358
+ /* Look at the per-block configuration for this address, and
359
+ * return a TLB entry directing the transaction at either
360
+ * downstream_as or blocked_io_as, as appropriate.
361
+ * For the moment, always permit accesses.
362
+ */
363
+ ok = true;
364
+
365
+ trace_tz_mpc_translate(addr, flags,
366
+ iommu_idx == IOMMU_IDX_S ? "S" : "NS",
367
+ ok ? "pass" : "block");
368
+
369
+ ret.target_as = ok ? &s->downstream_as : &s->blocked_io_as;
370
+ return ret;
371
+}
372
+
373
+static int tz_mpc_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs)
374
+{
375
+ /* We treat unspecified attributes like secure. Transactions with
376
+ * unspecified attributes come from places like
377
+ * cpu_physical_memory_write_rom() for initial image load, and we want
378
+ * those to pass through the from-reset "everything is secure" config.
379
+ * All the real during-emulation transactions from the CPU will
380
+ * specify attributes.
381
+ */
382
+ return (attrs.unspecified || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_NS;
383
+}
384
+
385
+static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu)
386
+{
387
+ return IOMMU_NUM_INDEXES;
388
+}
389
+
390
+static void tz_mpc_reset(DeviceState *dev)
391
+{
392
+}
393
+
394
+static void tz_mpc_init(Object *obj)
395
+{
396
+ DeviceState *dev = DEVICE(obj);
397
+ TZMPC *s = TZ_MPC(obj);
398
+
399
+ qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
400
+}
401
+
402
+static void tz_mpc_realize(DeviceState *dev, Error **errp)
403
+{
404
+ Object *obj = OBJECT(dev);
405
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
406
+ TZMPC *s = TZ_MPC(dev);
407
+ uint64_t size;
408
+
409
+ /* We can't create the upstream end of the port until realize,
410
+ * as we don't know the size of the MR used as the downstream until then.
411
+ * We insist on having a downstream, to avoid complicating the code
412
+ * with handling the "don't know how big this is" case. It's easy
413
+ * enough for the user to create an unimplemented_device as downstream
414
+ * if they have nothing else to plug into this.
415
+ */
416
+ if (!s->downstream) {
417
+ error_setg(errp, "MPC 'downstream' link not set");
418
+ return;
419
+ }
420
+
421
+ size = memory_region_size(s->downstream);
422
+
423
+ memory_region_init_iommu(&s->upstream, sizeof(s->upstream),
424
+ TYPE_TZ_MPC_IOMMU_MEMORY_REGION,
425
+ obj, "tz-mpc-upstream", size);
426
+
427
+ /* In real hardware the block size is configurable. In QEMU we could
428
+ * make it configurable but will need it to be at least as big as the
429
+ * target page size so we can execute out of the resulting MRs. Guest
430
+ * software is supposed to check the block size using the BLK_CFG
431
+ * register, so make it fixed at the page size.
432
+ */
433
+ s->blocksize = memory_region_iommu_get_min_page_size(&s->upstream);
434
+ if (size % s->blocksize != 0) {
435
+ error_setg(errp,
436
+ "MPC 'downstream' size %" PRId64
437
+ " is not a multiple of %" HWADDR_PRIx " bytes",
438
+ size, s->blocksize);
439
+ object_unref(OBJECT(&s->upstream));
440
+ return;
441
+ }
442
+
443
+ /* BLK_MAX is the max value of BLK_IDX, which indexes an array of 32-bit
444
+ * words, each bit of which indicates one block.
445
+ */
446
+ s->blk_max = DIV_ROUND_UP(size / s->blocksize, 32);
447
+
448
+ memory_region_init_io(&s->regmr, obj, &tz_mpc_reg_ops,
449
+ s, "tz-mpc-regs", 0x1000);
450
+ sysbus_init_mmio(sbd, &s->regmr);
451
+
452
+ sysbus_init_mmio(sbd, MEMORY_REGION(&s->upstream));
453
+
454
+ /* This memory region is not exposed to users of this device as a
455
+ * sysbus MMIO region, but is instead used internally as something
456
+ * that our IOMMU translate function might direct accesses to.
457
+ */
458
+ memory_region_init_io(&s->blocked_io, obj, &tz_mpc_mem_blocked_ops,
459
+ s, "tz-mpc-blocked-io", size);
460
+
461
+ address_space_init(&s->downstream_as, s->downstream,
462
+ "tz-mpc-downstream");
463
+ address_space_init(&s->blocked_io_as, &s->blocked_io,
464
+ "tz-mpc-blocked-io");
465
+}
466
+
467
+static const VMStateDescription tz_mpc_vmstate = {
468
+ .name = "tz-mpc",
469
+ .version_id = 1,
470
+ .minimum_version_id = 1,
471
+ .fields = (VMStateField[]) {
472
+ VMSTATE_END_OF_LIST()
473
+ }
474
+};
475
+
476
+static Property tz_mpc_properties[] = {
477
+ DEFINE_PROP_LINK("downstream", TZMPC, downstream,
478
+ TYPE_MEMORY_REGION, MemoryRegion *),
479
+ DEFINE_PROP_END_OF_LIST(),
480
+};
481
+
482
+static void tz_mpc_class_init(ObjectClass *klass, void *data)
483
+{
484
+ DeviceClass *dc = DEVICE_CLASS(klass);
485
+
486
+ dc->realize = tz_mpc_realize;
487
+ dc->vmsd = &tz_mpc_vmstate;
488
+ dc->reset = tz_mpc_reset;
489
+ dc->props = tz_mpc_properties;
490
+}
491
+
492
+static const TypeInfo tz_mpc_info = {
493
+ .name = TYPE_TZ_MPC,
494
+ .parent = TYPE_SYS_BUS_DEVICE,
495
+ .instance_size = sizeof(TZMPC),
496
+ .instance_init = tz_mpc_init,
497
+ .class_init = tz_mpc_class_init,
498
+};
499
+
500
+static void tz_mpc_iommu_memory_region_class_init(ObjectClass *klass,
501
+ void *data)
502
+{
503
+ IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
504
+
505
+ imrc->translate = tz_mpc_translate;
506
+ imrc->attrs_to_index = tz_mpc_attrs_to_index;
507
+ imrc->num_indexes = tz_mpc_num_indexes;
508
+}
509
+
510
+static const TypeInfo tz_mpc_iommu_memory_region_info = {
511
+ .name = TYPE_TZ_MPC_IOMMU_MEMORY_REGION,
512
+ .parent = TYPE_IOMMU_MEMORY_REGION,
513
+ .class_init = tz_mpc_iommu_memory_region_class_init,
514
+};
515
+
516
+static void tz_mpc_register_types(void)
517
+{
518
+ type_register_static(&tz_mpc_info);
519
+ type_register_static(&tz_mpc_iommu_memory_region_info);
520
+}
521
+
522
+type_init(tz_mpc_register_types);
523
diff --git a/MAINTAINERS b/MAINTAINERS
170
index XXXXXXX..XXXXXXX 100644
524
index XXXXXXX..XXXXXXX 100644
171
--- a/tests/tcg/aarch64/Makefile.target
525
--- a/MAINTAINERS
172
+++ b/tests/tcg/aarch64/Makefile.target
526
+++ b/MAINTAINERS
173
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
527
@@ -XXX,XX +XXX,XX @@ F: hw/char/cmsdk-apb-uart.c
174
     $(call cc-option,-march=armv8.5-a, CROSS_CC_HAS_ARMV8_5); \
528
F: include/hw/char/cmsdk-apb-uart.h
175
     $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
529
F: hw/misc/tz-ppc.c
176
     $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
530
F: include/hw/misc/tz-ppc.h
177
-     $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
531
+F: hw/misc/tz-mpc.c
178
+     $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak
532
+F: include/hw/misc/tz-mpc.h
179
-include config-cc.mak
533
180
534
ARM cores
181
ifneq ($(CROSS_CC_HAS_ARMV8_2),)
535
M: Peter Maydell <peter.maydell@linaro.org>
182
@@ -XXX,XX +XXX,XX @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7
536
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
183
mte-%: CFLAGS += -march=armv8.5-a+memtag
537
index XXXXXXX..XXXXXXX 100644
184
endif
538
--- a/default-configs/arm-softmmu.mak
185
539
+++ b/default-configs/arm-softmmu.mak
186
+ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
540
@@ -XXX,XX +XXX,XX @@ CONFIG_CMSDK_APB_UART=y
187
+AARCH64_TESTS += sme-outprod1
541
CONFIG_MPS2_FPGAIO=y
188
+endif
542
CONFIG_MPS2_SCC=y
189
+
543
190
ifneq ($(CROSS_CC_HAS_SVE),)
544
+CONFIG_TZ_MPC=y
191
# System Registers Tests
545
CONFIG_TZ_PPC=y
192
AARCH64_TESTS += sysregs
546
CONFIG_IOTKIT=y
193
-ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
547
CONFIG_IOTKIT_SECCTL=y
194
-sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
548
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
195
+ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
549
index XXXXXXX..XXXXXXX 100644
196
+sysregs: CFLAGS+=-Wa,-march=armv9-a+sme -DHAS_ARMV9_SME
550
--- a/hw/misc/trace-events
197
else
551
+++ b/hw/misc/trace-events
198
sysregs: CFLAGS+=-march=armv8.1-a+sve
552
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
199
endif
553
mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
554
mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
555
556
+# hw/misc/tz-mpc.c
557
+tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
558
+tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
559
+tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d"
560
+tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d"
561
+tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s"
562
+
563
# hw/misc/tz-ppc.c
564
tz_ppc_reset(void) "TZ PPC: reset"
565
tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d"
200
--
566
--
201
2.34.1
567
2.17.1
568
569
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 18/28] hw/misc/tz-mpc.c: Implement registers
1
1
Implement the missing registers for the TZ MPC.
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Eric Auger <eric.auger@redhat.com>
5
Message-id: 20180620132032.28865-3-peter.maydell@linaro.org
6
---
7
include/hw/misc/tz-mpc.h | 10 +++
8
hw/misc/tz-mpc.c | 140 ++++++++++++++++++++++++++++++++++++++-
9
2 files changed, 147 insertions(+), 3 deletions(-)
10
11
diff --git a/include/hw/misc/tz-mpc.h b/include/hw/misc/tz-mpc.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/misc/tz-mpc.h
14
+++ b/include/hw/misc/tz-mpc.h
15
@@ -XXX,XX +XXX,XX @@ struct TZMPC {
16
17
/*< public >*/
18
19
+ /* State */
20
+ uint32_t ctrl;
21
+ uint32_t blk_idx;
22
+ uint32_t int_stat;
23
+ uint32_t int_en;
24
+ uint32_t int_info1;
25
+ uint32_t int_info2;
26
+
27
+ uint32_t *blk_lut;
28
+
29
qemu_irq irq;
30
31
/* Properties */
32
diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/misc/tz-mpc.c
35
+++ b/hw/misc/tz-mpc.c
36
@@ -XXX,XX +XXX,XX @@ enum {
37
38
/* Config registers */
39
REG32(CTRL, 0x00)
40
+ FIELD(CTRL, SEC_RESP, 4, 1)
41
+ FIELD(CTRL, AUTOINC, 8, 1)
42
+ FIELD(CTRL, LOCKDOWN, 31, 1)
43
REG32(BLK_MAX, 0x10)
44
REG32(BLK_CFG, 0x14)
45
REG32(BLK_IDX, 0x18)
46
REG32(BLK_LUT, 0x1c)
47
REG32(INT_STAT, 0x20)
48
+ FIELD(INT_STAT, IRQ, 0, 1)
49
REG32(INT_CLEAR, 0x24)
50
+ FIELD(INT_CLEAR, IRQ, 0, 1)
51
REG32(INT_EN, 0x28)
52
+ FIELD(INT_EN, IRQ, 0, 1)
53
REG32(INT_INFO1, 0x2c)
54
REG32(INT_INFO2, 0x30)
55
REG32(INT_SET, 0x34)
56
+ FIELD(INT_SET, IRQ, 0, 1)
57
REG32(PIDR4, 0xfd0)
58
REG32(PIDR5, 0xfd4)
59
REG32(PIDR6, 0xfd8)
60
@@ -XXX,XX +XXX,XX @@ static const uint8_t tz_mpc_idregs[] = {
61
0x0d, 0xf0, 0x05, 0xb1,
62
};
63
64
+static void tz_mpc_irq_update(TZMPC *s)
65
+{
66
+ qemu_set_irq(s->irq, s->int_stat && s->int_en);
67
+}
68
+
69
+static void tz_mpc_autoinc_idx(TZMPC *s, unsigned access_size)
70
+{
71
+ /* Auto-increment BLK_IDX if necessary */
72
+ if (access_size == 4 && (s->ctrl & R_CTRL_AUTOINC_MASK)) {
73
+ s->blk_idx++;
74
+ s->blk_idx %= s->blk_max;
75
+ }
76
+}
77
+
78
static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr,
79
uint64_t *pdata,
80
unsigned size, MemTxAttrs attrs)
81
{
82
+ TZMPC *s = TZ_MPC(opaque);
83
uint64_t r;
84
uint32_t offset = addr & ~0x3;
85
86
@@ -XXX,XX +XXX,XX @@ static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr,
87
}
88
89
switch (offset) {
90
+ case A_CTRL:
91
+ r = s->ctrl;
92
+ break;
93
+ case A_BLK_MAX:
94
+ r = s->blk_max;
95
+ break;
96
+ case A_BLK_CFG:
97
+ /* We are never in "init in progress state", so this just indicates
98
+ * the block size. s->blocksize == (1 << BLK_CFG + 5), so
99
+ * BLK_CFG == ctz32(s->blocksize) - 5
100
+ */
101
+ r = ctz32(s->blocksize) - 5;
102
+ break;
103
+ case A_BLK_IDX:
104
+ r = s->blk_idx;
105
+ break;
106
+ case A_BLK_LUT:
107
+ r = s->blk_lut[s->blk_idx];
108
+ tz_mpc_autoinc_idx(s, size);
109
+ break;
110
+ case A_INT_STAT:
111
+ r = s->int_stat;
112
+ break;
113
+ case A_INT_EN:
114
+ r = s->int_en;
115
+ break;
116
+ case A_INT_INFO1:
117
+ r = s->int_info1;
118
+ break;
119
+ case A_INT_INFO2:
120
+ r = s->int_info2;
121
+ break;
122
case A_PIDR4:
123
case A_PIDR5:
124
case A_PIDR6:
125
@@ -XXX,XX +XXX,XX @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
126
uint64_t value,
127
unsigned size, MemTxAttrs attrs)
128
{
129
+ TZMPC *s = TZ_MPC(opaque);
130
uint32_t offset = addr & ~0x3;
131
132
trace_tz_mpc_reg_write(addr, value, size);
133
@@ -XXX,XX +XXX,XX @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
134
uint32_t oldval;
135
136
switch (offset) {
137
- /* As we add support for registers which need expansions
138
- * other than zeroes we'll fill in cases here.
139
- */
140
+ case A_CTRL:
141
+ oldval = s->ctrl;
142
+ break;
143
+ case A_BLK_IDX:
144
+ oldval = s->blk_idx;
145
+ break;
146
+ case A_BLK_LUT:
147
+ oldval = s->blk_lut[s->blk_idx];
148
+ break;
149
default:
150
oldval = 0;
151
break;
152
@@ -XXX,XX +XXX,XX @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
153
value = deposit32(oldval, (addr & 3) * 8, size * 8, value);
154
}
155
156
+ if ((s->ctrl & R_CTRL_LOCKDOWN_MASK) &&
157
+ (offset == A_CTRL || offset == A_BLK_LUT || offset == A_INT_EN)) {
158
+ /* Lockdown mode makes these three registers read-only, and
159
+ * the only way out of it is to reset the device.
160
+ */
161
+ qemu_log_mask(LOG_GUEST_ERROR, "TZ MPC register write to offset 0x%x "
162
+ "while MPC is in lockdown mode\n", offset);
163
+ return MEMTX_OK;
164
+ }
165
+
166
switch (offset) {
167
+ case A_CTRL:
168
+ /* We don't implement the 'data gating' feature so all other bits
169
+ * are reserved and we make them RAZ/WI.
170
+ */
171
+ s->ctrl = value & (R_CTRL_SEC_RESP_MASK |
172
+ R_CTRL_AUTOINC_MASK |
173
+ R_CTRL_LOCKDOWN_MASK);
174
+ break;
175
+ case A_BLK_IDX:
176
+ s->blk_idx = value % s->blk_max;
177
+ break;
178
+ case A_BLK_LUT:
179
+ s->blk_lut[s->blk_idx] = value;
180
+ tz_mpc_autoinc_idx(s, size);
181
+ break;
182
+ case A_INT_CLEAR:
183
+ if (value & R_INT_CLEAR_IRQ_MASK) {
184
+ s->int_stat = 0;
185
+ tz_mpc_irq_update(s);
186
+ }
187
+ break;
188
+ case A_INT_EN:
189
+ s->int_en = value & R_INT_EN_IRQ_MASK;
190
+ tz_mpc_irq_update(s);
191
+ break;
192
+ case A_INT_SET:
193
+ if (value & R_INT_SET_IRQ_MASK) {
194
+ s->int_stat = R_INT_STAT_IRQ_MASK;
195
+ tz_mpc_irq_update(s);
196
+ }
197
+ break;
198
case A_PIDR4:
199
case A_PIDR5:
200
case A_PIDR6:
201
@@ -XXX,XX +XXX,XX @@ static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu)
202
203
static void tz_mpc_reset(DeviceState *dev)
204
{
205
+ TZMPC *s = TZ_MPC(dev);
206
+
207
+ s->ctrl = 0x00000100;
208
+ s->blk_idx = 0;
209
+ s->int_stat = 0;
210
+ s->int_en = 1;
211
+ s->int_info1 = 0;
212
+ s->int_info2 = 0;
213
+
214
+ memset(s->blk_lut, 0, s->blk_max * sizeof(uint32_t));
215
}
216
217
static void tz_mpc_init(Object *obj)
218
@@ -XXX,XX +XXX,XX @@ static void tz_mpc_realize(DeviceState *dev, Error **errp)
219
"tz-mpc-downstream");
220
address_space_init(&s->blocked_io_as, &s->blocked_io,
221
"tz-mpc-blocked-io");
222
+
223
+ s->blk_lut = g_new(uint32_t, s->blk_max);
224
+}
225
+
226
+static int tz_mpc_post_load(void *opaque, int version_id)
227
+{
228
+ TZMPC *s = TZ_MPC(opaque);
229
+
230
+ /* Check the incoming data doesn't point blk_idx off the end of blk_lut. */
231
+ if (s->blk_idx >= s->blk_max) {
232
+ return -1;
233
+ }
234
+ return 0;
235
}
236
237
static const VMStateDescription tz_mpc_vmstate = {
238
.name = "tz-mpc",
239
.version_id = 1,
240
.minimum_version_id = 1,
241
+ .post_load = tz_mpc_post_load,
242
.fields = (VMStateField[]) {
243
+ VMSTATE_UINT32(ctrl, TZMPC),
244
+ VMSTATE_UINT32(blk_idx, TZMPC),
245
+ VMSTATE_UINT32(int_stat, TZMPC),
246
+ VMSTATE_UINT32(int_en, TZMPC),
247
+ VMSTATE_UINT32(int_info1, TZMPC),
248
+ VMSTATE_UINT32(int_info2, TZMPC),
249
+ VMSTATE_VARRAY_UINT32(blk_lut, TZMPC, blk_max,
250
+ 0, vmstate_info_uint32, uint32_t),
251
VMSTATE_END_OF_LIST()
252
}
253
};
254
--
255
2.17.1
256
257
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 19/28] hw/misc/tz-mpc.c: Implement correct blocked-access behaviour
1
The MPC is guest-configurable for whether blocked accesses:
2
* should be RAZ/WI or cause a bus error
3
* should generate an interrupt or not
1
4
5
Implement this behaviour in the blocked-access handlers.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20180620132032.28865-4-peter.maydell@linaro.org
10
---
11
hw/misc/tz-mpc.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++--
12
1 file changed, 48 insertions(+), 2 deletions(-)
13
14
diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/tz-mpc.c
17
+++ b/hw/misc/tz-mpc.c
18
@@ -XXX,XX +XXX,XX @@ REG32(INT_EN, 0x28)
19
FIELD(INT_EN, IRQ, 0, 1)
20
REG32(INT_INFO1, 0x2c)
21
REG32(INT_INFO2, 0x30)
22
+ FIELD(INT_INFO2, HMASTER, 0, 16)
23
+ FIELD(INT_INFO2, HNONSEC, 16, 1)
24
+ FIELD(INT_INFO2, CFG_NS, 17, 1)
25
REG32(INT_SET, 0x34)
26
FIELD(INT_SET, IRQ, 0, 1)
27
REG32(PIDR4, 0xfd0)
28
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps tz_mpc_reg_ops = {
29
.impl.max_access_size = 4,
30
};
31
32
+static inline bool tz_mpc_cfg_ns(TZMPC *s, hwaddr addr)
33
+{
34
+ /* Return the cfg_ns bit from the LUT for the specified address */
35
+ hwaddr blknum = addr / s->blocksize;
36
+ hwaddr blkword = blknum / 32;
37
+ uint32_t blkbit = 1U << (blknum % 32);
38
+
39
+ /* This would imply the address was larger than the size we
40
+ * defined this memory region to be, so it can't happen.
41
+ */
42
+ assert(blkword < s->blk_max);
43
+ return s->blk_lut[blkword] & blkbit;
44
+}
45
+
46
+static MemTxResult tz_mpc_handle_block(TZMPC *s, hwaddr addr, MemTxAttrs attrs)
47
+{
48
+ /* Handle a blocked transaction: raise IRQ, capture info, etc */
49
+ if (!s->int_stat) {
50
+ /* First blocked transfer: capture information into INT_INFO1 and
51
+ * INT_INFO2. Subsequent transfers are still blocked but don't
52
+ * capture information until the guest clears the interrupt.
53
+ */
54
+
55
+ s->int_info1 = addr;
56
+ s->int_info2 = 0;
57
+ s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, HMASTER,
58
+ attrs.requester_id & 0xffff);
59
+ s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, HNONSEC,
60
+ ~attrs.secure);
61
+ s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, CFG_NS,
62
+ tz_mpc_cfg_ns(s, addr));
63
+ s->int_stat |= R_INT_STAT_IRQ_MASK;
64
+ tz_mpc_irq_update(s);
65
+ }
66
+
67
+ /* Generate bus error if desired; otherwise RAZ/WI */
68
+ return (s->ctrl & R_CTRL_SEC_RESP_MASK) ? MEMTX_ERROR : MEMTX_OK;
69
+}
70
+
71
/* Accesses only reach these read and write functions if the MPC is
72
* blocking them; non-blocked accesses go directly to the downstream
73
* memory region without passing through this code.
74
@@ -XXX,XX +XXX,XX @@ static MemTxResult tz_mpc_mem_blocked_read(void *opaque, hwaddr addr,
75
uint64_t *pdata,
76
unsigned size, MemTxAttrs attrs)
77
{
78
+ TZMPC *s = TZ_MPC(opaque);
79
+
80
trace_tz_mpc_mem_blocked_read(addr, size, attrs.secure);
81
82
*pdata = 0;
83
- return MEMTX_OK;
84
+ return tz_mpc_handle_block(s, addr, attrs);
85
}
86
87
static MemTxResult tz_mpc_mem_blocked_write(void *opaque, hwaddr addr,
88
uint64_t value,
89
unsigned size, MemTxAttrs attrs)
90
{
91
+ TZMPC *s = TZ_MPC(opaque);
92
+
93
trace_tz_mpc_mem_blocked_write(addr, value, size, attrs.secure);
94
95
- return MEMTX_OK;
96
+ return tz_mpc_handle_block(s, addr, attrs);
97
}
98
99
static const MemoryRegionOps tz_mpc_mem_blocked_ops = {
100
--
101
2.17.1
102
103
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 20/28] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate
1
The final part of the Memory Protection Controller we need to
2
implement is actually using the BLK_LUT data programmed by the
3
guest to determine whether to block the transaction or not.
1
4
5
Since this means we now change transaction mappings when
6
the guest writes to BLK_LUT, we must also call the IOMMU
7
notifiers at that point.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 20180620132032.28865-5-peter.maydell@linaro.org
12
---
13
hw/misc/tz-mpc.c | 53 ++++++++++++++++++++++++++++++++++++++++++--
14
hw/misc/trace-events | 1 +
15
2 files changed, 52 insertions(+), 2 deletions(-)
16
17
diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/tz-mpc.c
20
+++ b/hw/misc/tz-mpc.c
21
@@ -XXX,XX +XXX,XX @@ static void tz_mpc_irq_update(TZMPC *s)
22
qemu_set_irq(s->irq, s->int_stat && s->int_en);
23
}
24
25
+static void tz_mpc_iommu_notify(TZMPC *s, uint32_t lutidx,
26
+ uint32_t oldlut, uint32_t newlut)
27
+{
28
+ /* Called when the LUT word at lutidx has changed from oldlut to newlut;
29
+ * must call the IOMMU notifiers for the changed blocks.
30
+ */
31
+ IOMMUTLBEntry entry = {
32
+ .addr_mask = s->blocksize - 1,
33
+ };
34
+ hwaddr addr = lutidx * s->blocksize * 32;
35
+ int i;
36
+
37
+ for (i = 0; i < 32; i++, addr += s->blocksize) {
38
+ bool block_is_ns;
39
+
40
+ if (!((oldlut ^ newlut) & (1 << i))) {
41
+ continue;
42
+ }
43
+ /* This changes the mappings for both the S and the NS space,
44
+ * so we need to do four notifies: an UNMAP then a MAP for each.
45
+ */
46
+ block_is_ns = newlut & (1 << i);
47
+
48
+ trace_tz_mpc_iommu_notify(addr);
49
+ entry.iova = addr;
50
+ entry.translated_addr = addr;
51
+
52
+ entry.perm = IOMMU_NONE;
53
+ memory_region_notify_iommu(&s->upstream, IOMMU_IDX_S, entry);
54
+ memory_region_notify_iommu(&s->upstream, IOMMU_IDX_NS, entry);
55
+
56
+ entry.perm = IOMMU_RW;
57
+ if (block_is_ns) {
58
+ entry.target_as = &s->blocked_io_as;
59
+ } else {
60
+ entry.target_as = &s->downstream_as;
61
+ }
62
+ memory_region_notify_iommu(&s->upstream, IOMMU_IDX_S, entry);
63
+ if (block_is_ns) {
64
+ entry.target_as = &s->downstream_as;
65
+ } else {
66
+ entry.target_as = &s->blocked_io_as;
67
+ }
68
+ memory_region_notify_iommu(&s->upstream, IOMMU_IDX_NS, entry);
69
+ }
70
+}
71
+
72
static void tz_mpc_autoinc_idx(TZMPC *s, unsigned access_size)
73
{
74
/* Auto-increment BLK_IDX if necessary */
75
@@ -XXX,XX +XXX,XX @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
76
s->blk_idx = value % s->blk_max;
77
break;
78
case A_BLK_LUT:
79
+ tz_mpc_iommu_notify(s, s->blk_idx, s->blk_lut[s->blk_idx], value);
80
s->blk_lut[s->blk_idx] = value;
81
tz_mpc_autoinc_idx(s, size);
82
break;
83
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry tz_mpc_translate(IOMMUMemoryRegion *iommu,
84
/* Look at the per-block configuration for this address, and
85
* return a TLB entry directing the transaction at either
86
* downstream_as or blocked_io_as, as appropriate.
87
- * For the moment, always permit accesses.
88
+ * If the LUT cfg_ns bit is 1, only non-secure transactions
89
+ * may pass. If the bit is 0, only secure transactions may pass.
90
*/
91
- ok = true;
92
+ ok = tz_mpc_cfg_ns(s, addr) == (iommu_idx == IOMMU_IDX_NS);
93
94
trace_tz_mpc_translate(addr, flags,
95
iommu_idx == IOMMU_IDX_S ? "S" : "NS",
96
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
97
index XXXXXXX..XXXXXXX 100644
98
--- a/hw/misc/trace-events
99
+++ b/hw/misc/trace-events
100
@@ -XXX,XX +XXX,XX @@ tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs wri
101
tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d"
102
tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d"
103
tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s"
104
+tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64
105
106
# hw/misc/tz-ppc.c
107
tz_ppc_reset(void) "TZ PPC: reset"
108
--
109
2.17.1
110
111
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 21/28] hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS
1
Implement the SECMPCINTSTATUS register. This is the only register
2
in the security controller that deals with Memory Protection
3
Controllers, and it simply provides a read-only view of the
4
interrupt lines from the various MPCs in the system.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20180620132032.28865-6-peter.maydell@linaro.org
8
---
9
include/hw/misc/iotkit-secctl.h | 8 +++++++
10
hw/misc/iotkit-secctl.c | 38 +++++++++++++++++++++++++++++++--
11
2 files changed, 44 insertions(+), 2 deletions(-)
12
13
diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/misc/iotkit-secctl.h
16
+++ b/include/hw/misc/iotkit-secctl.h
17
@@ -XXX,XX +XXX,XX @@
18
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
19
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
20
* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
21
+ * Controlling the MPC in the IoTKit:
22
+ * + named GPIO input mpc_status
23
+ * Controlling each of the 16 expansion MPCs which a system using the IoTKit
24
+ * might provide:
25
+ * + named GPIO inputs mpcexp_status[0..15]
26
*/
27
28
#ifndef IOTKIT_SECCTL_H
29
@@ -XXX,XX +XXX,XX @@
30
#define IOTS_NUM_APB_PPC 2
31
#define IOTS_NUM_APB_EXP_PPC 4
32
#define IOTS_NUM_AHB_EXP_PPC 4
33
+#define IOTS_NUM_EXP_MPC 16
34
+#define IOTS_NUM_MPC 1
35
36
typedef struct IoTKitSecCtl IoTKitSecCtl;
37
38
@@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl {
39
uint32_t secrespcfg;
40
uint32_t nsccfg;
41
uint32_t brginten;
42
+ uint32_t mpcintstatus;
43
44
IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
45
IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
46
diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/misc/iotkit-secctl.c
49
+++ b/hw/misc/iotkit-secctl.c
50
@@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr,
51
case A_NSCCFG:
52
r = s->nsccfg;
53
break;
54
+ case A_SECMPCINTSTATUS:
55
+ r = s->mpcintstatus;
56
+ break;
57
case A_SECPPCINTSTAT:
58
r = s->secppcintstat;
59
break;
60
@@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr,
61
case A_APBSPPPCEXP3:
62
r = s->apbexp[offset_to_ppc_idx(offset)].sp;
63
break;
64
- case A_SECMPCINTSTATUS:
65
case A_SECMSCINTSTAT:
66
case A_SECMSCINTEN:
67
case A_NSMSCEXP:
68
@@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_reset(DeviceState *dev)
69
foreach_ppc(s, iotkit_secctl_reset_ppc);
70
}
71
72
+static void iotkit_secctl_mpc_status(void *opaque, int n, int level)
73
+{
74
+ IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
75
+
76
+ s->mpcintstatus = deposit32(s->mpcintstatus, 0, 1, !!level);
77
+}
78
+
79
+static void iotkit_secctl_mpcexp_status(void *opaque, int n, int level)
80
+{
81
+ IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
82
+
83
+ s->mpcintstatus = deposit32(s->mpcintstatus, n + 16, 1, !!level);
84
+}
85
+
86
static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level)
87
{
88
IoTKitSecCtlPPC *ppc = opaque;
89
@@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj)
90
qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1);
91
qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1);
92
93
+ qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", 1);
94
+ qdev_init_gpio_in_named(dev, iotkit_secctl_mpcexp_status,
95
+ "mpcexp_status", IOTS_NUM_EXP_MPC);
96
+
97
memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops,
98
s, "iotkit-secctl-s-regs", 0x1000);
99
memory_region_init_io(&s->ns_regs, obj, &iotkit_secctl_ns_ops,
100
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_secctl_ppc_vmstate = {
101
}
102
};
103
104
+static const VMStateDescription iotkit_secctl_mpcintstatus_vmstate = {
105
+ .name = "iotkit-secctl-mpcintstatus",
106
+ .version_id = 1,
107
+ .minimum_version_id = 1,
108
+ .fields = (VMStateField[]) {
109
+ VMSTATE_UINT32(mpcintstatus, IoTKitSecCtl),
110
+ VMSTATE_END_OF_LIST()
111
+ }
112
+};
113
+
114
static const VMStateDescription iotkit_secctl_vmstate = {
115
.name = "iotkit-secctl",
116
.version_id = 1,
117
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_secctl_vmstate = {
118
VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1,
119
iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC),
120
VMSTATE_END_OF_LIST()
121
- }
122
+ },
123
+ .subsections = (const VMStateDescription*[]) {
124
+ &iotkit_secctl_mpcintstatus_vmstate,
125
+ NULL
126
+ },
127
};
128
129
static void iotkit_secctl_class_init(ObjectClass *klass, void *data)
130
--
131
2.17.1
132
133
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 22/28] hw/arm/iotkit: Instantiate MPC
1
Wire up the one MPC that is part of the IoTKit itself. For the
2
moment we don't wire up its interrupt line.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20180620132032.28865-7-peter.maydell@linaro.org
7
---
8
include/hw/arm/iotkit.h | 2 ++
9
hw/arm/iotkit.c | 38 +++++++++++++++++++++++++++-----------
10
2 files changed, 29 insertions(+), 11 deletions(-)
11
12
diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/arm/iotkit.h
15
+++ b/include/hw/arm/iotkit.h
16
@@ -XXX,XX +XXX,XX @@
17
#include "hw/arm/armv7m.h"
18
#include "hw/misc/iotkit-secctl.h"
19
#include "hw/misc/tz-ppc.h"
20
+#include "hw/misc/tz-mpc.h"
21
#include "hw/timer/cmsdk-apb-timer.h"
22
#include "hw/misc/unimp.h"
23
#include "hw/or-irq.h"
24
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKit {
25
IoTKitSecCtl secctl;
26
TZPPC apb_ppc0;
27
TZPPC apb_ppc1;
28
+ TZMPC mpc;
29
CMSDKAPBTIMER timer0;
30
CMSDKAPBTIMER timer1;
31
qemu_or_irq ppc_irq_orgate;
32
diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/iotkit.c
35
+++ b/hw/arm/iotkit.c
36
@@ -XXX,XX +XXX,XX @@ static void iotkit_init(Object *obj)
37
TYPE_TZ_PPC);
38
init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1),
39
TYPE_TZ_PPC);
40
+ init_sysbus_child(obj, "mpc", &s->mpc, sizeof(s->mpc), TYPE_TZ_MPC);
41
init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0),
42
TYPE_CMSDK_APB_TIMER);
43
init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1),
44
@@ -XXX,XX +XXX,XX @@ static void iotkit_realize(DeviceState *dev, Error **errp)
45
*/
46
make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000);
47
48
- /* This RAM should be behind a Memory Protection Controller, but we
49
- * don't implement that yet.
50
- */
51
- memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err);
52
- if (err) {
53
- error_propagate(errp, err);
54
- return;
55
- }
56
- memory_region_add_subregion(&s->container, 0x20000000, &s->sram0);
57
58
/* Security controller */
59
object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err);
60
@@ -XXX,XX +XXX,XX @@ static void iotkit_realize(DeviceState *dev, Error **errp)
61
qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0,
62
qdev_get_gpio_in(dev_splitter, 0));
63
64
+ /* This RAM lives behind the Memory Protection Controller */
65
+ memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err);
66
+ if (err) {
67
+ error_propagate(errp, err);
68
+ return;
69
+ }
70
+ object_property_set_link(OBJECT(&s->mpc), OBJECT(&s->sram0),
71
+ "downstream", &err);
72
+ if (err) {
73
+ error_propagate(errp, err);
74
+ return;
75
+ }
76
+ object_property_set_bool(OBJECT(&s->mpc), true, "realized", &err);
77
+ if (err) {
78
+ error_propagate(errp, err);
79
+ return;
80
+ }
81
+ /* Map the upstream end of the MPC into the right place... */
82
+ memory_region_add_subregion(&s->container, 0x20000000,
83
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mpc),
84
+ 1));
85
+ /* ...and its register interface */
86
+ memory_region_add_subregion(&s->container, 0x50083000,
87
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mpc),
88
+ 0));
89
+
90
/* Devices behind APB PPC0:
91
* 0x40000000: timer0
92
* 0x40001000: timer1
93
@@ -XXX,XX +XXX,XX @@ static void iotkit_realize(DeviceState *dev, Error **errp)
94
create_unimplemented_device("NS watchdog", 0x40081000, 0x1000);
95
create_unimplemented_device("S watchdog", 0x50081000, 0x1000);
96
97
- create_unimplemented_device("SRAM0 MPC", 0x50083000, 0x1000);
98
-
99
for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
100
Object *splitter = OBJECT(&s->ppc_irq_splitter[i]);
101
102
--
103
2.17.1
104
105
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 23/28] hw/arm/iotkit: Wire up MPC interrupt lines
1
The interrupt outputs from the MPC in the IoTKit and the expansion
2
MPCs in the board must be wired up to the security controller, and
3
also all ORed together to produce a single line to the NVIC.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180620132032.28865-8-peter.maydell@linaro.org
8
---
9
include/hw/arm/iotkit.h | 6 ++++
10
hw/arm/iotkit.c | 74 +++++++++++++++++++++++++++++++++++++++++
11
2 files changed, 80 insertions(+)
12
13
diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/iotkit.h
16
+++ b/include/hw/arm/iotkit.h
17
@@ -XXX,XX +XXX,XX @@
18
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
19
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
20
* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
21
+ * Controlling each of the 16 expansion MPCs which a system using the IoTKit
22
+ * might provide:
23
+ * + named GPIO inputs mpcexp_status[0..15]
24
*/
25
26
#ifndef IOTKIT_H
27
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKit {
28
qemu_or_irq ppc_irq_orgate;
29
SplitIRQ sec_resp_splitter;
30
SplitIRQ ppc_irq_splitter[NUM_PPCS];
31
+ SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
32
+ qemu_or_irq mpc_irq_orgate;
33
34
UnimplementedDeviceState dualtimer;
35
UnimplementedDeviceState s32ktimer;
36
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKit {
37
qemu_irq nsc_cfg_in;
38
39
qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
40
+ qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
41
42
uint32_t nsccfg;
43
44
diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/iotkit.c
47
+++ b/hw/arm/iotkit.c
48
@@ -XXX,XX +XXX,XX @@ static void iotkit_init(Object *obj)
49
init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1),
50
TYPE_TZ_PPC);
51
init_sysbus_child(obj, "mpc", &s->mpc, sizeof(s->mpc), TYPE_TZ_MPC);
52
+ object_initialize(&s->mpc_irq_orgate, sizeof(s->mpc_irq_orgate),
53
+ TYPE_OR_IRQ);
54
+ object_property_add_child(obj, "mpc-irq-orgate",
55
+ OBJECT(&s->mpc_irq_orgate), &error_abort);
56
+ for (i = 0; i < ARRAY_SIZE(s->mpc_irq_splitter); i++) {
57
+ char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
58
+ SplitIRQ *splitter = &s->mpc_irq_splitter[i];
59
+
60
+ object_initialize(splitter, sizeof(*splitter), TYPE_SPLIT_IRQ);
61
+ object_property_add_child(obj, name, OBJECT(splitter), &error_abort);
62
+ g_free(name);
63
+ }
64
init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0),
65
TYPE_CMSDK_APB_TIMER);
66
init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1),
67
@@ -XXX,XX +XXX,XX @@ static void iotkit_exp_irq(void *opaque, int n, int level)
68
qemu_set_irq(s->exp_irqs[n], level);
69
}
70
71
+static void iotkit_mpcexp_status(void *opaque, int n, int level)
72
+{
73
+ IoTKit *s = IOTKIT(opaque);
74
+ qemu_set_irq(s->mpcexp_status_in[n], level);
75
+}
76
+
77
static void iotkit_realize(DeviceState *dev, Error **errp)
78
{
79
IoTKit *s = IOTKIT(dev);
80
@@ -XXX,XX +XXX,XX @@ static void iotkit_realize(DeviceState *dev, Error **errp)
81
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mpc),
82
0));
83
84
+ /* We must OR together lines from the MPC splitters to go to the NVIC */
85
+ object_property_set_int(OBJECT(&s->mpc_irq_orgate),
86
+ IOTS_NUM_EXP_MPC + IOTS_NUM_MPC, "num-lines", &err);
87
+ if (err) {
88
+ error_propagate(errp, err);
89
+ return;
90
+ }
91
+ object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true,
92
+ "realized", &err);
93
+ if (err) {
94
+ error_propagate(errp, err);
95
+ return;
96
+ }
97
+ qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0,
98
+ qdev_get_gpio_in(DEVICE(&s->armv7m), 9));
99
+
100
/* Devices behind APB PPC0:
101
* 0x40000000: timer0
102
* 0x40001000: timer1
103
@@ -XXX,XX +XXX,XX @@ static void iotkit_realize(DeviceState *dev, Error **errp)
104
g_free(gpioname);
105
}
106
107
+ /* Wire up the splitters for the MPC IRQs */
108
+ for (i = 0; i < IOTS_NUM_EXP_MPC + IOTS_NUM_MPC; i++) {
109
+ SplitIRQ *splitter = &s->mpc_irq_splitter[i];
110
+ DeviceState *dev_splitter = DEVICE(splitter);
111
+
112
+ object_property_set_int(OBJECT(splitter), 2, "num-lines", &err);
113
+ if (err) {
114
+ error_propagate(errp, err);
115
+ return;
116
+ }
117
+ object_property_set_bool(OBJECT(splitter), true, "realized", &err);
118
+ if (err) {
119
+ error_propagate(errp, err);
120
+ return;
121
+ }
122
+
123
+ if (i < IOTS_NUM_EXP_MPC) {
124
+ /* Splitter input is from GPIO input line */
125
+ s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0);
126
+ qdev_connect_gpio_out(dev_splitter, 0,
127
+ qdev_get_gpio_in_named(dev_secctl,
128
+ "mpcexp_status", i));
129
+ } else {
130
+ /* Splitter input is from our own MPC */
131
+ qdev_connect_gpio_out_named(DEVICE(&s->mpc), "irq", 0,
132
+ qdev_get_gpio_in(dev_splitter, 0));
133
+ qdev_connect_gpio_out(dev_splitter, 0,
134
+ qdev_get_gpio_in_named(dev_secctl,
135
+ "mpc_status", 0));
136
+ }
137
+
138
+ qdev_connect_gpio_out(dev_splitter, 1,
139
+ qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i));
140
+ }
141
+ /* Create GPIO inputs which will pass the line state for our
142
+ * mpcexp_irq inputs to the correct splitter devices.
143
+ */
144
+ qdev_init_gpio_in_named(dev, iotkit_mpcexp_status, "mpcexp_status",
145
+ IOTS_NUM_EXP_MPC);
146
+
147
iotkit_forward_sec_resp_cfg(s);
148
149
system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq;
150
--
151
2.17.1
152
153
diff view generated by jsdifflib
[PULL 07/11] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code
[Qemu-devel] [PULL 24/28] hw/arm/mps2-tz.c: Instantiate MPCs
1
From: John Högberg <john.hogberg@ericsson.com>
1
Instantiate and wire up the Memory Protection Controllers
2
in the MPS2 board itself.
2
3
3
https://gitlab.com/qemu-project/qemu/-/issues/1034
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20180620132032.28865-9-peter.maydell@linaro.org
7
---
8
hw/arm/mps2-tz.c | 71 ++++++++++++++++++++++++++++++------------------
9
1 file changed, 44 insertions(+), 27 deletions(-)
4
10
5
Signed-off-by: John Högberg <john.hogberg@ericsson.com>
11
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
6
Message-id: 168778890374.24232.3402138851538068785-2@git.sr.ht
12
index XXXXXXX..XXXXXXX 100644
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
--- a/hw/arm/mps2-tz.c
8
[PMM: fixed typo in comment]
14
+++ b/hw/arm/mps2-tz.c
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
tests/tcg/aarch64/icivau.c | 189 ++++++++++++++++++++++++++++++
12
tests/tcg/aarch64/Makefile.target | 3 +-
13
2 files changed, 191 insertions(+), 1 deletion(-)
14
create mode 100644 tests/tcg/aarch64/icivau.c
15
16
diff --git a/tests/tcg/aarch64/icivau.c b/tests/tcg/aarch64/icivau.c
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/tests/tcg/aarch64/icivau.c
21
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
22
+/*
16
#include "hw/timer/cmsdk-apb-timer.h"
23
+ * Tests the IC IVAU-driven workaround for catching changes made to dual-mapped
17
#include "hw/misc/mps2-scc.h"
24
+ * code that would otherwise go unnoticed in user mode.
18
#include "hw/misc/mps2-fpgaio.h"
25
+ *
19
+#include "hw/misc/tz-mpc.h"
26
+ * Copyright (c) 2023 Ericsson AB
20
#include "hw/arm/iotkit.h"
27
+ * SPDX-License-Identifier: GPL-2.0-or-later
21
#include "hw/devices.h"
28
+ */
22
#include "net/net.h"
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
25
IoTKit iotkit;
26
MemoryRegion psram;
27
- MemoryRegion ssram1;
28
+ MemoryRegion ssram[3];
29
MemoryRegion ssram1_m;
30
- MemoryRegion ssram23;
31
MPS2SCC scc;
32
MPS2FPGAIO fpgaio;
33
TZPPC ppc[5];
34
- UnimplementedDeviceState ssram_mpc[3];
35
+ TZMPC ssram_mpc[3];
36
UnimplementedDeviceState spi[5];
37
UnimplementedDeviceState i2c[4];
38
UnimplementedDeviceState i2s_audio;
39
@@ -XXX,XX +XXX,XX @@ typedef struct {
40
/* Main SYSCLK frequency in Hz */
41
#define SYSCLK_FRQ 20000000
42
43
-/* Initialize the auxiliary RAM region @mr and map it into
44
- * the memory map at @base.
45
- */
46
-static void make_ram(MemoryRegion *mr, const char *name,
47
- hwaddr base, hwaddr size)
48
-{
49
- memory_region_init_ram(mr, NULL, name, size, &error_fatal);
50
- memory_region_add_subregion(get_system_memory(), base, mr);
51
-}
52
-
53
/* Create an alias of an entire original MemoryRegion @orig
54
* located at @base in the memory map.
55
*/
56
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
57
return sysbus_mmio_get_region(s, 0);
58
}
59
60
+static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
61
+ const char *name, hwaddr size)
62
+{
63
+ TZMPC *mpc = opaque;
64
+ int i = mpc - &mms->ssram_mpc[0];
65
+ MemoryRegion *ssram = &mms->ssram[i];
66
+ MemoryRegion *upstream;
67
+ char *mpcname = g_strdup_printf("%s-mpc", name);
68
+ static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 };
69
+ static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 };
29
+
70
+
30
+#include <sys/mman.h>
71
+ memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
31
+#include <sys/stat.h>
32
+#include <string.h>
33
+#include <stdint.h>
34
+#include <stdlib.h>
35
+#include <unistd.h>
36
+#include <fcntl.h>
37
+
72
+
38
+#define MAX_CODE_SIZE 128
73
+ init_sysbus_child(OBJECT(mms), mpcname, mpc,
74
+ sizeof(mms->ssram_mpc[0]), TYPE_TZ_MPC);
75
+ object_property_set_link(OBJECT(mpc), OBJECT(ssram),
76
+ "downstream", &error_fatal);
77
+ object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
78
+ /* Map the upstream end of the MPC into system memory */
79
+ upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
80
+ memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
81
+ /* and connect its interrupt to the IoTKit */
82
+ qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
83
+ qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
84
+ "mpcexp_status", i));
39
+
85
+
40
+typedef int (SelfModTest)(uint32_t, uint32_t*);
86
+ /* The first SSRAM is a special case as it has an alias; accesses to
41
+typedef int (BasicTest)(int);
87
+ * the alias region at 0x00400000 must also go to the MPC upstream.
42
+
43
+static void mark_code_modified(const uint32_t *exec_data, size_t length)
44
+{
45
+ int dc_required, ic_required;
46
+ unsigned long ctr_el0;
47
+
48
+ /*
49
+ * Clear the data/instruction cache, as indicated by the CTR_ELO.{DIC,IDC}
50
+ * flags.
51
+ *
52
+ * For completeness we might be tempted to assert that we should fail when
53
+ * the whole code update sequence is omitted, but that would make the test
54
+ * flaky as it can succeed by coincidence on actual hardware.
55
+ */
88
+ */
56
+ asm ("mrs %0, ctr_el0\n" : "=r"(ctr_el0));
89
+ if (i == 0) {
57
+
90
+ make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000);
58
+ /* CTR_EL0.IDC */
59
+ dc_required = !((ctr_el0 >> 28) & 1);
60
+
61
+ /* CTR_EL0.DIC */
62
+ ic_required = !((ctr_el0 >> 29) & 1);
63
+
64
+ if (dc_required) {
65
+ size_t dcache_stride, i;
66
+
67
+ /*
68
+ * Step according to the minimum cache size, as the cache maintenance
69
+ * instructions operate on the cache line of the given address.
70
+ *
71
+ * We assume that exec_data is properly aligned.
72
+ */
73
+ dcache_stride = (4 << ((ctr_el0 >> 16) & 0xF));
74
+
75
+ for (i = 0; i < length; i += dcache_stride) {
76
+ const char *dc_addr = &((const char *)exec_data)[i];
77
+ asm volatile ("dc cvau, %x[dc_addr]\n"
78
+ : /* no outputs */
79
+ : [dc_addr] "r"(dc_addr)
80
+ : "memory");
81
+ }
82
+
83
+ asm volatile ("dmb ish\n");
84
+ }
91
+ }
85
+
92
+
86
+ if (ic_required) {
93
+ g_free(mpcname);
87
+ size_t icache_stride, i;
94
+ /* Return the register interface MR for our caller to map behind the PPC */
88
+
95
+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
89
+ icache_stride = (4 << (ctr_el0 & 0xF));
90
+
91
+ for (i = 0; i < length; i += icache_stride) {
92
+ const char *ic_addr = &((const char *)exec_data)[i];
93
+ asm volatile ("ic ivau, %x[ic_addr]\n"
94
+ : /* no outputs */
95
+ : [ic_addr] "r"(ic_addr)
96
+ : "memory");
97
+ }
98
+
99
+ asm volatile ("dmb ish\n");
100
+ }
101
+
102
+ asm volatile ("isb sy\n");
103
+}
96
+}
104
+
97
+
105
+static int basic_test(uint32_t *rw_data, const uint32_t *exec_data)
98
static void mps2tz_common_init(MachineState *machine)
106
+{
99
{
107
+ /*
100
MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
108
+ * As user mode only misbehaved for dual-mapped code when previously
101
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
109
+ * translated code had been changed, we'll start off with this basic test
102
NULL, "mps.ram", 0x01000000);
110
+ * function to ensure that there's already some translated code at
103
memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);
111
+ * exec_data before the next test. This should cause the next test to fail
104
112
+ * if `mark_code_modified` fails to invalidate the code.
105
- /* The SSRAM memories should all be behind Memory Protection Controllers,
113
+ *
106
- * but we don't implement that yet.
114
+ * Note that the payload is in binary form instead of inline assembler
107
- */
115
+ * because we cannot use __attribute__((naked)) on this platform and the
108
- make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000);
116
+ * workarounds are at least as ugly as this is.
109
- make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000);
117
+ */
110
-
118
+ static const uint32_t basic_payload[] = {
111
- make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000);
119
+ 0xD65F03C0 /* 0x00: RET */
112
-
120
+ };
113
/* The overflow IRQs for all UARTs are ORed together.
121
+
114
* Tx, Rx and "combined" IRQs are sent to the NVIC separately.
122
+ BasicTest *copied_ptr = (BasicTest *)exec_data;
115
* Create the OR gate for this.
123
+
116
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
124
+ memcpy(rw_data, basic_payload, sizeof(basic_payload));
117
const PPCInfo ppcs[] = { {
125
+ mark_code_modified(exec_data, sizeof(basic_payload));
118
.name = "apb_ppcexp0",
126
+
119
.ports = {
127
+ return copied_ptr(1234) == 1234;
120
- { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0],
128
+}
121
- 0x58007000, 0x1000 },
129
+
122
- { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1],
130
+static int self_modification_test(uint32_t *rw_data, const uint32_t *exec_data)
123
- 0x58008000, 0x1000 },
131
+{
124
- { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2],
132
+ /*
125
- 0x58009000, 0x1000 },
133
+ * This test is self-modifying in an attempt to cover an edge case where
126
+ { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },
134
+ * the IC IVAU instruction invalidates itself.
127
+ { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 },
135
+ *
128
+ { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 },
136
+ * Note that the IC IVAU instruction is 16 bytes into the function, in what
129
},
137
+ * will be the same cache line as the modified instruction on machines with
130
}, {
138
+ * a cache line size >= 16 bytes.
131
.name = "apb_ppcexp1",
139
+ */
140
+ static const uint32_t self_mod_payload[] = {
141
+ /* Overwrite the placeholder instruction with the new one. */
142
+ 0xB9001C20, /* 0x00: STR w0, [x1, 0x1C] */
143
+
144
+ /* Get the executable address of the modified instruction. */
145
+ 0x100000A8, /* 0x04: ADR x8, <0x1C> */
146
+
147
+ /* Mark the modified instruction as updated. */
148
+ 0xD50B7B28, /* 0x08: DC CVAU x8 */
149
+ 0xD5033BBF, /* 0x0C: DMB ISH */
150
+ 0xD50B7528, /* 0x10: IC IVAU x8 */
151
+ 0xD5033BBF, /* 0x14: DMB ISH */
152
+ 0xD5033FDF, /* 0x18: ISB */
153
+
154
+ /* Placeholder instruction, overwritten above. */
155
+ 0x52800000, /* 0x1C: MOV w0, 0 */
156
+
157
+ 0xD65F03C0 /* 0x20: RET */
158
+ };
159
+
160
+ SelfModTest *copied_ptr = (SelfModTest *)exec_data;
161
+ int i;
162
+
163
+ memcpy(rw_data, self_mod_payload, sizeof(self_mod_payload));
164
+ mark_code_modified(exec_data, sizeof(self_mod_payload));
165
+
166
+ for (i = 1; i < 10; i++) {
167
+ /* Replace the placeholder instruction with `MOV w0, i` */
168
+ uint32_t new_instr = 0x52800000 | (i << 5);
169
+
170
+ if (copied_ptr(new_instr, rw_data) != i) {
171
+ return 0;
172
+ }
173
+ }
174
+
175
+ return 1;
176
+}
177
+
178
+int main(int argc, char **argv)
179
+{
180
+ const char *shm_name = "qemu-test-tcg-aarch64-icivau";
181
+ int fd;
182
+
183
+ fd = shm_open(shm_name, O_CREAT | O_RDWR, S_IRUSR | S_IWUSR);
184
+
185
+ if (fd < 0) {
186
+ return EXIT_FAILURE;
187
+ }
188
+
189
+ /* Unlink early to avoid leaving garbage in case the test crashes. */
190
+ shm_unlink(shm_name);
191
+
192
+ if (ftruncate(fd, MAX_CODE_SIZE) == 0) {
193
+ const uint32_t *exec_data;
194
+ uint32_t *rw_data;
195
+
196
+ rw_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_WRITE,
197
+ MAP_SHARED, fd, 0);
198
+ exec_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_EXEC,
199
+ MAP_SHARED, fd, 0);
200
+
201
+ if (rw_data && exec_data) {
202
+ if (basic_test(rw_data, exec_data) &&
203
+ self_modification_test(rw_data, exec_data)) {
204
+ return EXIT_SUCCESS;
205
+ }
206
+ }
207
+ }
208
+
209
+ return EXIT_FAILURE;
210
+}
211
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
212
index XXXXXXX..XXXXXXX 100644
213
--- a/tests/tcg/aarch64/Makefile.target
214
+++ b/tests/tcg/aarch64/Makefile.target
215
@@ -XXX,XX +XXX,XX @@ AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
216
VPATH         += $(AARCH64_SRC)
217
218
# Base architecture tests
219
-AARCH64_TESTS=fcvt pcalign-a64
220
+AARCH64_TESTS=fcvt pcalign-a64 icivau
221
222
fcvt: LDFLAGS+=-lm
223
+icivau: LDFLAGS+=-lrt
224
225
run-fcvt: fcvt
226
    $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
227
--
132
--
228
2.34.1
133
2.17.1
229
134
230
135
diff view generated by jsdifflib
[PULL 03/11] target/arm: Avoid splitting Zregs across lines in dump
[Qemu-devel] [PULL 25/28] target/arm: Introduce ARM_FEATURE_M_MAIN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Julia Suvorova <jusual@mail.ru>
2
2
3
Allow the line length to extend to 548 columns. While annoyingly wide,
3
This feature is intended to distinguish ARMv8-M variants: Baseline and
4
it's still less confusing than the continuations we print. Also, the
4
Mainline. ARMv7-M compatibility requires the Main Extension. ARMv6-M
5
default VL used by Linux (and max for A64FX) uses only 140 columns.
5
compatibility is provided by all ARMv8-M implementations.
6
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Julia Suvorova <jusual@mail.ru>
8
Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org
8
Message-id: 20180622080138.17702-2-jusual@mail.ru
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/cpu.c | 36 ++++++++++++++----------------------
12
target/arm/cpu.h | 1 +
13
1 file changed, 14 insertions(+), 22 deletions(-)
13
target/arm/cpu.c | 3 +++
14
2 files changed, 4 insertions(+)
14
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ enum arm_features {
21
ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */
22
ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
23
ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */
24
+ ARM_FEATURE_M_MAIN, /* M profile Main Extension */
25
};
26
27
static inline int arm_feature(CPUARMState *env, int feature)
15
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
28
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.c
30
--- a/target/arm/cpu.c
18
+++ b/target/arm/cpu.c
31
+++ b/target/arm/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
32
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
20
ARMCPU *cpu = ARM_CPU(cs);
33
ARMCPU *cpu = ARM_CPU(obj);
21
CPUARMState *env = &cpu->env;
34
set_feature(&cpu->env, ARM_FEATURE_V7);
22
uint32_t psr = pstate_read(env);
35
set_feature(&cpu->env, ARM_FEATURE_M);
23
- int i;
36
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
24
+ int i, j;
37
cpu->midr = 0x410fc231;
25
int el = arm_current_el(env);
38
cpu->pmsav7_dregion = 8;
26
const char *ns_status;
39
cpu->id_pfr0 = 0x00000030;
27
bool sve;
40
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
28
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
41
29
}
42
set_feature(&cpu->env, ARM_FEATURE_V7);
30
43
set_feature(&cpu->env, ARM_FEATURE_M);
31
if (sve) {
44
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
32
- int j, zcr_len = sve_vqm1_for_el(env, el);
45
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
33
+ int zcr_len = sve_vqm1_for_el(env, el);
46
cpu->midr = 0x410fc240; /* r0p0 */
34
47
cpu->pmsav7_dregion = 8;
35
for (i = 0; i <= FFR_PRED_NUM; i++) {
48
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
36
bool eol;
49
37
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
50
set_feature(&cpu->env, ARM_FEATURE_V8);
38
}
51
set_feature(&cpu->env, ARM_FEATURE_M);
39
}
52
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
40
53
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
41
- for (i = 0; i < 32; i++) {
54
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
42
- if (zcr_len == 0) {
55
cpu->midr = 0x410fd213; /* r0p3 */
43
+ if (zcr_len == 0) {
44
+ /*
45
+ * With vl=16, there are only 37 columns per register,
46
+ * so output two registers per line.
47
+ */
48
+ for (i = 0; i < 32; i++) {
49
qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
50
i, env->vfp.zregs[i].d[1],
51
env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
52
- } else if (zcr_len == 1) {
53
- qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
54
- ":%016" PRIx64 ":%016" PRIx64 "\n",
55
- i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
56
- env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
57
- } else {
58
+ }
59
+ } else {
60
+ for (i = 0; i < 32; i++) {
61
+ qemu_fprintf(f, "Z%02d=", i);
62
for (j = zcr_len; j >= 0; j--) {
63
- bool odd = (zcr_len - j) % 2 != 0;
64
- if (j == zcr_len) {
65
- qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
66
- } else if (!odd) {
67
- if (j > 0) {
68
- qemu_fprintf(f, " [%x-%x]=", j, j - 1);
69
- } else {
70
- qemu_fprintf(f, " [%x]=", j);
71
- }
72
- }
73
qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
74
env->vfp.zregs[i].d[j * 2 + 1],
75
- env->vfp.zregs[i].d[j * 2],
76
- odd || j == 0 ? "\n" : ":");
77
+ env->vfp.zregs[i].d[j * 2 + 0],
78
+ j ? ":" : "\n");
79
}
80
}
81
}
82
--
56
--
83
2.34.1
57
2.17.1
58
59
diff view generated by jsdifflib
[PULL 09/11] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
[Qemu-devel] [PULL 26/28] target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline
1
From: Fabiano Rosas <farosas@suse.de>
1
From: Julia Suvorova <jusual@mail.ru>
2
2
3
This code is only relevant when TCG is present in the build. Building
3
Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
4
with --disable-tcg --enable-xen on an x86 host we get:
4
aligned memory accesses for load/store instructions.
5
5
6
$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg --enable-xen
6
Signed-off-by: Julia Suvorova <jusual@mail.ru>
7
$ make -j$(nproc)
7
Message-id: 20180622080138.17702-3-jusual@mail.ru
8
...
9
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr':
10
../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr'
11
../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr'
12
13
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `arm_gdb_get_m_systemreg':
14
../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control'
15
16
Signed-off-by: Fabiano Rosas <farosas@suse.de>
17
Message-id: 20230628164821.16771-1-farosas@suse.de
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
10
---
21
target/arm/gdbstub.c | 4 ++++
11
target/arm/translate.c | 18 ++++++++++++++++--
22
1 file changed, 4 insertions(+)
12
1 file changed, 16 insertions(+), 2 deletions(-)
23
13
24
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/gdbstub.c
16
--- a/target/arm/translate.c
27
+++ b/target/arm/gdbstub.c
17
+++ b/target/arm/translate.c
28
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
18
@@ -XXX,XX +XXX,XX @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)
29
return cpu->dyn_sysreg_xml.num;
19
static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
20
int index, TCGMemOp opc)
21
{
22
- TCGv addr = gen_aa32_addr(s, a32, opc);
23
+ TCGv addr;
24
+
25
+ if (arm_dc_feature(s, ARM_FEATURE_M) &&
26
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
27
+ opc |= MO_ALIGN;
28
+ }
29
+
30
+ addr = gen_aa32_addr(s, a32, opc);
31
tcg_gen_qemu_ld_i32(val, addr, index, opc);
32
tcg_temp_free(addr);
30
}
33
}
31
34
@@ -XXX,XX +XXX,XX @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
32
+#ifdef CONFIG_TCG
35
static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
33
typedef enum {
36
int index, TCGMemOp opc)
34
M_SYSREG_MSP,
35
M_SYSREG_PSP,
36
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
37
return cpu->dyn_m_secextreg_xml.num;
38
}
39
#endif
40
+#endif /* CONFIG_TCG */
41
42
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
43
{
37
{
44
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
38
- TCGv addr = gen_aa32_addr(s, a32, opc);
45
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
39
+ TCGv addr;
46
"system-registers.xml", 0);
40
+
47
41
+ if (arm_dc_feature(s, ARM_FEATURE_M) &&
48
+#ifdef CONFIG_TCG
42
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
49
if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
43
+ opc |= MO_ALIGN;
50
gdb_register_coprocessor(cs,
44
+ }
51
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
45
+
52
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
46
+ addr = gen_aa32_addr(s, a32, opc);
53
}
47
tcg_gen_qemu_st_i32(val, addr, index, opc);
54
#endif
48
tcg_temp_free(addr);
55
}
56
+#endif /* CONFIG_TCG */
57
}
49
}
58
--
50
--
59
2.34.1
51
2.17.1
52
53
diff view generated by jsdifflib
[PULL 11/11] target/xtensa: Assert that interrupt level is within bounds
[Qemu-devel] [PULL 27/28] vl.c: Don't zero-initialize statics for serial_hds
1
In handle_interrupt() we use level as an index into the interrupt_vector[]
1
checkpatch reminds us that statics shouldn't be zero-initialized:
2
array. This is safe because we have checked it against env->config->nlevel,
3
but Coverity can't see that (and it is only true because each CPU config
4
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
5
complains about a possible array overrun (CID 1507131)
6
2
7
Add an assert() which will make Coverity happy and catch the unlikely
3
ERROR: do not initialise statics to 0 or NULL
8
case of a mis-set XCHAL_NUM_INTLEVELS in future.
4
#35: FILE: vl.c:157:
5
+static int num_serial_hds = 0;
6
7
ERROR: do not initialise statics to 0 or NULL
8
#36: FILE: vl.c:158:
9
+static Chardev **serial_hds = NULL;
10
11
I forgot to fix this in 6af2692e86f9fdfb3d; do so now.
9
12
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
14
Reviewed-by: Thomas Huth <thuth@redhat.com>
12
Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org
15
Message-id: 20180426140253.3918-1-peter.maydell@linaro.org
13
---
16
---
14
target/xtensa/exc_helper.c | 3 +++
17
vl.c | 4 ++--
15
1 file changed, 3 insertions(+)
18
1 file changed, 2 insertions(+), 2 deletions(-)
16
19
17
diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
20
diff --git a/vl.c b/vl.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/target/xtensa/exc_helper.c
22
--- a/vl.c
20
+++ b/target/xtensa/exc_helper.c
23
+++ b/vl.c
21
@@ -XXX,XX +XXX,XX @@ static void handle_interrupt(CPUXtensaState *env)
24
@@ -XXX,XX +XXX,XX @@ QEMUClockType rtc_clock;
22
CPUState *cs = env_cpu(env);
25
int vga_interface_type = VGA_NONE;
23
26
static DisplayOptions dpy;
24
if (level > 1) {
27
int no_frame;
25
+ /* env->config->nlevel check should have ensured this */
28
-static int num_serial_hds = 0;
26
+ assert(level < sizeof(env->config->interrupt_vector));
29
-static Chardev **serial_hds = NULL;
27
+
30
+static int num_serial_hds;
28
env->sregs[EPC1 + level - 1] = env->pc;
31
+static Chardev **serial_hds;
29
env->sregs[EPS2 + level - 2] = env->sregs[PS];
32
Chardev *parallel_hds[MAX_PARALLEL_PORTS];
30
env->sregs[PS] =
33
Chardev *virtcon_hds[MAX_VIRTIO_CONSOLES];
34
int win2k_install_hack = 0;
31
--
35
--
32
2.34.1
36
2.17.1
37
38
diff view generated by jsdifflib
[PULL 08/11] tests/qtest: xlnx-canfd-test: Fix code coverity issues
[Qemu-devel] [PULL 28/28] xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom()
1
From: Vikram Garhwal <vikram.garhwal@amd.com>
1
The xen pci_assign_dev_load_option_rom() currently creates a RAM
2
memory region with memory_region_init_ram_nomigrate(), and then
3
manually registers it with vmstate_register_ram(). In fact for
4
its only callsite, the 'owner' pointer we use for the init call
5
and the '&dev->qdev' pointer we use for the vmstate_register_ram()
6
call refer to the same object. Simplify the function to only
7
take a pointer to the device once instead of twice, and use
8
memory_region_init_ram() which automatically does the vmstate
9
register for us.
2
10
3
Following are done to fix the coverity issues:
11
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
4
1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN)
5
2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE)
6
3. Replace rand() in generate_random_data() with g_rand_int()
7
8
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
9
Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
tests/qtest/xlnx-canfd-test.c | 33 +++++++++++----------------------
14
hw/xen/xen_pt.h | 2 +-
14
1 file changed, 11 insertions(+), 22 deletions(-)
15
hw/xen/xen_pt_graphics.c | 2 +-
16
hw/xen/xen_pt_load_rom.c | 6 +++---
17
3 files changed, 5 insertions(+), 5 deletions(-)
15
18
16
diff --git a/tests/qtest/xlnx-canfd-test.c b/tests/qtest/xlnx-canfd-test.c
19
diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/qtest/xlnx-canfd-test.c
21
--- a/hw/xen/xen_pt.h
19
+++ b/tests/qtest/xlnx-canfd-test.c
22
+++ b/hw/xen/xen_pt.h
20
@@ -XXX,XX +XXX,XX @@ static void generate_random_data(uint32_t *buf_tx, bool is_canfd_frame)
23
@@ -XXX,XX +XXX,XX @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
21
/* Generate random TX data for CANFD frame. */
22
if (is_canfd_frame) {
23
for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) {
24
- buf_tx[2 + i] = rand();
25
+ buf_tx[2 + i] = g_random_int();
26
}
27
} else {
28
/* Generate random TX data for CAN frame. */
29
for (int i = 0; i < CAN_FRAME_SIZE - 2; i++) {
30
- buf_tx[2 + i] = rand();
31
+ buf_tx[2 + i] = g_random_int();
32
}
33
}
34
}
24
}
35
25
36
-static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
26
extern void *pci_assign_dev_load_option_rom(PCIDevice *dev,
37
+static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx,
27
- struct Object *owner, int *size,
38
+ uint32_t frame_size)
28
+ int *size,
29
unsigned int domain,
30
unsigned int bus, unsigned int slot,
31
unsigned int function);
32
diff --git a/hw/xen/xen_pt_graphics.c b/hw/xen/xen_pt_graphics.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/xen/xen_pt_graphics.c
35
+++ b/hw/xen/xen_pt_graphics.c
36
@@ -XXX,XX +XXX,XX @@ int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev)
37
static void *get_vgabios(XenPCIPassthroughState *s, int *size,
38
XenHostPCIDevice *dev)
39
{
39
{
40
uint32_t int_status;
40
- return pci_assign_dev_load_option_rom(&s->dev, OBJECT(&s->dev), size,
41
uint32_t fifo_status_reg_value;
41
+ return pci_assign_dev_load_option_rom(&s->dev, size,
42
/* At which RX FIFO the received data is stored. */
42
dev->domain, dev->bus,
43
uint8_t store_ind = 0;
43
dev->dev, dev->func);
44
- bool is_canfd_frame = false;
44
}
45
45
diff --git a/hw/xen/xen_pt_load_rom.c b/hw/xen/xen_pt_load_rom.c
46
/* Read the interrupt on CANFD rx. */
46
index XXXXXXX..XXXXXXX 100644
47
int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
47
--- a/hw/xen/xen_pt_load_rom.c
48
@@ -XXX,XX +XXX,XX @@ static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
48
+++ b/hw/xen/xen_pt_load_rom.c
49
buf_rx[0] = qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET);
49
@@ -XXX,XX +XXX,XX @@
50
buf_rx[1] = qtest_readl(qts, can_base_addr + R_RX0_DLC_OFFSET);
50
* load the corresponding ROM data to RAM. If an error occurs while loading an
51
51
* option ROM, we just ignore that option ROM and continue with the next one.
52
- is_canfd_frame = (buf_rx[1] >> DLC_FD_BIT_SHIFT) & 1;
52
*/
53
-
53
-void *pci_assign_dev_load_option_rom(PCIDevice *dev, struct Object *owner,
54
- if (is_canfd_frame) {
54
+void *pci_assign_dev_load_option_rom(PCIDevice *dev,
55
- for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) {
55
int *size, unsigned int domain,
56
- buf_rx[i + 2] = qtest_readl(qts,
56
unsigned int bus, unsigned int slot,
57
- can_base_addr + R_RX0_DATA1_OFFSET + 4 * i);
57
unsigned int function)
58
- }
58
@@ -XXX,XX +XXX,XX @@ void *pci_assign_dev_load_option_rom(PCIDevice *dev, struct Object *owner,
59
- } else {
59
uint8_t val;
60
- buf_rx[2] = qtest_readl(qts, can_base_addr + R_RX0_DATA1_OFFSET);
60
struct stat st;
61
- buf_rx[3] = qtest_readl(qts, can_base_addr + R_RX0_DATA2_OFFSET);
61
void *ptr = NULL;
62
+ for (int i = 0; i < frame_size - 2; i++) {
62
+ Object *owner = OBJECT(dev);
63
+ buf_rx[i + 2] = qtest_readl(qts,
63
64
+ can_base_addr + R_RX0_DATA1_OFFSET + 4 * i);
64
/* If loading ROM from file, pci handles it */
65
}
65
if (dev->romfile || !dev->rom_bar) {
66
66
@@ -XXX,XX +XXX,XX @@ void *pci_assign_dev_load_option_rom(PCIDevice *dev, struct Object *owner,
67
/* Clear the RX interrupt. */
67
fseek(fp, 0, SEEK_SET);
68
@@ -XXX,XX +XXX,XX @@ static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
68
69
g_assert_cmpint((buf_rx[size] & DLC_FD_BIT_MASK), ==,
69
snprintf(name, sizeof(name), "%s.rom", object_get_typename(owner));
70
(buf_tx[size] & DLC_FD_BIT_MASK));
70
- memory_region_init_ram_nomigrate(&dev->rom, owner, name, st.st_size, &error_abort);
71
} else {
71
- vmstate_register_ram(&dev->rom, &dev->qdev);
72
- if (!is_canfd_frame && size == 4) {
72
+ memory_region_init_ram(&dev->rom, owner, name, st.st_size, &error_abort);
73
- break;
73
ptr = memory_region_get_ram_ptr(&dev->rom);
74
- }
74
memset(ptr, 0xff, st.st_size);
75
-
75
76
g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
77
}
78
79
@@ -XXX,XX +XXX,XX @@ static void test_can_data_transfer(void)
80
write_data(qts, CANFD0_BASE_ADDR, buf_tx, false);
81
82
send_data(qts, CANFD0_BASE_ADDR);
83
- read_data(qts, CANFD1_BASE_ADDR, buf_rx);
84
+ read_data(qts, CANFD1_BASE_ADDR, buf_rx, CAN_FRAME_SIZE);
85
match_rx_tx_data(buf_tx, buf_rx, false);
86
87
qtest_quit(qts);
88
@@ -XXX,XX +XXX,XX @@ static void test_canfd_data_transfer(void)
89
write_data(qts, CANFD0_BASE_ADDR, buf_tx, true);
90
91
send_data(qts, CANFD0_BASE_ADDR);
92
- read_data(qts, CANFD1_BASE_ADDR, buf_rx);
93
+ read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
94
match_rx_tx_data(buf_tx, buf_rx, true);
95
96
qtest_quit(qts);
97
@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
98
write_data(qts, CANFD0_BASE_ADDR, buf_tx, true);
99
100
send_data(qts, CANFD0_BASE_ADDR);
101
- read_data(qts, CANFD0_BASE_ADDR, buf_rx);
102
+ read_data(qts, CANFD0_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
103
match_rx_tx_data(buf_tx, buf_rx, true);
104
105
generate_random_data(buf_tx, true);
106
@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
107
write_data(qts, CANFD1_BASE_ADDR, buf_tx, true);
108
109
send_data(qts, CANFD1_BASE_ADDR);
110
- read_data(qts, CANFD1_BASE_ADDR, buf_rx);
111
+ read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
112
match_rx_tx_data(buf_tx, buf_rx, true);
113
114
qtest_quit(qts);
115
--
76
--
116
2.34.1
77
2.17.1
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.