ppc: Improve multisocket support

[RFC PATCH 0/4] ppc: Improve multisocket support

Posted by Cédric Le Goater 9 months, 4 weeks ago

Hello,

Here are changes improving multisocket support of the XIVE models
(POWER9 only). When a source has an END target on another chip, the
XIVE IC will use an MMIO store to forward the notification to the
remote chip. The long term plan is to get rid of pnv_xive_get_remote()
whic is a modeling shortcut. I have had them for while, they compile,
they seem to still work but this is not for merge yet. If someone
could take over, that would be nice.

The best way to test is to start a 2 sockets * 1 cpu system with devices
attached to the PCI buses of chip 0 and to offline CPU 0. All sources
should be configured to be served by CPU 1 on socket 1 and trigger
notifications on chip 0 should be forwarded to chip 1.

Last patch adds support for degenerative interrupts. This is used by
the lowest level FW of POWER systems. Difficult to test.

Thanks,

C. 

Cédric Le Goater (4):
  ppc/xive: introduce a new XiveRouter end_notify() handler
  ppc/pnv: handle END triggers between chips with MMIOs
  ppc/pnv: add support for the PC MMIOs
  ppc/pnv: Add support for degenerative interrupts (POWER LSI)

 hw/intc/pnv_xive_regs.h   |   1 +
 include/hw/ppc/pnv_xive.h |  15 +++
 include/hw/ppc/xive.h     |   3 +
 hw/intc/pnv_xive.c        | 262 +++++++++++++++++++++++++++++++-------
 hw/intc/xive.c            |  50 ++++++--
 5 files changed, 278 insertions(+), 53 deletions(-)

-- 
2.41.0

Re: [RFC PATCH 0/4] ppc: Improve multisocket support

Posted by Frederic Barrat 9 months, 3 weeks ago


On 04/07/2023 15:49, Cédric Le Goater wrote:
> Hello,
> 
> Here are changes improving multisocket support of the XIVE models
> (POWER9 only). When a source has an END target on another chip, the
> XIVE IC will use an MMIO store to forward the notification to the
> remote chip. The long term plan is to get rid of pnv_xive_get_remote()
> whic is a modeling shortcut. I have had them for while, they compile,
> they seem to still work but this is not for merge yet. If someone
> could take over, that would be nice.
> 
> The best way to test is to start a 2 sockets * 1 cpu system with devices
> attached to the PCI buses of chip 0 and to offline CPU 0. All sources
> should be configured to be served by CPU 1 on socket 1 and trigger
> notifications on chip 0 should be forwarded to chip 1.
> 
> Last patch adds support for degenerative interrupts. This is used by
> the lowest level FW of POWER systems. Difficult to test.
> 


Thanks for the series! My crystal ball tells me the PC MMIO patch will 
come handy soon (to be adapted for P10 and groups). And the remote 
routing looks pretty interesting too.
The last patch (LSI) may rot a bit longer though :)

   Fred


> Thanks,
> 
> C.
> 
> Cédric Le Goater (4):
>    ppc/xive: introduce a new XiveRouter end_notify() handler
>    ppc/pnv: handle END triggers between chips with MMIOs
>    ppc/pnv: add support for the PC MMIOs
>    ppc/pnv: Add support for degenerative interrupts (POWER LSI)
> 
>   hw/intc/pnv_xive_regs.h   |   1 +
>   include/hw/ppc/pnv_xive.h |  15 +++
>   include/hw/ppc/xive.h     |   3 +
>   hw/intc/pnv_xive.c        | 262 +++++++++++++++++++++++++++++++-------
>   hw/intc/xive.c            |  50 ++++++--
>   5 files changed, 278 insertions(+), 53 deletions(-)
>

Re: [RFC PATCH 0/4] ppc: Improve multisocket support

Posted by Cédric Le Goater 9 months, 3 weeks ago

On 7/4/23 18:20, Frederic Barrat wrote:
> 
> 
> On 04/07/2023 15:49, Cédric Le Goater wrote:
>> Hello,
>>
>> Here are changes improving multisocket support of the XIVE models
>> (POWER9 only). When a source has an END target on another chip, the
>> XIVE IC will use an MMIO store to forward the notification to the
>> remote chip. The long term plan is to get rid of pnv_xive_get_remote()
>> whic is a modeling shortcut. I have had them for while, they compile,
>> they seem to still work but this is not for merge yet. If someone
>> could take over, that would be nice.
>>
>> The best way to test is to start a 2 sockets * 1 cpu system with devices
>> attached to the PCI buses of chip 0 and to offline CPU 0. All sources
>> should be configured to be served by CPU 1 on socket 1 and trigger
>> notifications on chip 0 should be forwarded to chip 1.
>>
>> Last patch adds support for degenerative interrupts. This is used by
>> the lowest level FW of POWER systems. Difficult to test.
>>
> 
> 
> Thanks for the series! My crystal ball tells me the PC MMIO patch will come handy soon (to be adapted for P10 and groups). And the remote routing looks pretty interesting too.

I am glad !

I think the first 2 patches are a good addition. They remove a
qdev_get_machine() call which is ugly. P10 has the same kind of
shortcut.

C.