Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
this warning doesn't trigger report the core thread state is 0.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/ppc/pnv_core.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 7fff2fd9e298..98356d7f6538 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = {
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
+#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3
+
static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
{
@@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
val = 0x0;
break;
+ case PNV9_XSCOM_EC_CORE_THREAD_STATE:
+ val = 0;
+ break;
default:
qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
addr);
@@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
* POWER10 Quads
*/
+#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412
+
static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
{
@@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
uint64_t val = -1;
switch (offset) {
+ case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE:
+ val = 0;
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
offset);
--
2.40.1
On Fri Jun 30, 2023 at 1:55 PM AEST, Joel Stanley wrote: > Firmware now warns if booting in LPAR per core mode (PPC bit 62). So > this warning doesn't trigger report the core thread state is 0. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > hw/ppc/pnv_core.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 7fff2fd9e298..98356d7f6538 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = { > #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d > #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a > > +#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 > + > static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, > unsigned int width) > { > @@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, > case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: > val = 0x0; > break; > + case PNV9_XSCOM_EC_CORE_THREAD_STATE: > + val = 0; > + break; > default: > qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > addr); > @@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { > * POWER10 Quads > */ > > +#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412 > + > static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > unsigned int width) > { > @@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > uint64_t val = -1; > > switch (offset) { > + case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE: > + val = 0; > + break; > default: > qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > offset); Yeah this is the problem, this is just addressing one core in the quad. AFAIKS P9 may have the same problem though so I don't blame the confusion. The other patches seem good because we'll want a P10 quad too I think. Thanks, Nick
On 6/30/23 05:55, Joel Stanley wrote: > Firmware now warns if booting in LPAR per core mode (PPC bit 62). So > this warning doesn't trigger report the core thread state is 0. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/ppc/pnv_core.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 7fff2fd9e298..98356d7f6538 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = { > #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d > #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a > > +#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 > + > static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, > unsigned int width) > { > @@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, > case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: > val = 0x0; > break; > + case PNV9_XSCOM_EC_CORE_THREAD_STATE: > + val = 0; > + break; > default: > qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > addr); > @@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { > * POWER10 Quads > */ > > +#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412 > + > static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > unsigned int width) > { > @@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > uint64_t val = -1; > > switch (offset) { > + case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE: > + val = 0; > + break; > default: > qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > offset);
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