Add a PnvQuad class for the P10 powernv machine. No xscoms are
implemented yet, but this allows them to be added.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c77fdb6747a4..5f25fe985ab2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
PnvQuad *eq = &chip10->quads[i];
pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
- PNV_QUAD_TYPE_NAME("power9"));
+ PNV_QUAD_TYPE_NAME("power10"));
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index b9a57463aec4..7fff2fd9e298 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+/*
+ * POWER10 Quads
+ */
+
+static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
+ unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+ uint64_t val = -1;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ offset);
+ }
+
+ return val;
+}
+
+static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ offset);
+ }
+}
+
+static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
+ .read = pnv_quad_power10_xscom_read,
+ .write = pnv_quad_power10_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
@@ -428,6 +469,13 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
}
+static void pnv_quad_power10_class_init(ObjectClass *oc, void *data)
+{
+ PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
+
+ pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
+}
+
static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -451,6 +499,11 @@ static const TypeInfo pnv_quad_infos[] = {
.name = PNV_QUAD_TYPE_NAME("power9"),
.class_init = pnv_quad_power9_class_init,
},
+ {
+ .parent = TYPE_PNV_QUAD,
+ .name = PNV_QUAD_TYPE_NAME("power10"),
+ .class_init = pnv_quad_power10_class_init,
+ },
};
DEFINE_TYPES(pnv_quad_infos);
--
2.40.1On 6/30/23 05:55, Joel Stanley wrote:
> Add a PnvQuad class for the P10 powernv machine. No xscoms are
> implemented yet, but this allows them to be added.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv.c | 2 +-
> hw/ppc/pnv_core.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index c77fdb6747a4..5f25fe985ab2 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> PnvQuad *eq = &chip10->quads[i];
>
> pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> - PNV_QUAD_TYPE_NAME("power9"));
> + PNV_QUAD_TYPE_NAME("power10"));
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index b9a57463aec4..7fff2fd9e298 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +/*
> + * POWER10 Quads
> + */
> +
> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> + uint64_t val = -1;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> + offset);
> + }
> +
> + return val;
> +}
> +
> +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> + offset);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
> + .read = pnv_quad_power10_xscom_read,
> + .write = pnv_quad_power10_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> static void pnv_quad_realize(DeviceState *dev, Error **errp)
> {
> PnvQuad *eq = PNV_QUAD(dev);
> @@ -428,6 +469,13 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
> pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
> }
>
> +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data)
> +{
> + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
> +
> + pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
> +}
> +
> static void pnv_quad_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -451,6 +499,11 @@ static const TypeInfo pnv_quad_infos[] = {
> .name = PNV_QUAD_TYPE_NAME("power9"),
> .class_init = pnv_quad_power9_class_init,
> },
> + {
> + .parent = TYPE_PNV_QUAD,
> + .name = PNV_QUAD_TYPE_NAME("power10"),
> + .class_init = pnv_quad_power10_class_init,
> + },
> };
>
> DEFINE_TYPES(pnv_quad_infos);
On 30/06/2023 05:55, Joel Stanley wrote:
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index b9a57463aec4..7fff2fd9e298 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
...
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
^^^ reading
I'm guessing we'll need to flush out that function pretty soon, so not
worth resending.
Fred
On Fri, 30 Jun 2023 at 07:30, Frederic Barrat <fbarrat@linux.ibm.com> wrote: > > > > On 30/06/2023 05:55, Joel Stanley wrote: > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > > index b9a57463aec4..7fff2fd9e298 100644 > > --- a/hw/ppc/pnv_core.c > > +++ b/hw/ppc/pnv_core.c > > > +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > ... > > + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > > ^^^ reading > > I'm guessing we'll need to flush out that function pretty soon, so not > worth resending. Thanks, good catch. It's incorrect in the p9 callback too. I had it fixed locally along with a re-wording to make it clear the message was for unimplemented operations, but decided not to send that.
On 6/30/23 09:35, Joel Stanley wrote: > On Fri, 30 Jun 2023 at 07:30, Frederic Barrat <fbarrat@linux.ibm.com> wrote: >> >> >> >> On 30/06/2023 05:55, Joel Stanley wrote: >>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c >>> index b9a57463aec4..7fff2fd9e298 100644 >>> --- a/hw/ppc/pnv_core.c >>> +++ b/hw/ppc/pnv_core.c >> >>> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, >> ... >>> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, >> >> ^^^ reading >> >> I'm guessing we'll need to flush out that function pretty soon, so not >> worth resending. > > Thanks, good catch. It's incorrect in the p9 callback too. > > I had it fixed locally along with a re-wording to make it clear the > message was for unimplemented operations, but decided not to send > that. There is still time for a v2 ! Please keep the R-b. Thanks, C.
On 6/30/23 04:44, Cédric Le Goater wrote: > On 6/30/23 09:35, Joel Stanley wrote: >> On Fri, 30 Jun 2023 at 07:30, Frederic Barrat <fbarrat@linux.ibm.com> wrote: >>> >>> >>> >>> On 30/06/2023 05:55, Joel Stanley wrote: >>>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c >>>> index b9a57463aec4..7fff2fd9e298 100644 >>>> --- a/hw/ppc/pnv_core.c >>>> +++ b/hw/ppc/pnv_core.c >>> >>>> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, >>> ... >>>> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, >>> >>> ^^^ reading >>> >>> I'm guessing we'll need to flush out that function pretty soon, so not >>> worth resending. >> >> Thanks, good catch. It's incorrect in the p9 callback too. >> >> I had it fixed locally along with a re-wording to make it clear the >> message was for unimplemented operations, but decided not to send >> that. > > > There is still time for a v2 ! Please keep the R-b. Since you're sending a v2 please fix the 80+ char line in patch 4 to make checkpatch.pl happy: -static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int width) +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int width) I'll not queue the series for now. Daniel > > Thanks, > > C. >
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