On 6/28/23 03:32, Philippe Mathieu-Daudé wrote:
> We only build for 32/64-bit hosts, so TCG is required for
> 128-bit targets.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d9a3684b3e..5762ff68b4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -476,6 +476,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
> #endif
> }
>
> +#ifdef CONFIG_TCG
> static void rv128_base_cpu_init(Object *obj)
> {
> if (qemu_tcg_mttcg_enabled()) {
> @@ -494,7 +495,10 @@ static void rv128_base_cpu_init(Object *obj)
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> #endif
> }
> -#else
> +#endif
> +
> +#else /* !TARGET_RISCV64 */
> +
> static void rv32_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -576,7 +580,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> cpu->cfg.ext_icsr = true;
> cpu->cfg.pmp = true;
> }
> -#endif
> +#endif /* !TARGET_RISCV64 */
>
> #if defined(CONFIG_KVM)
> static void riscv_host_cpu_init(Object *obj)
> @@ -1951,8 +1955,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
> +#ifdef CONFIG_TCG
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> -#endif
> +#endif /* CONFIG_TCG */
> +#endif /* TARGET_RISCV64 */
> };
>
> DEFINE_TYPES(riscv_cpu_type_infos)