[PULL 00/26] target-arm queue
[PULL v2 00/11] target-arm queue
1
Hi; here's a target-arm pullreq. Mostly this is RTH's FEAT_RME
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
series; there are also a handful of bug fixes including some
2
ethernet device failed 'make check' on big-endian hosts.
3
which aren't arm-specific but which it's convenient to include
4
here.
5
3
6
thanks
7
-- PMM
4
-- PMM
8
5
9
The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb:
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
10
7
11
Merge tag 'q800-for-8.1-pull-request' of https://github.com/vivier/qemu-m68k into staging (2023-06-22 10:18:32 +0200)
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
12
9
13
are available in the Git repository at:
10
are available in the Git repository at:
14
11
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230623
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
16
13
17
for you to fetch changes up to 497fad38979c16b6412388927401e577eba43d26:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
18
15
19
pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym (2023-06-23 11:46:02 +0100)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
20
17
21
----------------------------------------------------------------
18
----------------------------------------------------------------
22
target-arm queue:
19
target-arm queue:
23
* Add (experimental) support for FEAT_RME
20
* Correctly initialize MDCR_EL2.HPMN
24
* host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
21
* versal: Use nr_apu_cpus in favor of hard coding 2
25
* target/arm: Restructure has_vfp_d32 test
22
* accel/tcg: Add URL of clang bug to comment about our workaround
26
* hw/arm/sbsa-ref: add ITS support in SBSA GIC
23
* Add support for FEAT_DIT, Data Independent Timing
27
* target/arm: Fix sve predicate store, 8 <= VQ <= 15
24
* Remove GPIO from unimplemented NPCM7XX
28
* pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym
25
* Fix SCR RES1 handling
26
* Don't migrate CPUARMState.features
29
27
30
----------------------------------------------------------------
28
----------------------------------------------------------------
29
Aaron Lindsay (1):
30
target/arm: Don't migrate CPUARMState.features
31
32
Daniel Müller (1):
33
target/arm: Correctly initialize MDCR_EL2.HPMN
34
35
Edgar E. Iglesias (1):
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
37
38
Hao Wu (1):
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
40
41
Mike Nawrocki (1):
42
target/arm: Fix SCR RES1 handling
43
31
Peter Maydell (2):
44
Peter Maydell (2):
32
host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
45
arm: Update infocenter.arm.com URLs
33
pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym
46
accel/tcg: Add URL of clang bug to comment about our workaround
34
47
35
Richard Henderson (23):
48
Rebecca Cran (4):
36
target/arm: Add isar_feature_aa64_rme
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
37
target/arm: Update SCR and HCR for RME
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
38
target/arm: SCR_EL3.NS may be RES1
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
39
target/arm: Add RME cpregs
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
40
target/arm: Introduce ARMSecuritySpace
41
include/exec/memattrs: Add two bits of space to MemTxAttrs
42
target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx
43
target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}
44
target/arm: Remove __attribute__((nonnull)) from ptw.c
45
target/arm: Pipe ARMSecuritySpace through ptw.c
46
target/arm: NSTable is RES0 for the RME EL3 regime
47
target/arm: Handle Block and Page bits for security space
48
target/arm: Handle no-execute for Realm and Root regimes
49
target/arm: Use get_phys_addr_with_struct in S1_ptw_translate
50
target/arm: Move s1_is_el0 into S1Translate
51
target/arm: Use get_phys_addr_with_struct for stage2
52
target/arm: Add GPC syndrome
53
target/arm: Implement GPC exceptions
54
target/arm: Implement the granule protection check
55
target/arm: Add cpu properties for enabling FEAT_RME
56
docs/system/arm: Document FEAT_RME
57
target/arm: Restructure has_vfp_d32 test
58
target/arm: Fix sve predicate store, 8 <= VQ <= 15
59
53
60
Shashi Mallela (1):
54
include/hw/dma/pl080.h | 7 ++--
61
hw/arm/sbsa-ref: add ITS support in SBSA GIC
55
include/hw/misc/arm_integrator_debug.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
57
target/arm/cpu.h | 17 ++++++++
58
target/arm/internals.h | 6 +++
59
accel/tcg/cpu-exec.c | 25 +++++++++---
60
hw/arm/aspeed_ast2600.c | 2 +-
61
hw/arm/musca.c | 4 +-
62
hw/arm/npcm7xx.c | 8 ----
63
hw/arm/xlnx-versal.c | 4 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
65
hw/timer/arm_timer.c | 7 ++--
66
target/arm/cpu.c | 4 ++
67
target/arm/cpu64.c | 5 +++
68
target/arm/helper-a64.c | 27 +++++++++++--
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
70
target/arm/machine.c | 2 +-
71
target/arm/op_helper.c | 9 +----
72
target/arm/translate-a64.c | 12 ++++++
73
19 files changed, 164 insertions(+), 55 deletions(-)
62
74
63
docs/system/arm/cpu-features.rst | 23 ++
64
docs/system/arm/emulation.rst | 1 +
65
docs/system/arm/sbsa.rst | 14 +
66
include/exec/memattrs.h | 9 +-
67
include/qemu/compiler.h | 13 +
68
include/qemu/host-utils.h | 2 +-
69
target/arm/cpu.h | 151 ++++++++---
70
target/arm/internals.h | 27 ++
71
target/arm/syndrome.h | 10 +
72
hw/arm/sbsa-ref.c | 33 ++-
73
target/arm/cpu.c | 32 ++-
74
target/arm/helper.c | 162 ++++++++++-
75
target/arm/ptw.c | 570 +++++++++++++++++++++++++++++++--------
76
target/arm/tcg/cpu64.c | 53 ++++
77
target/arm/tcg/tlb_helper.c | 96 ++++++-
78
target/arm/tcg/translate-sve.c | 2 +-
79
pc-bios/keymaps/meson.build | 2 +-
80
17 files changed, 1034 insertions(+), 166 deletions(-)
diff view generated by jsdifflib
[PULL 01/26] target/arm: Add isar_feature_aa64_rme
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Add the missing field for ID_AA64PFR0, and the predicate.
4
Disable it if EL3 is forced off by the board or command-line.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230620124418.805717-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 6 ++++++
13
target/arm/cpu.c | 4 ++++
14
2 files changed, 10 insertions(+)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, SEL2, 36, 4)
21
FIELD(ID_AA64PFR0, MPAM, 40, 4)
22
FIELD(ID_AA64PFR0, AMU, 44, 4)
23
FIELD(ID_AA64PFR0, DIT, 48, 4)
24
+FIELD(ID_AA64PFR0, RME, 52, 4)
25
FIELD(ID_AA64PFR0, CSV2, 56, 4)
26
FIELD(ID_AA64PFR0, CSV3, 60, 4)
27
28
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
29
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
30
}
31
32
+static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
33
+{
34
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
35
+}
36
+
37
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
38
{
39
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
40
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu.c
43
+++ b/target/arm/cpu.c
44
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
45
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
46
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
47
ID_AA64PFR0, EL3, 0);
48
+
49
+ /* Disable the realm management extension, which requires EL3. */
50
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
51
+ ID_AA64PFR0, RME, 0);
52
}
53
54
if (!cpu->has_el2) {
55
--
56
2.34.1
57
58
diff view generated by jsdifflib
[PULL 02/26] target/arm: Update SCR and HCR for RME
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF
4
to be set, and invalidate TLBs when NSE changes.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 5 +++--
12
target/arm/helper.c | 10 ++++++++--
13
2 files changed, 11 insertions(+), 4 deletions(-)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
20
#define HCR_TERR (1ULL << 36)
21
#define HCR_TEA (1ULL << 37)
22
#define HCR_MIOCNCE (1ULL << 38)
23
-/* RES0 bit 39 */
24
+#define HCR_TME (1ULL << 39)
25
#define HCR_APK (1ULL << 40)
26
#define HCR_API (1ULL << 41)
27
#define HCR_NV (1ULL << 42)
28
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
29
#define HCR_NV2 (1ULL << 45)
30
#define HCR_FWB (1ULL << 46)
31
#define HCR_FIEN (1ULL << 47)
32
-/* RES0 bit 48 */
33
+#define HCR_GPF (1ULL << 48)
34
#define HCR_TID4 (1ULL << 49)
35
#define HCR_TICAB (1ULL << 50)
36
#define HCR_AMVOFFEN (1ULL << 51)
37
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
38
#define SCR_TRNDR (1ULL << 40)
39
#define SCR_ENTP2 (1ULL << 41)
40
#define SCR_GPF (1ULL << 48)
41
+#define SCR_NSE (1ULL << 62)
42
43
#define HSTR_TTEE (1 << 16)
44
#define HSTR_TJDBX (1 << 17)
45
diff --git a/target/arm/helper.c b/target/arm/helper.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/helper.c
48
+++ b/target/arm/helper.c
49
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
50
if (cpu_isar_feature(aa64_fgt, cpu)) {
51
valid_mask |= SCR_FGTEN;
52
}
53
+ if (cpu_isar_feature(aa64_rme, cpu)) {
54
+ valid_mask |= SCR_NSE | SCR_GPF;
55
+ }
56
} else {
57
valid_mask &= ~(SCR_RW | SCR_ST);
58
if (cpu_isar_feature(aa32_ras, cpu)) {
59
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
60
env->cp15.scr_el3 = value;
61
62
/*
63
- * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
64
+ * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
65
* we must invalidate all TLBs below EL3.
66
*/
67
- if (changed & SCR_NS) {
68
+ if (changed & (SCR_NS | SCR_NSE)) {
69
tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 |
70
ARMMMUIdxBit_E20_0 |
71
ARMMMUIdxBit_E10_1 |
72
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
73
if (cpu_isar_feature(aa64_fwb, cpu)) {
74
valid_mask |= HCR_FWB;
75
}
76
+ if (cpu_isar_feature(aa64_rme, cpu)) {
77
+ valid_mask |= HCR_GPF;
78
+ }
79
}
80
81
if (cpu_isar_feature(any_evt, cpu)) {
82
--
83
2.34.1
diff view generated by jsdifflib
[PULL 03/26] target/arm: SCR_EL3.NS may be RES1
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
With RME, SEL2 must also be present to support secure state.
4
The NS bit is RES1 if SEL2 is not present.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-4-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 3 +++
12
1 file changed, 3 insertions(+)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
19
}
20
if (cpu_isar_feature(aa64_sel2, cpu)) {
21
valid_mask |= SCR_EEL2;
22
+ } else if (cpu_isar_feature(aa64_rme, cpu)) {
23
+ /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
24
+ value |= SCR_NS;
25
}
26
if (cpu_isar_feature(aa64_mte, cpu)) {
27
valid_mask |= SCR_ATA;
28
--
29
2.34.1
diff view generated by jsdifflib
[PULL 04/26] target/arm: Add RME cpregs
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS,
4
RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-5-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 19 ++++++++++
12
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
13
2 files changed, 103 insertions(+)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
20
uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
21
uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
22
uint64_t fgt_exec[1]; /* HFGITR */
23
+
24
+ /* RME registers */
25
+ uint64_t gpccr_el3;
26
+ uint64_t gptbr_el3;
27
+ uint64_t mfar_el3;
28
} cp15;
29
30
struct {
31
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
32
uint64_t reset_cbar;
33
uint32_t reset_auxcr;
34
bool reset_hivecs;
35
+ uint8_t reset_l0gptsz;
36
37
/*
38
* Intermediate values used during property parsing.
39
@@ -XXX,XX +XXX,XX @@ FIELD(MVFR1, SIMDFMAC, 28, 4)
40
FIELD(MVFR2, SIMDMISC, 0, 4)
41
FIELD(MVFR2, FPMISC, 4, 4)
42
43
+FIELD(GPCCR, PPS, 0, 3)
44
+FIELD(GPCCR, IRGN, 8, 2)
45
+FIELD(GPCCR, ORGN, 10, 2)
46
+FIELD(GPCCR, SH, 12, 2)
47
+FIELD(GPCCR, PGS, 14, 2)
48
+FIELD(GPCCR, GPC, 16, 1)
49
+FIELD(GPCCR, GPCP, 17, 1)
50
+FIELD(GPCCR, L0GPTSZ, 20, 4)
51
+
52
+FIELD(MFAR, FPA, 12, 40)
53
+FIELD(MFAR, NSE, 62, 1)
54
+FIELD(MFAR, NS, 63, 1)
55
+
56
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
57
58
/* If adding a feature bit which corresponds to a Linux ELF
59
diff --git a/target/arm/helper.c b/target/arm/helper.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/helper.c
62
+++ b/target/arm/helper.c
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
64
.access = PL2_RW, .accessfn = access_esm,
65
.type = ARM_CP_CONST, .resetvalue = 0 },
66
};
67
+
68
+static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri,
69
+ uint64_t value)
70
+{
71
+ CPUState *cs = env_cpu(env);
72
+
73
+ tlb_flush(cs);
74
+}
75
+
76
+static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
77
+ uint64_t value)
78
+{
79
+ /* L0GPTSZ is RO; other bits not mentioned are RES0. */
80
+ uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK |
81
+ R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK |
82
+ R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK;
83
+
84
+ env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask);
85
+}
86
+
87
+static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
88
+{
89
+ env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ,
90
+ env_archcpu(env)->reset_l0gptsz);
91
+}
92
+
93
+static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri,
94
+ uint64_t value)
95
+{
96
+ CPUState *cs = env_cpu(env);
97
+
98
+ tlb_flush_all_cpus_synced(cs);
99
+}
100
+
101
+static const ARMCPRegInfo rme_reginfo[] = {
102
+ { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64,
103
+ .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
104
+ .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset,
105
+ .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) },
106
+ { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64,
107
+ .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4,
108
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },
109
+ { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64,
110
+ .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5,
111
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) },
112
+ { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64,
113
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4,
114
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
115
+ .writefn = tlbi_aa64_paall_write },
116
+ { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64,
117
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4,
118
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
119
+ .writefn = tlbi_aa64_paallos_write },
120
+ /*
121
+ * QEMU does not have a way to invalidate by physical address, thus
122
+ * invalidating a range of physical addresses is accomplished by
123
+ * flushing all tlb entries in the outer sharable domain,
124
+ * just like PAALLOS.
125
+ */
126
+ { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64,
127
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7,
128
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
129
+ .writefn = tlbi_aa64_paallos_write },
130
+ { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64,
131
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3,
132
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
133
+ .writefn = tlbi_aa64_paallos_write },
134
+ { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64,
135
+ .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1,
136
+ .access = PL3_W, .type = ARM_CP_NOP },
137
+};
138
+
139
+static const ARMCPRegInfo rme_mte_reginfo[] = {
140
+ { .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64,
141
+ .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5,
142
+ .access = PL3_W, .type = ARM_CP_NOP },
143
+};
144
#endif /* TARGET_AARCH64 */
145
146
static void define_pmu_regs(ARMCPU *cpu)
147
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
148
if (cpu_isar_feature(aa64_fgt, cpu)) {
149
define_arm_cp_regs(cpu, fgt_reginfo);
150
}
151
+
152
+ if (cpu_isar_feature(aa64_rme, cpu)) {
153
+ define_arm_cp_regs(cpu, rme_reginfo);
154
+ if (cpu_isar_feature(aa64_mte, cpu)) {
155
+ define_arm_cp_regs(cpu, rme_mte_reginfo);
156
+ }
157
+ }
158
#endif
159
160
if (cpu_isar_feature(any_predinv, cpu)) {
161
--
162
2.34.1
diff view generated by jsdifflib
[PULL 05/26] target/arm: Introduce ARMSecuritySpace
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Introduce both the enumeration and functions to retrieve
4
the current state, and state outside of EL3.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-6-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 89 ++++++++++++++++++++++++++++++++++-----------
12
target/arm/helper.c | 60 ++++++++++++++++++++++++++++++
13
2 files changed, 127 insertions(+), 22 deletions(-)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
20
21
void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
22
23
-#if !defined(CONFIG_USER_ONLY)
24
/*
25
+ * ARM v9 security states.
26
+ * The ordering of the enumeration corresponds to the low 2 bits
27
+ * of the GPI value, and (except for Root) the concat of NSE:NS.
28
+ */
29
+
30
+typedef enum ARMSecuritySpace {
31
+ ARMSS_Secure = 0,
32
+ ARMSS_NonSecure = 1,
33
+ ARMSS_Root = 2,
34
+ ARMSS_Realm = 3,
35
+} ARMSecuritySpace;
36
+
37
+/* Return true if @space is secure, in the pre-v9 sense. */
38
+static inline bool arm_space_is_secure(ARMSecuritySpace space)
39
+{
40
+ return space == ARMSS_Secure || space == ARMSS_Root;
41
+}
42
+
43
+/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
44
+static inline ARMSecuritySpace arm_secure_to_space(bool secure)
45
+{
46
+ return secure ? ARMSS_Secure : ARMSS_NonSecure;
47
+}
48
+
49
+#if !defined(CONFIG_USER_ONLY)
50
+/**
51
+ * arm_security_space_below_el3:
52
+ * @env: cpu context
53
+ *
54
+ * Return the security space of exception levels below EL3, following
55
+ * an exception return to those levels. Unlike arm_security_space,
56
+ * this doesn't care about the current EL.
57
+ */
58
+ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
59
+
60
+/**
61
+ * arm_is_secure_below_el3:
62
+ * @env: cpu context
63
+ *
64
* Return true if exception levels below EL3 are in secure state,
65
- * or would be following an exception return to that level.
66
- * Unlike arm_is_secure() (which is always a question about the
67
- * _current_ state of the CPU) this doesn't care about the current
68
- * EL or mode.
69
+ * or would be following an exception return to those levels.
70
*/
71
static inline bool arm_is_secure_below_el3(CPUARMState *env)
72
{
73
- assert(!arm_feature(env, ARM_FEATURE_M));
74
- if (arm_feature(env, ARM_FEATURE_EL3)) {
75
- return !(env->cp15.scr_el3 & SCR_NS);
76
- } else {
77
- /* If EL3 is not supported then the secure state is implementation
78
- * defined, in which case QEMU defaults to non-secure.
79
- */
80
- return false;
81
- }
82
+ ARMSecuritySpace ss = arm_security_space_below_el3(env);
83
+ return ss == ARMSS_Secure;
84
}
85
86
/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
87
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
88
return false;
89
}
90
91
-/* Return true if the processor is in secure state */
92
+/**
93
+ * arm_security_space:
94
+ * @env: cpu context
95
+ *
96
+ * Return the current security space of the cpu.
97
+ */
98
+ARMSecuritySpace arm_security_space(CPUARMState *env);
99
+
100
+/**
101
+ * arm_is_secure:
102
+ * @env: cpu context
103
+ *
104
+ * Return true if the processor is in secure state.
105
+ */
106
static inline bool arm_is_secure(CPUARMState *env)
107
{
108
- if (arm_feature(env, ARM_FEATURE_M)) {
109
- return env->v7m.secure;
110
- }
111
- if (arm_is_el3_or_mon(env)) {
112
- return true;
113
- }
114
- return arm_is_secure_below_el3(env);
115
+ return arm_space_is_secure(arm_security_space(env));
116
}
117
118
/*
119
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
120
}
121
122
#else
123
+static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
124
+{
125
+ return ARMSS_NonSecure;
126
+}
127
+
128
static inline bool arm_is_secure_below_el3(CPUARMState *env)
129
{
130
return false;
131
}
132
133
+static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
134
+{
135
+ return ARMSS_NonSecure;
136
+}
137
+
138
static inline bool arm_is_secure(CPUARMState *env)
139
{
140
return false;
141
diff --git a/target/arm/helper.c b/target/arm/helper.c
142
index XXXXXXX..XXXXXXX 100644
143
--- a/target/arm/helper.c
144
+++ b/target/arm/helper.c
145
@@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
146
}
147
}
148
#endif
149
+
150
+#ifndef CONFIG_USER_ONLY
151
+ARMSecuritySpace arm_security_space(CPUARMState *env)
152
+{
153
+ if (arm_feature(env, ARM_FEATURE_M)) {
154
+ return arm_secure_to_space(env->v7m.secure);
155
+ }
156
+
157
+ /*
158
+ * If EL3 is not supported then the secure state is implementation
159
+ * defined, in which case QEMU defaults to non-secure.
160
+ */
161
+ if (!arm_feature(env, ARM_FEATURE_EL3)) {
162
+ return ARMSS_NonSecure;
163
+ }
164
+
165
+ /* Check for AArch64 EL3 or AArch32 Mon. */
166
+ if (is_a64(env)) {
167
+ if (extract32(env->pstate, 2, 2) == 3) {
168
+ if (cpu_isar_feature(aa64_rme, env_archcpu(env))) {
169
+ return ARMSS_Root;
170
+ } else {
171
+ return ARMSS_Secure;
172
+ }
173
+ }
174
+ } else {
175
+ if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
176
+ return ARMSS_Secure;
177
+ }
178
+ }
179
+
180
+ return arm_security_space_below_el3(env);
181
+}
182
+
183
+ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
184
+{
185
+ assert(!arm_feature(env, ARM_FEATURE_M));
186
+
187
+ /*
188
+ * If EL3 is not supported then the secure state is implementation
189
+ * defined, in which case QEMU defaults to non-secure.
190
+ */
191
+ if (!arm_feature(env, ARM_FEATURE_EL3)) {
192
+ return ARMSS_NonSecure;
193
+ }
194
+
195
+ /*
196
+ * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
197
+ * Ignoring NSE when !NS retains consistency without having to
198
+ * modify other predicates.
199
+ */
200
+ if (!(env->cp15.scr_el3 & SCR_NS)) {
201
+ return ARMSS_Secure;
202
+ } else if (env->cp15.scr_el3 & SCR_NSE) {
203
+ return ARMSS_Realm;
204
+ } else {
205
+ return ARMSS_NonSecure;
206
+ }
207
+}
208
+#endif /* !CONFIG_USER_ONLY */
209
--
210
2.34.1
diff view generated by jsdifflib
[PULL 06/26] include/exec/memattrs: Add two bits of space to MemTxAttrs
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We will need 2 bits to represent ARMSecurityState.
4
5
Do not attempt to replace or widen secure, even though it
6
logically overlaps the new field -- there are uses within
7
e.g. hw/block/pflash_cfi01.c, which don't know anything
8
specific about ARM.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20230620124418.805717-7-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/exec/memattrs.h | 9 ++++++++-
16
1 file changed, 8 insertions(+), 1 deletion(-)
17
18
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/exec/memattrs.h
21
+++ b/include/exec/memattrs.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct MemTxAttrs {
23
* "didn't specify" if necessary.
24
*/
25
unsigned int unspecified:1;
26
- /* ARM/AMBA: TrustZone Secure access
27
+ /*
28
+ * ARM/AMBA: TrustZone Secure access
29
* x86: System Management Mode access
30
*/
31
unsigned int secure:1;
32
+ /*
33
+ * ARM: ArmSecuritySpace. This partially overlaps secure, but it is
34
+ * easier to have both fields to assist code that does not understand
35
+ * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash).
36
+ */
37
+ unsigned int space:2;
38
/* Memory access is usermode (unprivileged) */
39
unsigned int user:1;
40
/*
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 07/26] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
It will be helpful to have ARMMMUIdx_Phys_* to be in the same
4
relative order as ARMSecuritySpace enumerators. This requires
5
the adjustment to the nstable check. While there, check for being
6
in secure state rather than rely on clearing the low bit making
7
no change to non-secure state.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230620124418.805717-8-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 12 ++++++------
15
target/arm/ptw.c | 12 +++++-------
16
2 files changed, 11 insertions(+), 13 deletions(-)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
23
ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
24
ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
25
26
- /* TLBs with 1-1 mapping to the physical address spaces. */
27
- ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A,
28
- ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A,
29
-
30
/*
31
* Used for second stage of an S12 page table walk, or for descriptor
32
* loads during first stage of an S1 page table walk. Note that both
33
* are in use simultaneously for SecureEL2: the security state for
34
* the S2 ptw is selected by the NS bit from the S1 ptw.
35
*/
36
- ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A,
37
- ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A,
38
+ ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A,
39
+ ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A,
40
+
41
+ /* TLBs with 1-1 mapping to the physical address spaces. */
42
+ ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
43
+ ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
44
45
/*
46
* These are not allocated TLBs and are used only for AT system
47
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/ptw.c
50
+++ b/target/arm/ptw.c
51
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
52
descaddr |= (address >> (stride * (4 - level))) & indexmask;
53
descaddr &= ~7ULL;
54
nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1);
55
- if (nstable) {
56
+ if (nstable && ptw->in_secure) {
57
/*
58
* Stage2_S -> Stage2 or Phys_S -> Phys_NS
59
- * Assert that the non-secure idx are even, and relative order.
60
+ * Assert the relative order of the secure/non-secure indexes.
61
*/
62
- QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) != 0);
63
- QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) != 0);
64
- QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 != ARMMMUIdx_Phys_S);
65
- QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 != ARMMMUIdx_Stage2_S);
66
- ptw->in_ptw_idx &= ~1;
67
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS);
68
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2);
69
+ ptw->in_ptw_idx += 1;
70
ptw->in_secure = false;
71
}
72
if (!S1_ptw_translate(env, ptw, descaddr, fi)) {
73
--
74
2.34.1
diff view generated by jsdifflib
[PULL 08/26] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
With FEAT_RME, there are four physical address spaces.
4
For now, just define the symbols, and mention them in
5
the same spots as the other Phys indexes in ptw.c.
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230620124418.805717-9-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.h | 23 +++++++++++++++++++++--
14
target/arm/ptw.c | 10 ++++++++--
15
2 files changed, 29 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
22
ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A,
23
24
/* TLBs with 1-1 mapping to the physical address spaces. */
25
- ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
26
- ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
27
+ ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
28
+ ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
29
+ ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A,
30
+ ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A,
31
32
/*
33
* These are not allocated TLBs and are used only for AT system
34
@@ -XXX,XX +XXX,XX @@ typedef enum ARMASIdx {
35
ARMASIdx_TagS = 3,
36
} ARMASIdx;
37
38
+static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
39
+{
40
+ /* Assert the relative order of the physical mmu indexes. */
41
+ QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
42
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
43
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
44
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
45
+
46
+ return ARMMMUIdx_Phys_S + space;
47
+}
48
+
49
+static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
50
+{
51
+ assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
52
+ return idx - ARMMMUIdx_Phys_S;
53
+}
54
+
55
static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
56
{
57
/* If all the CLIDR.Ctypem bits are 0 there are no caches, and
58
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/ptw.c
61
+++ b/target/arm/ptw.c
62
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
63
case ARMMMUIdx_E3:
64
break;
65
66
- case ARMMMUIdx_Phys_NS:
67
case ARMMMUIdx_Phys_S:
68
+ case ARMMMUIdx_Phys_NS:
69
+ case ARMMMUIdx_Phys_Root:
70
+ case ARMMMUIdx_Phys_Realm:
71
/* No translation for physical address spaces. */
72
return true;
73
74
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
75
switch (mmu_idx) {
76
case ARMMMUIdx_Stage2:
77
case ARMMMUIdx_Stage2_S:
78
- case ARMMMUIdx_Phys_NS:
79
case ARMMMUIdx_Phys_S:
80
+ case ARMMMUIdx_Phys_NS:
81
+ case ARMMMUIdx_Phys_Root:
82
+ case ARMMMUIdx_Phys_Realm:
83
break;
84
85
default:
86
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
87
switch (mmu_idx) {
88
case ARMMMUIdx_Phys_S:
89
case ARMMMUIdx_Phys_NS:
90
+ case ARMMMUIdx_Phys_Root:
91
+ case ARMMMUIdx_Phys_Realm:
92
/* Checking Phys early avoids special casing later vs regime_el. */
93
return get_phys_addr_disabled(env, address, access_type, mmu_idx,
94
is_secure, result, fi);
95
--
96
2.34.1
97
98
diff view generated by jsdifflib
[PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This was added in 7e98e21c098 as part of a reorg in which
4
one of the argument had been legally NULL, and this caught
5
actual instances. Now that the reorg is complete, this
6
serves little purpose.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230620124418.805717-10-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/ptw.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/ptw.c
20
+++ b/target/arm/ptw.c
21
@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
22
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
23
uint64_t address,
24
MMUAccessType access_type, bool s1_is_el0,
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
26
- __attribute__((nonnull));
27
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi);
28
29
static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
30
target_ulong address,
31
MMUAccessType access_type,
32
GetPhysAddrResult *result,
33
- ARMMMUFaultInfo *fi)
34
- __attribute__((nonnull));
35
+ ARMMMUFaultInfo *fi);
36
37
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
38
static const uint8_t pamax_map[] = {
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
[PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Add input and output space members to S1Translate. Set and adjust
4
them in S1_ptw_translate, and the various points at which we drop
5
secure state. Initialize the space in get_phys_addr; for now leave
6
get_phys_addr_with_secure considering only secure vs non-secure spaces.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230620124418.805717-11-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/ptw.c | 86 +++++++++++++++++++++++++++++++++++++++---------
14
1 file changed, 71 insertions(+), 15 deletions(-)
15
16
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/ptw.c
19
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@
21
typedef struct S1Translate {
22
ARMMMUIdx in_mmu_idx;
23
ARMMMUIdx in_ptw_idx;
24
+ ARMSecuritySpace in_space;
25
bool in_secure;
26
bool in_debug;
27
bool out_secure;
28
bool out_rw;
29
bool out_be;
30
+ ARMSecuritySpace out_space;
31
hwaddr out_virt;
32
hwaddr out_phys;
33
void *out_host;
34
@@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
35
static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
36
hwaddr addr, ARMMMUFaultInfo *fi)
37
{
38
+ ARMSecuritySpace space = ptw->in_space;
39
bool is_secure = ptw->in_secure;
40
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
41
ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
42
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
43
.in_mmu_idx = s2_mmu_idx,
44
.in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
45
.in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
46
+ .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
47
+ : space == ARMSS_Realm ? ARMSS_Realm
48
+ : ARMSS_NonSecure),
49
.in_debug = true,
50
};
51
GetPhysAddrResult s2 = { };
52
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
53
ptw->out_phys = s2.f.phys_addr;
54
pte_attrs = s2.cacheattrs.attrs;
55
ptw->out_secure = s2.f.attrs.secure;
56
+ ptw->out_space = s2.f.attrs.space;
57
} else {
58
/* Regime is physical. */
59
ptw->out_phys = addr;
60
pte_attrs = 0;
61
ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S;
62
+ ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure
63
+ : space == ARMSS_Realm ? ARMSS_Realm
64
+ : ARMSS_NonSecure);
65
}
66
ptw->out_host = NULL;
67
ptw->out_rw = false;
68
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
69
ptw->out_rw = full->prot & PAGE_WRITE;
70
pte_attrs = full->pte_attrs;
71
ptw->out_secure = full->attrs.secure;
72
+ ptw->out_space = full->attrs.space;
73
#else
74
g_assert_not_reached();
75
#endif
76
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw,
77
}
78
} else {
79
/* Page tables are in MMIO. */
80
- MemTxAttrs attrs = { .secure = ptw->out_secure };
81
+ MemTxAttrs attrs = {
82
+ .secure = ptw->out_secure,
83
+ .space = ptw->out_space,
84
+ };
85
AddressSpace *as = arm_addressspace(cs, attrs);
86
MemTxResult result = MEMTX_OK;
87
88
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw,
89
#endif
90
} else {
91
/* Page tables are in MMIO. */
92
- MemTxAttrs attrs = { .secure = ptw->out_secure };
93
+ MemTxAttrs attrs = {
94
+ .secure = ptw->out_secure,
95
+ .space = ptw->out_space,
96
+ };
97
AddressSpace *as = arm_addressspace(cs, attrs);
98
MemTxResult result = MEMTX_OK;
99
100
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
101
* regime, because the attribute will already be non-secure.
102
*/
103
result->f.attrs.secure = false;
104
+ result->f.attrs.space = ARMSS_NonSecure;
105
}
106
result->f.phys_addr = phys_addr;
107
return false;
108
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
109
* regime, because the attribute will already be non-secure.
110
*/
111
result->f.attrs.secure = false;
112
+ result->f.attrs.space = ARMSS_NonSecure;
113
}
114
115
if (regime_is_stage2(mmu_idx)) {
116
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
117
*/
118
if (sattrs.ns) {
119
result->f.attrs.secure = false;
120
+ result->f.attrs.space = ARMSS_NonSecure;
121
} else if (!secure) {
122
/*
123
* NS access to S memory must fault.
124
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
125
bool is_secure = ptw->in_secure;
126
bool ret, ipa_secure;
127
ARMCacheAttrs cacheattrs1;
128
+ ARMSecuritySpace ipa_space;
129
bool is_el0;
130
uint64_t hcr;
131
132
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
133
134
ipa = result->f.phys_addr;
135
ipa_secure = result->f.attrs.secure;
136
+ ipa_space = result->f.attrs.space;
137
138
is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
139
ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
140
ptw->in_secure = ipa_secure;
141
+ ptw->in_space = ipa_space;
142
ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx);
143
144
/*
145
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
146
ARMMMUIdx s1_mmu_idx;
147
148
/*
149
- * The page table entries may downgrade secure to non-secure, but
150
- * cannot upgrade an non-secure translation regime's attributes
151
- * to secure.
152
+ * The page table entries may downgrade Secure to NonSecure, but
153
+ * cannot upgrade a NonSecure translation regime's attributes
154
+ * to Secure or Realm.
155
*/
156
result->f.attrs.secure = is_secure;
157
+ result->f.attrs.space = ptw->in_space;
158
159
switch (mmu_idx) {
160
case ARMMMUIdx_Phys_S:
161
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
162
163
default:
164
/* Single stage uses physical for ptw. */
165
- ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
166
+ ptw->in_ptw_idx = arm_space_to_phys(ptw->in_space);
167
break;
168
}
169
170
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
171
S1Translate ptw = {
172
.in_mmu_idx = mmu_idx,
173
.in_secure = is_secure,
174
+ .in_space = arm_secure_to_space(is_secure),
175
};
176
return get_phys_addr_with_struct(env, &ptw, address, access_type,
177
result, fi);
178
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
179
MMUAccessType access_type, ARMMMUIdx mmu_idx,
180
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
181
{
182
- bool is_secure;
183
+ S1Translate ptw = {
184
+ .in_mmu_idx = mmu_idx,
185
+ };
186
+ ARMSecuritySpace ss;
187
188
switch (mmu_idx) {
189
case ARMMMUIdx_E10_0:
190
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
191
case ARMMMUIdx_Stage1_E1:
192
case ARMMMUIdx_Stage1_E1_PAN:
193
case ARMMMUIdx_E2:
194
- is_secure = arm_is_secure_below_el3(env);
195
+ ss = arm_security_space_below_el3(env);
196
break;
197
case ARMMMUIdx_Stage2:
198
+ /*
199
+ * For Secure EL2, we need this index to be NonSecure;
200
+ * otherwise this will already be NonSecure or Realm.
201
+ */
202
+ ss = arm_security_space_below_el3(env);
203
+ if (ss == ARMSS_Secure) {
204
+ ss = ARMSS_NonSecure;
205
+ }
206
+ break;
207
case ARMMMUIdx_Phys_NS:
208
case ARMMMUIdx_MPrivNegPri:
209
case ARMMMUIdx_MUserNegPri:
210
case ARMMMUIdx_MPriv:
211
case ARMMMUIdx_MUser:
212
- is_secure = false;
213
+ ss = ARMSS_NonSecure;
214
break;
215
- case ARMMMUIdx_E3:
216
case ARMMMUIdx_Stage2_S:
217
case ARMMMUIdx_Phys_S:
218
case ARMMMUIdx_MSPrivNegPri:
219
case ARMMMUIdx_MSUserNegPri:
220
case ARMMMUIdx_MSPriv:
221
case ARMMMUIdx_MSUser:
222
- is_secure = true;
223
+ ss = ARMSS_Secure;
224
+ break;
225
+ case ARMMMUIdx_E3:
226
+ if (arm_feature(env, ARM_FEATURE_AARCH64) &&
227
+ cpu_isar_feature(aa64_rme, env_archcpu(env))) {
228
+ ss = ARMSS_Root;
229
+ } else {
230
+ ss = ARMSS_Secure;
231
+ }
232
+ break;
233
+ case ARMMMUIdx_Phys_Root:
234
+ ss = ARMSS_Root;
235
+ break;
236
+ case ARMMMUIdx_Phys_Realm:
237
+ ss = ARMSS_Realm;
238
break;
239
default:
240
g_assert_not_reached();
241
}
242
- return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
243
- is_secure, result, fi);
244
+
245
+ ptw.in_space = ss;
246
+ ptw.in_secure = arm_space_is_secure(ss);
247
+ return get_phys_addr_with_struct(env, &ptw, address, access_type,
248
+ result, fi);
249
}
250
251
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
252
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
253
{
254
ARMCPU *cpu = ARM_CPU(cs);
255
CPUARMState *env = &cpu->env;
256
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
257
+ ARMSecuritySpace ss = arm_security_space(env);
258
S1Translate ptw = {
259
- .in_mmu_idx = arm_mmu_idx(env),
260
- .in_secure = arm_is_secure(env),
261
+ .in_mmu_idx = mmu_idx,
262
+ .in_space = ss,
263
+ .in_secure = arm_space_is_secure(ss),
264
.in_debug = true,
265
};
266
GetPhysAddrResult res = {};
267
--
268
2.34.1
diff view generated by jsdifflib
[PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Test in_space instead of in_secure so that we don't
4
switch out of Root space.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-12-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 28 ++++++++++++++--------------
12
1 file changed, 14 insertions(+), 14 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
19
{
20
ARMCPU *cpu = env_archcpu(env);
21
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
22
- bool is_secure = ptw->in_secure;
23
int32_t level;
24
ARMVAParameters param;
25
uint64_t ttbr;
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
27
uint64_t descaddrmask;
28
bool aarch64 = arm_el_is_aa64(env, el);
29
uint64_t descriptor, new_descriptor;
30
- bool nstable;
31
32
/* TODO: This code does not support shareability levels. */
33
if (aarch64) {
34
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
35
descaddrmask = MAKE_64BIT_MASK(0, 40);
36
}
37
descaddrmask &= ~indexmask_grainsize;
38
-
39
- /*
40
- * Secure stage 1 accesses start with the page table in secure memory and
41
- * can be downgraded to non-secure at any step. Non-secure accesses
42
- * remain non-secure. We implement this by just ORing in the NSTable/NS
43
- * bits at each step.
44
- * Stage 2 never gets this kind of downgrade.
45
- */
46
- tableattrs = is_secure ? 0 : (1 << 4);
47
+ tableattrs = 0;
48
49
next_level:
50
descaddr |= (address >> (stride * (4 - level))) & indexmask;
51
descaddr &= ~7ULL;
52
- nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1);
53
- if (nstable && ptw->in_secure) {
54
+
55
+ /*
56
+ * Process the NSTable bit from the previous level. This changes
57
+ * the table address space and the output space from Secure to
58
+ * NonSecure. With RME, the EL3 translation regime does not change
59
+ * from Root to NonSecure.
60
+ */
61
+ if (ptw->in_space == ARMSS_Secure
62
+ && !regime_is_stage2(mmu_idx)
63
+ && extract32(tableattrs, 4, 1)) {
64
/*
65
* Stage2_S -> Stage2 or Phys_S -> Phys_NS
66
* Assert the relative order of the secure/non-secure indexes.
67
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
68
QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2);
69
ptw->in_ptw_idx += 1;
70
ptw->in_secure = false;
71
+ ptw->in_space = ARMSS_NonSecure;
72
}
73
+
74
if (!S1_ptw_translate(env, ptw, descaddr, fi)) {
75
goto do_fault;
76
}
77
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
78
*/
79
attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
80
if (!regime_is_stage2(mmu_idx)) {
81
- attrs |= nstable << 5; /* NS */
82
+ attrs |= !ptw->in_secure << 5; /* NS */
83
if (!param.hpd) {
84
attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */
85
/*
86
--
87
2.34.1
diff view generated by jsdifflib
[PULL 12/26] target/arm: Handle Block and Page bits for security space
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
With Realm security state, bit 55 of a block or page descriptor during
4
the stage2 walk becomes the NS bit; during the stage1 walk the bit 5
5
NS bit is RES0. With Root security state, bit 11 of the block or page
6
descriptor during the stage1 walk becomes the NSE bit.
7
8
Rather than collecting an NS bit and applying it later, compute the
9
output pa space from the input pa space and unconditionally assign.
10
This means that we no longer need to adjust the output space earlier
11
for the NSTable bit.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230620124418.805717-13-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/ptw.c | 89 +++++++++++++++++++++++++++++++++++++++---------
19
1 file changed, 73 insertions(+), 16 deletions(-)
20
21
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/ptw.c
24
+++ b/target/arm/ptw.c
25
@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
26
* @mmu_idx: MMU index indicating required translation regime
27
* @is_aa64: TRUE if AArch64
28
* @ap: The 2-bit simple AP (AP[2:1])
29
- * @ns: NS (non-secure) bit
30
* @xn: XN (execute-never) bit
31
* @pxn: PXN (privileged execute-never) bit
32
+ * @in_pa: The original input pa space
33
+ * @out_pa: The output pa space, modified by NSTable, NS, and NSE
34
*/
35
static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
36
- int ap, int ns, int xn, int pxn)
37
+ int ap, int xn, int pxn,
38
+ ARMSecuritySpace in_pa, ARMSecuritySpace out_pa)
39
{
40
ARMCPU *cpu = env_archcpu(env);
41
bool is_user = regime_is_user(env, mmu_idx);
42
@@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
43
}
44
}
45
46
- if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
47
+ if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure &&
48
+ (env->cp15.scr_el3 & SCR_SIF)) {
49
return prot_rw;
50
}
51
52
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
53
int32_t stride;
54
int addrsize, inputsize, outputsize;
55
uint64_t tcr = regime_tcr(env, mmu_idx);
56
- int ap, ns, xn, pxn;
57
+ int ap, xn, pxn;
58
uint32_t el = regime_el(env, mmu_idx);
59
uint64_t descaddrmask;
60
bool aarch64 = arm_el_is_aa64(env, el);
61
uint64_t descriptor, new_descriptor;
62
+ ARMSecuritySpace out_space;
63
64
/* TODO: This code does not support shareability levels. */
65
if (aarch64) {
66
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
67
}
68
69
ap = extract32(attrs, 6, 2);
70
+ out_space = ptw->in_space;
71
if (regime_is_stage2(mmu_idx)) {
72
- ns = mmu_idx == ARMMMUIdx_Stage2;
73
+ /*
74
+ * R_GYNXY: For stage2 in Realm security state, bit 55 is NS.
75
+ * The bit remains ignored for other security states.
76
+ */
77
+ if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) {
78
+ out_space = ARMSS_NonSecure;
79
+ }
80
xn = extract64(attrs, 53, 2);
81
result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
82
} else {
83
- ns = extract32(attrs, 5, 1);
84
+ int nse, ns = extract32(attrs, 5, 1);
85
+ switch (out_space) {
86
+ case ARMSS_Root:
87
+ /*
88
+ * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime.
89
+ * R_XTYPW: NSE and NS together select the output pa space.
90
+ */
91
+ nse = extract32(attrs, 11, 1);
92
+ out_space = (nse << 1) | ns;
93
+ if (out_space == ARMSS_Secure &&
94
+ !cpu_isar_feature(aa64_sel2, cpu)) {
95
+ out_space = ARMSS_NonSecure;
96
+ }
97
+ break;
98
+ case ARMSS_Secure:
99
+ if (ns) {
100
+ out_space = ARMSS_NonSecure;
101
+ }
102
+ break;
103
+ case ARMSS_Realm:
104
+ switch (mmu_idx) {
105
+ case ARMMMUIdx_Stage1_E0:
106
+ case ARMMMUIdx_Stage1_E1:
107
+ case ARMMMUIdx_Stage1_E1_PAN:
108
+ /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */
109
+ break;
110
+ case ARMMMUIdx_E2:
111
+ case ARMMMUIdx_E20_0:
112
+ case ARMMMUIdx_E20_2:
113
+ case ARMMMUIdx_E20_2_PAN:
114
+ /*
115
+ * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1,
116
+ * NS changes the output to non-secure space.
117
+ */
118
+ if (ns) {
119
+ out_space = ARMSS_NonSecure;
120
+ }
121
+ break;
122
+ default:
123
+ g_assert_not_reached();
124
+ }
125
+ break;
126
+ case ARMSS_NonSecure:
127
+ /* R_QRMFF: For NonSecure state, the NS bit is RES0. */
128
+ break;
129
+ default:
130
+ g_assert_not_reached();
131
+ }
132
xn = extract64(attrs, 54, 1);
133
pxn = extract64(attrs, 53, 1);
134
- result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
135
+
136
+ /*
137
+ * Note that we modified ptw->in_space earlier for NSTable, but
138
+ * result->f.attrs retains a copy of the original security space.
139
+ */
140
+ result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn,
141
+ result->f.attrs.space, out_space);
142
}
143
144
if (!(result->f.prot & (1 << access_type))) {
145
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
146
}
147
}
148
149
- if (ns) {
150
- /*
151
- * The NS bit will (as required by the architecture) have no effect if
152
- * the CPU doesn't support TZ or this is a non-secure translation
153
- * regime, because the attribute will already be non-secure.
154
- */
155
- result->f.attrs.secure = false;
156
- result->f.attrs.space = ARMSS_NonSecure;
157
- }
158
+ result->f.attrs.space = out_space;
159
+ result->f.attrs.secure = arm_space_is_secure(out_space);
160
161
if (regime_is_stage2(mmu_idx)) {
162
result->cacheattrs.is_s2_format = true;
163
--
164
2.34.1
diff view generated by jsdifflib
[PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
While Root and Realm may read and write data from other spaces,
4
neither may execute from other pa spaces.
5
6
This happens for Stage1 EL3, EL2, EL2&0, and Stage2 EL1&0.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230620124418.805717-14-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/ptw.c | 52 ++++++++++++++++++++++++++++++++++++++++++------
14
1 file changed, 46 insertions(+), 6 deletions(-)
15
16
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/ptw.c
19
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ do_fault:
21
* @xn: XN (execute-never) bits
22
* @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
23
*/
24
-static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
25
+static int get_S2prot_noexecute(int s2ap)
26
{
27
int prot = 0;
28
29
@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
30
if (s2ap & 2) {
31
prot |= PAGE_WRITE;
32
}
33
+ return prot;
34
+}
35
+
36
+static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
37
+{
38
+ int prot = get_S2prot_noexecute(s2ap);
39
40
if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
41
switch (xn) {
42
@@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
43
}
44
}
45
46
- if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure &&
47
- (env->cp15.scr_el3 & SCR_SIF)) {
48
- return prot_rw;
49
+ if (in_pa != out_pa) {
50
+ switch (in_pa) {
51
+ case ARMSS_Root:
52
+ /*
53
+ * R_ZWRVD: permission fault for insn fetched from non-Root,
54
+ * I_WWBFB: SIF has no effect in EL3.
55
+ */
56
+ return prot_rw;
57
+ case ARMSS_Realm:
58
+ /*
59
+ * R_PKTDS: permission fault for insn fetched from non-Realm,
60
+ * for Realm EL2 or EL2&0. The corresponding fault for EL1&0
61
+ * happens during any stage2 translation.
62
+ */
63
+ switch (mmu_idx) {
64
+ case ARMMMUIdx_E2:
65
+ case ARMMMUIdx_E20_0:
66
+ case ARMMMUIdx_E20_2:
67
+ case ARMMMUIdx_E20_2_PAN:
68
+ return prot_rw;
69
+ default:
70
+ break;
71
+ }
72
+ break;
73
+ case ARMSS_Secure:
74
+ if (env->cp15.scr_el3 & SCR_SIF) {
75
+ return prot_rw;
76
+ }
77
+ break;
78
+ default:
79
+ /* Input NonSecure must have output NonSecure. */
80
+ g_assert_not_reached();
81
+ }
82
}
83
84
/* TODO have_wxn should be replaced with
85
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
86
/*
87
* R_GYNXY: For stage2 in Realm security state, bit 55 is NS.
88
* The bit remains ignored for other security states.
89
+ * R_YMCSL: Executing an insn fetched from non-Realm causes
90
+ * a stage2 permission fault.
91
*/
92
if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) {
93
out_space = ARMSS_NonSecure;
94
+ result->f.prot = get_S2prot_noexecute(ap);
95
+ } else {
96
+ xn = extract64(attrs, 53, 2);
97
+ result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
98
}
99
- xn = extract64(attrs, 53, 2);
100
- result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
101
} else {
102
int nse, ns = extract32(attrs, 5, 1);
103
switch (out_space) {
104
--
105
2.34.1
diff view generated by jsdifflib
[PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Do not provide a fast-path for physical addresses,
4
as those will need to be validated for GPC.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-15-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 44 +++++++++++++++++---------------------------
12
1 file changed, 17 insertions(+), 27 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
19
* From gdbstub, do not use softmmu so that we don't modify the
20
* state of the cpu at all, including softmmu tlb contents.
21
*/
22
- if (regime_is_stage2(s2_mmu_idx)) {
23
- S1Translate s2ptw = {
24
- .in_mmu_idx = s2_mmu_idx,
25
- .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
26
- .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
27
- .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
28
- : space == ARMSS_Realm ? ARMSS_Realm
29
- : ARMSS_NonSecure),
30
- .in_debug = true,
31
- };
32
- GetPhysAddrResult s2 = { };
33
+ S1Translate s2ptw = {
34
+ .in_mmu_idx = s2_mmu_idx,
35
+ .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
36
+ .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
37
+ .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
38
+ : space == ARMSS_Realm ? ARMSS_Realm
39
+ : ARMSS_NonSecure),
40
+ .in_debug = true,
41
+ };
42
+ GetPhysAddrResult s2 = { };
43
44
- if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
45
- false, &s2, fi)) {
46
- goto fail;
47
- }
48
- ptw->out_phys = s2.f.phys_addr;
49
- pte_attrs = s2.cacheattrs.attrs;
50
- ptw->out_secure = s2.f.attrs.secure;
51
- ptw->out_space = s2.f.attrs.space;
52
- } else {
53
- /* Regime is physical. */
54
- ptw->out_phys = addr;
55
- pte_attrs = 0;
56
- ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S;
57
- ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure
58
- : space == ARMSS_Realm ? ARMSS_Realm
59
- : ARMSS_NonSecure);
60
+ if (get_phys_addr_with_struct(env, &s2ptw, addr,
61
+ MMU_DATA_LOAD, &s2, fi)) {
62
+ goto fail;
63
}
64
+ ptw->out_phys = s2.f.phys_addr;
65
+ pte_attrs = s2.cacheattrs.attrs;
66
ptw->out_host = NULL;
67
ptw->out_rw = false;
68
+ ptw->out_secure = s2.f.attrs.secure;
69
+ ptw->out_space = s2.f.attrs.space;
70
} else {
71
#ifdef CONFIG_TCG
72
CPUTLBEntryFull *full;
73
--
74
2.34.1
diff view generated by jsdifflib
[PULL 15/26] target/arm: Move s1_is_el0 into S1Translate
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Instead of passing this to get_phys_addr_lpae, stash it
4
in the S1Translate structure.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230620124418.805717-16-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 27 ++++++++++++---------------
13
1 file changed, 12 insertions(+), 15 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
20
ARMSecuritySpace in_space;
21
bool in_secure;
22
bool in_debug;
23
+ /*
24
+ * If this is stage 2 of a stage 1+2 page table walk, then this must
25
+ * be true if stage 1 is an EL0 access; otherwise this is ignored.
26
+ * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}.
27
+ */
28
+ bool in_s1_is_el0;
29
bool out_secure;
30
bool out_rw;
31
bool out_be;
32
@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
33
} S1Translate;
34
35
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
36
- uint64_t address,
37
- MMUAccessType access_type, bool s1_is_el0,
38
+ uint64_t address, MMUAccessType access_type,
39
GetPhysAddrResult *result, ARMMMUFaultInfo *fi);
40
41
static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
42
@@ -XXX,XX +XXX,XX @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
43
* @ptw: Current and next stage parameters for the walk.
44
* @address: virtual address to get physical address for
45
* @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
46
- * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
47
- * (so this is a stage 2 page table walk),
48
- * must be true if this is stage 2 of a stage 1+2
49
- * walk for an EL0 access. If @mmu_idx is anything else,
50
- * @s1_is_el0 is ignored.
51
* @result: set on translation success,
52
* @fi: set to fault info if the translation fails
53
*/
54
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
55
uint64_t address,
56
- MMUAccessType access_type, bool s1_is_el0,
57
+ MMUAccessType access_type,
58
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
59
{
60
ARMCPU *cpu = env_archcpu(env);
61
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
62
result->f.prot = get_S2prot_noexecute(ap);
63
} else {
64
xn = extract64(attrs, 53, 2);
65
- result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
66
+ result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0);
67
}
68
} else {
69
int nse, ns = extract32(attrs, 5, 1);
70
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
71
bool ret, ipa_secure;
72
ARMCacheAttrs cacheattrs1;
73
ARMSecuritySpace ipa_space;
74
- bool is_el0;
75
uint64_t hcr;
76
77
ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi);
78
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
79
ipa_secure = result->f.attrs.secure;
80
ipa_space = result->f.attrs.space;
81
82
- is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
83
+ ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
84
ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
85
ptw->in_secure = ipa_secure;
86
ptw->in_space = ipa_space;
87
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
88
ret = get_phys_addr_pmsav8(env, ipa, access_type,
89
ptw->in_mmu_idx, is_secure, result, fi);
90
} else {
91
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
92
- is_el0, result, fi);
93
+ ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi);
94
}
95
fi->s2addr = ipa;
96
97
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
98
}
99
100
if (regime_using_lpae_format(env, mmu_idx)) {
101
- return get_phys_addr_lpae(env, ptw, address, access_type, false,
102
- result, fi);
103
+ return get_phys_addr_lpae(env, ptw, address, access_type, result, fi);
104
} else if (arm_feature(env, ARM_FEATURE_V7) ||
105
regime_sctlr(env, mmu_idx) & SCTLR_XP) {
106
return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
107
--
108
2.34.1
109
110
diff view generated by jsdifflib
[PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This fixes a bug in which we failed to initialize
4
the result attributes properly after the memset.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230620124418.805717-17-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 11 +----------
13
1 file changed, 1 insertion(+), 10 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
20
void *out_host;
21
} S1Translate;
22
23
-static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
24
- uint64_t address, MMUAccessType access_type,
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi);
26
-
27
static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
28
target_ulong address,
29
MMUAccessType access_type,
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
31
cacheattrs1 = result->cacheattrs;
32
memset(result, 0, sizeof(*result));
33
34
- if (arm_feature(env, ARM_FEATURE_PMSA)) {
35
- ret = get_phys_addr_pmsav8(env, ipa, access_type,
36
- ptw->in_mmu_idx, is_secure, result, fi);
37
- } else {
38
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi);
39
- }
40
+ ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi);
41
fi->s2addr = ipa;
42
43
/* Combine the S1 and S2 perms. */
44
--
45
2.34.1
46
47
diff view generated by jsdifflib
[PULL 17/26] target/arm: Add GPC syndrome
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The function takes the fields as filled in by
4
the Arm ARM pseudocode for TakeGPCException.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-18-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/syndrome.h | 10 ++++++++++
12
1 file changed, 10 insertions(+)
13
14
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/syndrome.h
17
+++ b/target/arm/syndrome.h
18
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
19
EC_SVEACCESSTRAP = 0x19,
20
EC_ERETTRAP = 0x1a,
21
EC_SMETRAP = 0x1d,
22
+ EC_GPC = 0x1e,
23
EC_INSNABORT = 0x20,
24
EC_INSNABORT_SAME_EL = 0x21,
25
EC_PCALIGNMENT = 0x22,
26
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
27
(cv << 24) | (cond << 20) | rm;
28
}
29
30
+static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc,
31
+ int cm, int s1ptw, int wnr, int fsc)
32
+{
33
+ /* TODO: FEAT_NV2 adds VNCR */
34
+ return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21)
35
+ | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7)
36
+ | (wnr << 6) | fsc;
37
+}
38
+
39
static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
40
{
41
return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
42
--
43
2.34.1
diff view generated by jsdifflib
[PULL 18/26] target/arm: Implement GPC exceptions
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Handle GPC Fault types in arm_deliver_fault, reporting as
4
either a GPC exception at EL3, or falling through to insn
5
or data aborts at various exception levels.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230620124418.805717-19-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 1 +
13
target/arm/internals.h | 27 +++++++++++
14
target/arm/helper.c | 5 ++
15
target/arm/tcg/tlb_helper.c | 96 +++++++++++++++++++++++++++++++++++--
16
4 files changed, 126 insertions(+), 3 deletions(-)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@
23
#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
24
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
25
#define EXCP_VSERR 24
26
+#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */
27
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
28
29
#define ARMV7M_EXCP_RESET 1
30
diff --git a/target/arm/internals.h b/target/arm/internals.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/internals.h
33
+++ b/target/arm/internals.h
34
@@ -XXX,XX +XXX,XX @@ typedef enum ARMFaultType {
35
ARMFault_ICacheMaint,
36
ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */
37
ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
38
+ ARMFault_GPCFOnWalk,
39
+ ARMFault_GPCFOnOutput,
40
} ARMFaultType;
41
42
+typedef enum ARMGPCF {
43
+ GPCF_None,
44
+ GPCF_AddressSize,
45
+ GPCF_Walk,
46
+ GPCF_EABT,
47
+ GPCF_Fail,
48
+} ARMGPCF;
49
+
50
/**
51
* ARMMMUFaultInfo: Information describing an ARM MMU Fault
52
* @type: Type of fault
53
+ * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}.
54
* @level: Table walk level (for translation, access flag and permission faults)
55
* @domain: Domain of the fault address (for non-LPAE CPUs only)
56
* @s2addr: Address that caused a fault at stage 2
57
+ * @paddr: physical address that caused a fault for gpc
58
+ * @paddr_space: physical address space that caused a fault for gpc
59
* @stage2: True if we faulted at stage 2
60
* @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
61
* @s1ns: True if we faulted on a non-secure IPA while in secure state
62
@@ -XXX,XX +XXX,XX @@ typedef enum ARMFaultType {
63
typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
64
struct ARMMMUFaultInfo {
65
ARMFaultType type;
66
+ ARMGPCF gpcf;
67
target_ulong s2addr;
68
+ target_ulong paddr;
69
+ ARMSecuritySpace paddr_space;
70
int level;
71
int domain;
72
bool stage2;
73
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
74
case ARMFault_Exclusive:
75
fsc = 0x35;
76
break;
77
+ case ARMFault_GPCFOnWalk:
78
+ assert(fi->level >= -1 && fi->level <= 3);
79
+ if (fi->level < 0) {
80
+ fsc = 0b100011;
81
+ } else {
82
+ fsc = 0b100100 | fi->level;
83
+ }
84
+ break;
85
+ case ARMFault_GPCFOnOutput:
86
+ fsc = 0b101000;
87
+ break;
88
default:
89
/* Other faults can't occur in a context that requires a
90
* long-format status code.
91
diff --git a/target/arm/helper.c b/target/arm/helper.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/arm/helper.c
94
+++ b/target/arm/helper.c
95
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
96
[EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
97
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
98
[EXCP_VSERR] = "Virtual SERR",
99
+ [EXCP_GPC] = "Granule Protection Check",
100
};
101
102
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
103
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
104
}
105
106
switch (cs->exception_index) {
107
+ case EXCP_GPC:
108
+ qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n",
109
+ env->cp15.mfar_el3);
110
+ /* fall through */
111
case EXCP_PREFETCH_ABORT:
112
case EXCP_DATA_ABORT:
113
/*
114
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/tcg/tlb_helper.c
117
+++ b/target/arm/tcg/tlb_helper.c
118
@@ -XXX,XX +XXX,XX @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
119
return fsr;
120
}
121
122
+static bool report_as_gpc_exception(ARMCPU *cpu, int current_el,
123
+ ARMMMUFaultInfo *fi)
124
+{
125
+ bool ret;
126
+
127
+ switch (fi->gpcf) {
128
+ case GPCF_None:
129
+ return false;
130
+ case GPCF_AddressSize:
131
+ case GPCF_Walk:
132
+ case GPCF_EABT:
133
+ /* R_PYTGX: GPT faults are reported as GPC. */
134
+ ret = true;
135
+ break;
136
+ case GPCF_Fail:
137
+ /*
138
+ * R_BLYPM: A GPF at EL3 is reported as insn or data abort.
139
+ * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC
140
+ * if SCR_EL3.GPF is set, otherwise an insn or data abort.
141
+ */
142
+ ret = (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el != 3;
143
+ break;
144
+ default:
145
+ g_assert_not_reached();
146
+ }
147
+
148
+ assert(cpu_isar_feature(aa64_rme, cpu));
149
+ assert(fi->type == ARMFault_GPCFOnWalk ||
150
+ fi->type == ARMFault_GPCFOnOutput);
151
+ if (fi->gpcf == GPCF_AddressSize) {
152
+ assert(fi->level == 0);
153
+ } else {
154
+ assert(fi->level >= 0 && fi->level <= 1);
155
+ }
156
+
157
+ return ret;
158
+}
159
+
160
+static unsigned encode_gpcsc(ARMMMUFaultInfo *fi)
161
+{
162
+ static uint8_t const gpcsc[] = {
163
+ [GPCF_AddressSize] = 0b000000,
164
+ [GPCF_Walk] = 0b000100,
165
+ [GPCF_Fail] = 0b001100,
166
+ [GPCF_EABT] = 0b010100,
167
+ };
168
+
169
+ /* Note that we've validated fi->gpcf and fi->level above. */
170
+ return gpcsc[fi->gpcf] | fi->level;
171
+}
172
+
173
static G_NORETURN
174
void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
175
MMUAccessType access_type,
176
int mmu_idx, ARMMMUFaultInfo *fi)
177
{
178
CPUARMState *env = &cpu->env;
179
- int target_el;
180
+ int target_el = exception_target_el(env);
181
+ int current_el = arm_current_el(env);
182
bool same_el;
183
uint32_t syn, exc, fsr, fsc;
184
185
- target_el = exception_target_el(env);
186
+ if (report_as_gpc_exception(cpu, current_el, fi)) {
187
+ target_el = 3;
188
+
189
+ fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
190
+
191
+ syn = syn_gpc(fi->stage2 && fi->type == ARMFault_GPCFOnWalk,
192
+ access_type == MMU_INST_FETCH,
193
+ encode_gpcsc(fi), 0, fi->s1ptw,
194
+ access_type == MMU_DATA_STORE, fsc);
195
+
196
+ env->cp15.mfar_el3 = fi->paddr;
197
+ switch (fi->paddr_space) {
198
+ case ARMSS_Secure:
199
+ break;
200
+ case ARMSS_NonSecure:
201
+ env->cp15.mfar_el3 |= R_MFAR_NS_MASK;
202
+ break;
203
+ case ARMSS_Root:
204
+ env->cp15.mfar_el3 |= R_MFAR_NSE_MASK;
205
+ break;
206
+ case ARMSS_Realm:
207
+ env->cp15.mfar_el3 |= R_MFAR_NSE_MASK | R_MFAR_NS_MASK;
208
+ break;
209
+ default:
210
+ g_assert_not_reached();
211
+ }
212
+
213
+ exc = EXCP_GPC;
214
+ goto do_raise;
215
+ }
216
+
217
+ /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */
218
+ if (fi->gpcf == GPCF_Fail && target_el < 2) {
219
+ if (arm_hcr_el2_eff(env) & HCR_GPF) {
220
+ target_el = 2;
221
+ }
222
+ }
223
+
224
if (fi->stage2) {
225
target_el = 2;
226
env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
227
@@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
228
env->cp15.hpfar_el2 |= HPFAR_NS;
229
}
230
}
231
- same_el = (arm_current_el(env) == target_el);
232
233
+ same_el = current_el == target_el;
234
fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
235
236
if (access_type == MMU_INST_FETCH) {
237
@@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
238
exc = EXCP_DATA_ABORT;
239
}
240
241
+ do_raise:
242
env->exception.vaddress = addr;
243
env->exception.fsr = fsr;
244
raise_exception(env, exc, syn, target_el);
245
--
246
2.34.1
diff view generated by jsdifflib
[PULL 19/26] target/arm: Implement the granule protection check
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Place the check at the end of get_phys_addr_with_struct,
4
so that we check all physical results.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230620124418.805717-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 249 +++++++++++++++++++++++++++++++++++++++++++----
12
1 file changed, 232 insertions(+), 17 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
19
void *out_host;
20
} S1Translate;
21
22
-static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
23
- target_ulong address,
24
- MMUAccessType access_type,
25
- GetPhysAddrResult *result,
26
- ARMMMUFaultInfo *fi);
27
+static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw,
28
+ target_ulong address,
29
+ MMUAccessType access_type,
30
+ GetPhysAddrResult *result,
31
+ ARMMMUFaultInfo *fi);
32
+
33
+static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw,
34
+ target_ulong address,
35
+ MMUAccessType access_type,
36
+ GetPhysAddrResult *result,
37
+ ARMMMUFaultInfo *fi);
38
39
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
40
static const uint8_t pamax_map[] = {
41
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
42
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
43
}
44
45
+static bool granule_protection_check(CPUARMState *env, uint64_t paddress,
46
+ ARMSecuritySpace pspace,
47
+ ARMMMUFaultInfo *fi)
48
+{
49
+ MemTxAttrs attrs = {
50
+ .secure = true,
51
+ .space = ARMSS_Root,
52
+ };
53
+ ARMCPU *cpu = env_archcpu(env);
54
+ uint64_t gpccr = env->cp15.gpccr_el3;
55
+ unsigned pps, pgs, l0gptsz, level = 0;
56
+ uint64_t tableaddr, pps_mask, align, entry, index;
57
+ AddressSpace *as;
58
+ MemTxResult result;
59
+ int gpi;
60
+
61
+ if (!FIELD_EX64(gpccr, GPCCR, GPC)) {
62
+ return true;
63
+ }
64
+
65
+ /*
66
+ * GPC Priority 1 (R_GMGRR):
67
+ * R_JWCSM: If the configuration of GPCCR_EL3 is invalid,
68
+ * the access fails as GPT walk fault at level 0.
69
+ */
70
+
71
+ /*
72
+ * Configuration of PPS to a value exceeding the implemented
73
+ * physical address size is invalid.
74
+ */
75
+ pps = FIELD_EX64(gpccr, GPCCR, PPS);
76
+ if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) {
77
+ goto fault_walk;
78
+ }
79
+ pps = pamax_map[pps];
80
+ pps_mask = MAKE_64BIT_MASK(0, pps);
81
+
82
+ switch (FIELD_EX64(gpccr, GPCCR, SH)) {
83
+ case 0b10: /* outer shareable */
84
+ break;
85
+ case 0b00: /* non-shareable */
86
+ case 0b11: /* inner shareable */
87
+ /* Inner and Outer non-cacheable requires Outer shareable. */
88
+ if (FIELD_EX64(gpccr, GPCCR, ORGN) == 0 &&
89
+ FIELD_EX64(gpccr, GPCCR, IRGN) == 0) {
90
+ goto fault_walk;
91
+ }
92
+ break;
93
+ default: /* reserved */
94
+ goto fault_walk;
95
+ }
96
+
97
+ switch (FIELD_EX64(gpccr, GPCCR, PGS)) {
98
+ case 0b00: /* 4KB */
99
+ pgs = 12;
100
+ break;
101
+ case 0b01: /* 64KB */
102
+ pgs = 16;
103
+ break;
104
+ case 0b10: /* 16KB */
105
+ pgs = 14;
106
+ break;
107
+ default: /* reserved */
108
+ goto fault_walk;
109
+ }
110
+
111
+ /* Note this field is read-only and fixed at reset. */
112
+ l0gptsz = 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ);
113
+
114
+ /*
115
+ * GPC Priority 2: Secure, Realm or Root address exceeds PPS.
116
+ * R_CPDSB: A NonSecure physical address input exceeding PPS
117
+ * does not experience any fault.
118
+ */
119
+ if (paddress & ~pps_mask) {
120
+ if (pspace == ARMSS_NonSecure) {
121
+ return true;
122
+ }
123
+ goto fault_size;
124
+ }
125
+
126
+ /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */
127
+ tableaddr = env->cp15.gptbr_el3 << 12;
128
+ if (tableaddr & ~pps_mask) {
129
+ goto fault_size;
130
+ }
131
+
132
+ /*
133
+ * BADDR is aligned per a function of PPS and L0GPTSZ.
134
+ * These bits of GPTBR_EL3 are RES0, but are not a configuration error,
135
+ * unlike the RES0 bits of the GPT entries (R_XNKFZ).
136
+ */
137
+ align = MAX(pps - l0gptsz + 3, 12);
138
+ align = MAKE_64BIT_MASK(0, align);
139
+ tableaddr &= ~align;
140
+
141
+ as = arm_addressspace(env_cpu(env), attrs);
142
+
143
+ /* Level 0 lookup. */
144
+ index = extract64(paddress, l0gptsz, pps - l0gptsz);
145
+ tableaddr += index * 8;
146
+ entry = address_space_ldq_le(as, tableaddr, attrs, &result);
147
+ if (result != MEMTX_OK) {
148
+ goto fault_eabt;
149
+ }
150
+
151
+ switch (extract32(entry, 0, 4)) {
152
+ case 1: /* block descriptor */
153
+ if (entry >> 8) {
154
+ goto fault_walk; /* RES0 bits not 0 */
155
+ }
156
+ gpi = extract32(entry, 4, 4);
157
+ goto found;
158
+ case 3: /* table descriptor */
159
+ tableaddr = entry & ~0xf;
160
+ align = MAX(l0gptsz - pgs - 1, 12);
161
+ align = MAKE_64BIT_MASK(0, align);
162
+ if (tableaddr & (~pps_mask | align)) {
163
+ goto fault_walk; /* RES0 bits not 0 */
164
+ }
165
+ break;
166
+ default: /* invalid */
167
+ goto fault_walk;
168
+ }
169
+
170
+ /* Level 1 lookup */
171
+ level = 1;
172
+ index = extract64(paddress, pgs + 4, l0gptsz - pgs - 4);
173
+ tableaddr += index * 8;
174
+ entry = address_space_ldq_le(as, tableaddr, attrs, &result);
175
+ if (result != MEMTX_OK) {
176
+ goto fault_eabt;
177
+ }
178
+
179
+ switch (extract32(entry, 0, 4)) {
180
+ case 1: /* contiguous descriptor */
181
+ if (entry >> 10) {
182
+ goto fault_walk; /* RES0 bits not 0 */
183
+ }
184
+ /*
185
+ * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE,
186
+ * and because we cannot invalidate by pa, and thus will always
187
+ * flush entire tlbs, we don't actually care about the range here
188
+ * and can simply extract the GPI as the result.
189
+ */
190
+ if (extract32(entry, 8, 2) == 0) {
191
+ goto fault_walk; /* reserved contig */
192
+ }
193
+ gpi = extract32(entry, 4, 4);
194
+ break;
195
+ default:
196
+ index = extract64(paddress, pgs, 4);
197
+ gpi = extract64(entry, index * 4, 4);
198
+ break;
199
+ }
200
+
201
+ found:
202
+ switch (gpi) {
203
+ case 0b0000: /* no access */
204
+ break;
205
+ case 0b1111: /* all access */
206
+ return true;
207
+ case 0b1000:
208
+ case 0b1001:
209
+ case 0b1010:
210
+ case 0b1011:
211
+ if (pspace == (gpi & 3)) {
212
+ return true;
213
+ }
214
+ break;
215
+ default:
216
+ goto fault_walk; /* reserved */
217
+ }
218
+
219
+ fi->gpcf = GPCF_Fail;
220
+ goto fault_common;
221
+ fault_eabt:
222
+ fi->gpcf = GPCF_EABT;
223
+ goto fault_common;
224
+ fault_size:
225
+ fi->gpcf = GPCF_AddressSize;
226
+ goto fault_common;
227
+ fault_walk:
228
+ fi->gpcf = GPCF_Walk;
229
+ fault_common:
230
+ fi->level = level;
231
+ fi->paddr = paddress;
232
+ fi->paddr_space = pspace;
233
+ return false;
234
+}
235
+
236
static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
237
{
238
/*
239
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
240
};
241
GetPhysAddrResult s2 = { };
242
243
- if (get_phys_addr_with_struct(env, &s2ptw, addr,
244
- MMU_DATA_LOAD, &s2, fi)) {
245
+ if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) {
246
goto fail;
247
}
248
+
249
ptw->out_phys = s2.f.phys_addr;
250
pte_attrs = s2.cacheattrs.attrs;
251
ptw->out_host = NULL;
252
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
253
254
fail:
255
assert(fi->type != ARMFault_None);
256
+ if (fi->type == ARMFault_GPCFOnOutput) {
257
+ fi->type = ARMFault_GPCFOnWalk;
258
+ }
259
fi->s2addr = addr;
260
fi->stage2 = true;
261
fi->s1ptw = true;
262
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
263
ARMMMUFaultInfo *fi)
264
{
265
uint8_t memattr = 0x00; /* Device nGnRnE */
266
- uint8_t shareability = 0; /* non-sharable */
267
+ uint8_t shareability = 0; /* non-shareable */
268
int r_el;
269
270
switch (mmu_idx) {
271
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
272
} else {
273
memattr = 0x44; /* Normal, NC, No */
274
}
275
- shareability = 2; /* outer sharable */
276
+ shareability = 2; /* outer shareable */
277
}
278
result->cacheattrs.is_s2_format = false;
279
break;
280
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
281
ARMSecuritySpace ipa_space;
282
uint64_t hcr;
283
284
- ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi);
285
+ ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi);
286
287
/* If S1 fails, return early. */
288
if (ret) {
289
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
290
cacheattrs1 = result->cacheattrs;
291
memset(result, 0, sizeof(*result));
292
293
- ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi);
294
+ ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi);
295
fi->s2addr = ipa;
296
297
/* Combine the S1 and S2 perms. */
298
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
299
return false;
300
}
301
302
-static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
303
+static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw,
304
target_ulong address,
305
MMUAccessType access_type,
306
GetPhysAddrResult *result,
307
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
308
}
309
}
310
311
+static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw,
312
+ target_ulong address,
313
+ MMUAccessType access_type,
314
+ GetPhysAddrResult *result,
315
+ ARMMMUFaultInfo *fi)
316
+{
317
+ if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) {
318
+ return true;
319
+ }
320
+ if (!granule_protection_check(env, result->f.phys_addr,
321
+ result->f.attrs.space, fi)) {
322
+ fi->type = ARMFault_GPCFOnOutput;
323
+ return true;
324
+ }
325
+ return false;
326
+}
327
+
328
bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
329
MMUAccessType access_type, ARMMMUIdx mmu_idx,
330
bool is_secure, GetPhysAddrResult *result,
331
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
332
.in_secure = is_secure,
333
.in_space = arm_secure_to_space(is_secure),
334
};
335
- return get_phys_addr_with_struct(env, &ptw, address, access_type,
336
- result, fi);
337
+ return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi);
338
}
339
340
bool get_phys_addr(CPUARMState *env, target_ulong address,
341
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
342
343
ptw.in_space = ss;
344
ptw.in_secure = arm_space_is_secure(ss);
345
- return get_phys_addr_with_struct(env, &ptw, address, access_type,
346
- result, fi);
347
+ return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi);
348
}
349
350
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
351
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
352
ARMMMUFaultInfo fi = {};
353
bool ret;
354
355
- ret = get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi);
356
+ ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi);
357
*attrs = res.f.attrs;
358
359
if (ret) {
360
--
361
2.34.1
diff view generated by jsdifflib
[PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Add an x-rme cpu property to enable FEAT_RME.
4
Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ,
5
for testing various possible configurations.
6
7
We're not currently completely sure whether FEAT_RME will
8
be OK to enable purely as a CPU-level property, or if it will
9
need board co-operation, so we're making these experimental
10
x- properties, so that the people developing the system
11
level software for RME can try to start using this and let
12
us know how it goes. The command line syntax for enabling
13
this will change in future, without backwards-compatibility.
14
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20230620124418.805717-21-richard.henderson@linaro.org
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/tcg/cpu64.c | 53 ++++++++++++++++++++++++++++++++++++++++++
21
1 file changed, 53 insertions(+)
22
23
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/tcg/cpu64.c
26
+++ b/target/arm/tcg/cpu64.c
27
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
28
cpu->sve_max_vq = max_vq;
29
}
30
31
+static bool cpu_arm_get_rme(Object *obj, Error **errp)
32
+{
33
+ ARMCPU *cpu = ARM_CPU(obj);
34
+ return cpu_isar_feature(aa64_rme, cpu);
35
+}
36
+
37
+static void cpu_arm_set_rme(Object *obj, bool value, Error **errp)
38
+{
39
+ ARMCPU *cpu = ARM_CPU(obj);
40
+ uint64_t t;
41
+
42
+ t = cpu->isar.id_aa64pfr0;
43
+ t = FIELD_DP64(t, ID_AA64PFR0, RME, value);
44
+ cpu->isar.id_aa64pfr0 = t;
45
+}
46
+
47
+static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
48
+ void *opaque, Error **errp)
49
+{
50
+ ARMCPU *cpu = ARM_CPU(obj);
51
+ uint32_t value;
52
+
53
+ if (!visit_type_uint32(v, name, &value, errp)) {
54
+ return;
55
+ }
56
+
57
+ /* Encode the value for the GPCCR_EL3 field. */
58
+ switch (value) {
59
+ case 30:
60
+ case 34:
61
+ case 36:
62
+ case 39:
63
+ cpu->reset_l0gptsz = value - 30;
64
+ break;
65
+ default:
66
+ error_setg(errp, "invalid value for l0gptsz");
67
+ error_append_hint(errp, "valid values are 30, 34, 36, 39\n");
68
+ break;
69
+ }
70
+}
71
+
72
+static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name,
73
+ void *opaque, Error **errp)
74
+{
75
+ ARMCPU *cpu = ARM_CPU(obj);
76
+ uint32_t value = cpu->reset_l0gptsz + 30;
77
+
78
+ visit_type_uint32(v, name, &value, errp);
79
+}
80
+
81
static Property arm_cpu_lpa2_property =
82
DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
83
84
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
85
aarch64_add_sme_properties(obj);
86
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
87
cpu_max_set_sve_max_vq, NULL, NULL);
88
+ object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme);
89
+ object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz,
90
+ cpu_max_set_l0gptsz, NULL, NULL);
91
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
92
}
93
94
--
95
2.34.1
diff view generated by jsdifflib
[PULL 21/26] docs/system/arm: Document FEAT_RME
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Message-id: 20230622143046.1578160-1-richard.henderson@linaro.org
6
[PMM: fixed typo; note experimental status in emulation.rst too]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
docs/system/arm/cpu-features.rst | 23 +++++++++++++++++++++++
10
docs/system/arm/emulation.rst | 1 +
11
2 files changed, 24 insertions(+)
12
13
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
14
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/cpu-features.rst
16
+++ b/docs/system/arm/cpu-features.rst
17
@@ -XXX,XX +XXX,XX @@ As with ``sve-default-vector-length``, if the default length is larger
18
than the maximum vector length enabled, the actual vector length will
19
be reduced. If this property is set to ``-1`` then the default vector
20
length is set to the maximum possible length.
21
+
22
+RME CPU Properties
23
+==================
24
+
25
+The status of RME support with QEMU is experimental. At this time we
26
+only support RME within the CPU proper, not within the SMMU or GIC.
27
+The feature is enabled by the CPU property ``x-rme``, with the ``x-``
28
+prefix present as a reminder of the experimental status, and defaults off.
29
+
30
+The method for enabling RME will change in some future QEMU release
31
+without notice or backward compatibility.
32
+
33
+RME Level 0 GPT Size Property
34
+-----------------------------
35
+
36
+To aid firmware developers in testing different possible CPU
37
+configurations, ``x-l0gptsz=S`` may be used to specify the value
38
+to encode into ``GPCCR_EL3.L0GPTSZ``, a read-only field that
39
+specifies the size of the Level 0 Granule Protection Table.
40
+Legal values for ``S`` are 30, 34, 36, and 39; the default is 30.
41
+
42
+As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or
43
+removed in some future QEMU release.
44
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
45
index XXXXXXX..XXXXXXX 100644
46
--- a/docs/system/arm/emulation.rst
47
+++ b/docs/system/arm/emulation.rst
48
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
49
- FEAT_RAS (Reliability, availability, and serviceability)
50
- FEAT_RASv1p1 (RAS Extension v1.1)
51
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
52
+- FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental)
53
- FEAT_RNG (Random number generator)
54
- FEAT_S2FWB (Stage 2 forced Write-Back)
55
- FEAT_SB (Speculation Barrier)
56
--
57
2.34.1
58
59
diff view generated by jsdifflib
[PULL 22/26] host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
Deleted patch
1
We use __builtin_subcll() to do a 64-bit subtract with borrow-in and
2
borrow-out when the host compiler supports it. Unfortunately some
3
versions of Apple Clang have a bug in their implementation of this
4
intrinsic which means it returns the wrong value. The effect is that
5
a QEMU built with the affected compiler will hang when emulating x86
6
or m68k float80 division.
7
1
8
The upstream LLVM issue is:
9
https://github.com/llvm/llvm-project/issues/55253
10
11
The commit that introduced the bug apparently never made it into an
12
upstream LLVM release without the subsequent fix
13
https://github.com/llvm/llvm-project/commit/fffb6e6afdbaba563189c1f715058ed401fbc88d
14
but unfortunately it did make it into Apple Clang 14.0, as shipped
15
in Xcode 14.3 (14.2 is reported to be OK). The Apple bug number is
16
FB12210478.
17
18
Add ifdefs to avoid use of __builtin_subcll() on Apple Clang version
19
14 or greater. There is not currently a version of Apple Clang which
20
has the bug fix -- when one appears we should be able to add an upper
21
bound to the ifdef condition so we can start using the builtin again.
22
We make the lower bound a conservative "any Apple clang with major
23
version 14 or greater" because the consequences of incorrectly
24
disabling the builtin when it would work are pretty small and the
25
consequences of not disabling it when we should are pretty bad.
26
27
Many thanks to those users who both reported this bug and also
28
did a lot of work in identifying the root cause; in particular
29
to Daniel Bertalan and osy.
30
31
Cc: qemu-stable@nongnu.org
32
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1631
33
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1659
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
37
Tested-by: Daniel Bertalan <dani@danielbertalan.dev>
38
Tested-by: Tested-By: Solra Bizna <solra@bizna.name>
39
Message-id: 20230622130823.1631719-1-peter.maydell@linaro.org
40
---
41
include/qemu/compiler.h | 13 +++++++++++++
42
include/qemu/host-utils.h | 2 +-
43
2 files changed, 14 insertions(+), 1 deletion(-)
44
45
diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/include/qemu/compiler.h
48
+++ b/include/qemu/compiler.h
49
@@ -XXX,XX +XXX,XX @@
50
#define QEMU_DISABLE_CFI
51
#endif
52
53
+/*
54
+ * Apple clang version 14 has a bug in its __builtin_subcll(); define
55
+ * BUILTIN_SUBCLL_BROKEN for the offending versions so we can avoid it.
56
+ * When a version of Apple clang which has this bug fixed is released
57
+ * we can add an upper bound to this check.
58
+ * See https://gitlab.com/qemu-project/qemu/-/issues/1631
59
+ * and https://gitlab.com/qemu-project/qemu/-/issues/1659 for details.
60
+ * The bug never made it into any upstream LLVM releases, only Apple ones.
61
+ */
62
+#if defined(__apple_build_version__) && __clang_major__ >= 14
63
+#define BUILTIN_SUBCLL_BROKEN
64
+#endif
65
+
66
#endif /* COMPILER_H */
67
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
68
index XXXXXXX..XXXXXXX 100644
69
--- a/include/qemu/host-utils.h
70
+++ b/include/qemu/host-utils.h
71
@@ -XXX,XX +XXX,XX @@ static inline uint64_t uadd64_carry(uint64_t x, uint64_t y, bool *pcarry)
72
*/
73
static inline uint64_t usub64_borrow(uint64_t x, uint64_t y, bool *pborrow)
74
{
75
-#if __has_builtin(__builtin_subcll)
76
+#if __has_builtin(__builtin_subcll) && !defined(BUILTIN_SUBCLL_BROKEN)
77
unsigned long long b = *pborrow;
78
x = __builtin_subcll(x, y, b, &b);
79
*pborrow = b & 1;
80
--
81
2.34.1
82
83
diff view generated by jsdifflib
[PULL 23/26] target/arm: Restructure has_vfp_d32 test
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
One cannot test for feature aa32_simd_r32 without first
4
testing if AArch32 mode is supported at all. This leads to
5
6
qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
7
8
for Apple M1 cpus.
9
10
We already have a check for ARMv8-A never setting vfp-d32 true,
11
so restructure the code so that AArch64 avoids the test entirely.
12
13
Reported-by: Mads Ynddal <mads@ynddal.dk>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
Tested-by: Mads Ynddal <m.ynddal@samsung.com>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Reviewed-by: Cédric Le Goater <clg@kaod.org>
19
Reviewed-by: Mads Ynddal <m.ynddal@samsung.com>
20
Message-id: 20230619140216.402530-1-richard.henderson@linaro.org
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
target/arm/cpu.c | 28 +++++++++++++++-------------
24
1 file changed, 15 insertions(+), 13 deletions(-)
25
26
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/cpu.c
29
+++ b/target/arm/cpu.c
30
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
31
* KVM does not currently allow us to lie to the guest about its
32
* ID/feature registers, so the guest always sees what the host has.
33
*/
34
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
35
- ? cpu_isar_feature(aa64_fp_simd, cpu)
36
- : cpu_isar_feature(aa32_vfp, cpu)) {
37
- cpu->has_vfp = true;
38
- if (!kvm_enabled()) {
39
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
40
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
41
+ if (cpu_isar_feature(aa64_fp_simd, cpu)) {
42
+ cpu->has_vfp = true;
43
+ cpu->has_vfp_d32 = true;
44
+ if (tcg_enabled() || qtest_enabled()) {
45
+ qdev_property_add_static(DEVICE(obj),
46
+ &arm_cpu_has_vfp_property);
47
+ }
48
}
49
- }
50
-
51
- if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
52
- cpu->has_vfp_d32 = true;
53
- if (!kvm_enabled()) {
54
+ } else if (cpu_isar_feature(aa32_vfp, cpu)) {
55
+ cpu->has_vfp = true;
56
+ if (cpu_isar_feature(aa32_simd_r32, cpu)) {
57
+ cpu->has_vfp_d32 = true;
58
/*
59
* The permitted values of the SIMDReg bits [3:0] on
60
* Armv8-A are either 0b0000 and 0b0010. On such CPUs,
61
* make sure that has_vfp_d32 can not be set to false.
62
*/
63
- if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) &&
64
- !arm_feature(&cpu->env, ARM_FEATURE_M))) {
65
+ if ((tcg_enabled() || qtest_enabled())
66
+ && !(arm_feature(&cpu->env, ARM_FEATURE_V8)
67
+ && !arm_feature(&cpu->env, ARM_FEATURE_M))) {
68
qdev_property_add_static(DEVICE(obj),
69
&arm_cpu_has_vfp_d32_property);
70
}
71
--
72
2.34.1
73
74
diff view generated by jsdifflib
[PULL 24/26] hw/arm/sbsa-ref: add ITS support in SBSA GIC
Deleted patch
1
From: Shashi Mallela <shashi.mallela@linaro.org>
2
1
3
Create ITS as part of SBSA platform GIC initialization.
4
5
GIC ITS information is in DeviceTree so TF-A can pass it to EDK2.
6
7
Bumping platform version to 0.2 as this is important hardware change.
8
9
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
11
Message-id: 20230619170913.517373-2-marcin.juszkiewicz@linaro.org
12
Co-authored-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
13
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
docs/system/arm/sbsa.rst | 14 ++++++++++++++
18
hw/arm/sbsa-ref.c | 33 ++++++++++++++++++++++++++++++---
19
2 files changed, 44 insertions(+), 3 deletions(-)
20
21
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
22
index XXXXXXX..XXXXXXX 100644
23
--- a/docs/system/arm/sbsa.rst
24
+++ b/docs/system/arm/sbsa.rst
25
@@ -XXX,XX +XXX,XX @@ to be a complete compliant DT. It currently reports:
26
- platform version
27
- GIC addresses
28
29
+Platform version
30
+''''''''''''''''
31
+
32
The platform version is only for informing platform firmware about
33
what kind of ``sbsa-ref`` board it is running on. It is neither
34
a QEMU versioned machine type nor a reflection of the level of the
35
@@ -XXX,XX +XXX,XX @@ SBSA/SystemReady SR support provided.
36
The ``machine-version-major`` value is updated when changes breaking
37
fw compatibility are introduced. The ``machine-version-minor`` value
38
is updated when features are added that don't break fw compatibility.
39
+
40
+Platform version changes:
41
+
42
+0.0
43
+ Devicetree holds information about CPUs, memory and platform version.
44
+
45
+0.1
46
+ GIC information is present in devicetree.
47
+
48
+0.2
49
+ GIC ITS information is present in devicetree.
50
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/arm/sbsa-ref.c
53
+++ b/hw/arm/sbsa-ref.c
54
@@ -XXX,XX +XXX,XX @@ enum {
55
SBSA_CPUPERIPHS,
56
SBSA_GIC_DIST,
57
SBSA_GIC_REDIST,
58
+ SBSA_GIC_ITS,
59
SBSA_SECURE_EC,
60
SBSA_GWDT_WS0,
61
SBSA_GWDT_REFRESH,
62
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
63
[SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
64
[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
65
[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
66
+ [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 },
67
[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
68
[SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
69
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
70
@@ -XXX,XX +XXX,XX @@ static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
71
2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
72
2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
73
74
+ nodename = g_strdup_printf("/intc/its");
75
+ qemu_fdt_add_subnode(sms->fdt, nodename);
76
+ qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
77
+ 2, sbsa_ref_memmap[SBSA_GIC_ITS].base,
78
+ 2, sbsa_ref_memmap[SBSA_GIC_ITS].size);
79
+
80
g_free(nodename);
81
}
82
+
83
/*
84
* Firmware on this machine only uses ACPI table to load OS, these limited
85
* device tree nodes are just to let firmware know the info which varies from
86
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
87
* fw compatibility.
88
*/
89
qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
90
- qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1);
91
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2);
92
93
if (ms->numa_state->have_numa_distance) {
94
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
95
@@ -XXX,XX +XXX,XX @@ static void create_secure_ram(SBSAMachineState *sms,
96
memory_region_add_subregion(secure_sysmem, base, secram);
97
}
98
99
-static void create_gic(SBSAMachineState *sms)
100
+static void create_its(SBSAMachineState *sms)
101
+{
102
+ const char *itsclass = its_class_name();
103
+ DeviceState *dev;
104
+
105
+ dev = qdev_new(itsclass);
106
+
107
+ object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
108
+ &error_abort);
109
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
110
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
111
+}
112
+
113
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
114
{
115
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
116
SysBusDevice *gicbusdev;
117
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms)
118
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
119
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
120
121
+ object_property_set_link(OBJECT(sms->gic), "sysmem",
122
+ OBJECT(mem), &error_fatal);
123
+ qdev_prop_set_bit(sms->gic, "has-lpi", true);
124
+
125
gicbusdev = SYS_BUS_DEVICE(sms->gic);
126
sysbus_realize_and_unref(gicbusdev, &error_fatal);
127
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
128
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms)
129
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
130
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
131
}
132
+ create_its(sms);
133
}
134
135
static void create_uart(const SBSAMachineState *sms, int uart,
136
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
137
138
create_secure_ram(sms, secure_sysmem);
139
140
- create_gic(sms);
141
+ create_gic(sms, sysmem);
142
143
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
144
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
145
--
146
2.34.1
diff view generated by jsdifflib
[PULL 25/26] target/arm: Fix sve predicate store, 8 <= VQ <= 15
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Brown bag time: store instead of load results in uninitialized temp.
4
5
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1704
7
Reported-by: Mark Rutland <mark.rutland@arm.com>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230620134659.817559-1-richard.henderson@linaro.org
11
Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
12
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/tcg/translate-sve.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/tcg/translate-sve.c
23
+++ b/target/arm/tcg/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
25
/* Predicate register stores can be any multiple of 2. */
26
if (len_remain >= 8) {
27
t0 = tcg_temp_new_i64();
28
- tcg_gen_st_i64(t0, base, vofs + len_align);
29
+ tcg_gen_ld_i64(t0, base, vofs + len_align);
30
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE);
31
len_remain -= 8;
32
len_align += 8;
33
--
34
2.34.1
35
36
diff view generated by jsdifflib
[PULL 26/26] pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym
Deleted patch
1
The xkb official name for the Arabic keyboard layout is 'ara'.
2
However xkb has for at least the past 15 years also permitted it to
3
be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
4
synoynm was removed, which breaks compilation of QEMU:
5
1
6
FAILED: pc-bios/keymaps/ar
7
/home/fred/qemu-git/src/qemu/build-full/qemu-keymap -f pc-bios/keymaps/ar -l ar
8
xkbcommon: ERROR: Couldn't find file "symbols/ar" in include paths
9
xkbcommon: ERROR: 1 include paths searched:
10
xkbcommon: ERROR:     /usr/share/X11/xkb
11
xkbcommon: ERROR: 3 include paths could not be added:
12
xkbcommon: ERROR:     /home/fred/.config/xkb
13
xkbcommon: ERROR:     /home/fred/.xkb
14
xkbcommon: ERROR:     /etc/xkb
15
xkbcommon: ERROR: Abandoning symbols file "(unnamed)"
16
xkbcommon: ERROR: Failed to compile xkb_symbols
17
xkbcommon: ERROR: Failed to compile keymap
18
19
The upstream xkeyboard-config change removing the compat
20
mapping is:
21
https://gitlab.freedesktop.org/xkeyboard-config/xkeyboard-config/-/commit/470ad2cd8fea84d7210377161d86b31999bb5ea6
22
23
Make QEMU always ask for the 'ara' xkb layout, which should work on
24
both older and newer xkeyboard-config. We leave the QEMU name for
25
this keyboard layout as 'ar'; it is not the only one where our name
26
for it deviates from the xkb standard name.
27
28
Cc: qemu-stable@nongnu.org
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
32
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
33
Message-id: 20230620162024.1132013-1-peter.maydell@linaro.org
34
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1709
35
---
36
pc-bios/keymaps/meson.build | 2 +-
37
1 file changed, 1 insertion(+), 1 deletion(-)
38
39
diff --git a/pc-bios/keymaps/meson.build b/pc-bios/keymaps/meson.build
40
index XXXXXXX..XXXXXXX 100644
41
--- a/pc-bios/keymaps/meson.build
42
+++ b/pc-bios/keymaps/meson.build
43
@@ -XXX,XX +XXX,XX @@
44
keymaps = {
45
- 'ar': '-l ar',
46
+ 'ar': '-l ara',
47
'bepo': '-l fr -v dvorak',
48
'cz': '-l cz',
49
'da': '-l dk',
50
--
51
2.34.1
52
53
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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