Series comparison

-[PULL 0/5] loongarch-to-apply queue
+[PULL 0/7] loongarch-to-apply queue
-The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:
+The following changes since commit cf86770c7aa31ebd6e56f4eeb25c34107f92c51e:
-  Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200)
+  Merge tag 'pull-request-2025-01-21v2' of https://gitlab.com/thuth/qemu into staging (2025-01-22 09:59:02 -0500)
 are available in the Git repository at:
-  https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230616
+  https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250124
-for you to fetch changes up to 505aa8d8f29b79fcef77563bb4124208badbd8d4:
+for you to fetch changes up to 3215fe8528de45a1794f0314623cc10bd8e8e19f:
-  target/loongarch: Fix CSR.DMW0-3.VSEG check (2023-06-16 17:58:46 +0800)
+  target/loongarch: Dump all generic CSR registers (2025-01-24 14:49:24 +0800)
 ----------------------------------------------------------------
-pull-loongarch-20230616
+pull-loongarch-20250124 queue
 * Fix CSR.DMW0-3.VSEG check
 * Add cpu arch_id support
 * Set physical cpuid route for LoongArch ipi device
 * Add numa support
 * Supplement cpu topology arguments
 ----------------------------------------------------------------
-Jiajie Chen (1):
+Bibo Mao (7):
-      target/loongarch: Fix CSR.DMW0-3.VSEG check
+      target/loongarch: Add dynamic function access with CSR register
       target/loongarch: Remove static CSR function setting
       target/loongarch: Add generic csr function type
       target/loongarch: Add common header file for CSR registers
       target/loongarch: Add common source file for CSR register
       target/loongarch: Set unused flag with CSR registers
       target/loongarch: Dump all generic CSR registers
-Tianrui Zhao (4):
+ target/loongarch/cpu.c                             |  96 +++++++++---
-      hw/loongarch/virt: Add cpu arch_id support
+ target/loongarch/csr.c                             | 129 +++++++++++++++++
-      hw/intc: Set physical cpuid route for LoongArch ipi device
+ target/loongarch/csr.h                             |  29 ++++
-      hw/loongarch: Add numa support
+ target/loongarch/meson.build                       |   1 +
-      hw/loongarch: Supplement cpu topology arguments
+ .../tcg/insn_trans/trans_privileged.c.inc          | 161 +++++----------------
+ target/loongarch/tcg/tcg_loongarch.h               |  12 ++
- hw/intc/loongarch_ipi.c       |  44 +++++++++++--
+ target/loongarch/tcg/translate.c                   |   5 +
- hw/loongarch/Kconfig          |   1 +
+files changed, 294 insertions(+), 139 deletions(-)
- hw/loongarch/acpi-build.c     |  78 ++++++++++++++++++-----
+ create mode 100644 target/loongarch/csr.c
- hw/loongarch/virt.c           | 144 ++++++++++++++++++++++++++++++++++++++----
+ create mode 100644 target/loongarch/csr.h
- target/loongarch/cpu.h        |   2 +
+ create mode 100644 target/loongarch/tcg/tcg_loongarch.h
  target/loongarch/tlb_helper.c |   4 +-
 files changed, 235 insertions(+), 38 deletions(-)

-[PULL 4/5] hw/loongarch: Supplement cpu topology arguments
+[PULL 1/7] target/loongarch: Add dynamic function access with CSR register
-From: Tianrui Zhao <zhaotianrui@loongson.cn>
+With CSR register, dynamic function access is used for CSR register
 access in TCG mode, so that csr info can be used by other modules.
-Supplement LoongArch cpu topology arguments, including support socket
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-and threads per core.
+---
  .../tcg/insn_trans/trans_privileged.c.inc     | 37 +++++++++++++++++--
  target/loongarch/tcg/tcg_loongarch.h          | 12 ++++++
  target/loongarch/tcg/translate.c              |  5 +++
 files changed, 51 insertions(+), 3 deletions(-)
  create mode 100644 target/loongarch/tcg/tcg_loongarch.h
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20230613123251.2471878-1-zhaotianrui@loongson.cn>
 ---
  hw/loongarch/acpi-build.c | 4 ++++
  hw/loongarch/virt.c       | 9 ++++++++-
 files changed, 12 insertions(+), 1 deletion(-)
 diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/acpi-build.c
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-+++ b/hw/loongarch/acpi-build.c
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ enum {
-     acpi_add_table(table_offsets, tables_blob);
+ #define CSR_OFF(NAME) \
-     build_madt(tables_blob, tables->linker, lams);
+     CSR_OFF_FLAGS(NAME, 0)
-+    acpi_add_table(table_offsets, tables_blob);
+-static const CSRInfo csr_info[] = {
-+    build_pptt(tables_blob, tables->linker, machine,
++static CSRInfo csr_info[] = {
-+               lams->oem_id, lams->oem_table_id);
+     CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
      CSR_OFF(PRMD),
      CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
      return false;
  }
 -static const CSRInfo *get_csr(unsigned csr_num)
 +static CSRInfo *get_csr(unsigned csr_num)
  {
 -    const CSRInfo *csr;
 +    CSRInfo *csr;
      if (csr_num >= ARRAY_SIZE(csr_info)) {
          return NULL;
@@ -XXX,XX +XXX,XX @@ static const CSRInfo *get_csr(unsigned csr_num)
      return csr;
  }
 +static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
 +                               GenCSRWrite writefn)
 +{
 +    CSRInfo *csr;
 +
-     acpi_add_table(table_offsets, tables_blob);
++    csr = get_csr(csr_num);
-     build_srat(tables_blob, tables->linker, machine);
++    if (!csr) {
++        return false;
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
++    }
 +
 +    csr->readfn = readfn;
 +    csr->writefn = writefn;
 +    return true;
 +}
 +
 +#define SET_CSR_FUNC(NAME, read, write)                 \
 +        set_csr_trans_func(LOONGARCH_CSR_##NAME, read, write)
 +
 +void loongarch_csr_translate_init(void)
 +{
 +    SET_CSR_FUNC(ESTAT, NULL, gen_helper_csrwr_estat);
 +    SET_CSR_FUNC(ASID,  NULL, gen_helper_csrwr_asid);
 +    SET_CSR_FUNC(PGD,   gen_helper_csrrd_pgd, NULL);
 +    SET_CSR_FUNC(PWCL,  NULL, gen_helper_csrwr_pwcl);
 +    SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL);
 +    SET_CSR_FUNC(TCFG,  NULL, gen_helper_csrwr_tcfg);
 +    SET_CSR_FUNC(TVAL,  gen_helper_csrrd_tval, NULL);
 +    SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr);
 +}
 +#undef SET_CSR_FUNC
 +
  static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write)
  {
      if ((csr->flags & CSRFL_READONLY) && write) {
 diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/loongarch/tcg/tcg_loongarch.h
@@ -XXX,XX +XXX,XX @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +/*
 + * QEMU LoongArch TCG interface
 + *
 + * Copyright (c) 2025 Loongson Technology Corporation Limited
 + */
 +#ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H
 +#define TARGET_LOONGARCH_TCG_LOONGARCH_H
 +
 +void loongarch_csr_translate_init(void);
 +
 +#endif  /* TARGET_LOONGARCH_TCG_LOONGARCH_H */
 diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/target/loongarch/tcg/translate.c
-+++ b/hw/loongarch/virt.c
++++ b/target/loongarch/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
+@@ -XXX,XX +XXX,XX @@
-     for (n = 0; n < ms->possible_cpus->len; n++) {
+ #include "exec/log.h"
-         ms->possible_cpus->cpus[n].type = ms->cpu_type;
+ #include "qemu/qemu-print.h"
-         ms->possible_cpus->cpus[n].arch_id = n;
+ #include "fpu/softfloat.h"
 +#include "tcg_loongarch.h"
  #include "translate.h"
  #include "internals.h"
  #include "vec.h"
@@ -XXX,XX +XXX,XX @@ void loongarch_translate_init(void)
                      offsetof(CPULoongArchState, lladdr), "lladdr");
      cpu_llval = tcg_global_mem_new(tcg_env,
                      offsetof(CPULoongArchState, llval), "llval");
 +
-+        ms->possible_cpus->cpus[n].props.has_socket_id = true;
++#ifndef CONFIG_USER_ONLY
-+        ms->possible_cpus->cpus[n].props.socket_id  =
++    loongarch_csr_translate_init();
-+                                   n / (ms->smp.cores * ms->smp.threads);
++#endif
          ms->possible_cpus->cpus[n].props.has_core_id = true;
 -        ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;
 +        ms->possible_cpus->cpus[n].props.core_id =
 +                                   n / ms->smp.threads % ms->smp.cores;
 +        ms->possible_cpus->cpus[n].props.has_thread_id = true;
 +        ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;
      }
      return ms->possible_cpus;
  }
 --
-.39.1
+.43.5

-New patch
+[PULL 2/7] target/loongarch: Remove static CSR function setting
+Since CSR function setting is done dynamically in TCG mode, remove
+static CSR function setting here.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+---
+ .../tcg/insn_trans/trans_privileged.c.inc        | 16 ++++++++--------
+file changed, 8 insertions(+), 8 deletions(-)
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
+     CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
+     CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
+     CSR_OFF(ECFG),
+-    CSR_OFF_FUNCS(ESTAT, CSRFL_EXITTB, NULL, gen_helper_csrwr_estat),
++    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
+     CSR_OFF(ERA),
+     CSR_OFF(BADV),
+     CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
+@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
+     CSR_OFF(TLBEHI),
+     CSR_OFF(TLBELO0),
+     CSR_OFF(TLBELO1),
+-    CSR_OFF_FUNCS(ASID, CSRFL_EXITTB, NULL, gen_helper_csrwr_asid),
++    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
+     CSR_OFF(PGDL),
+     CSR_OFF(PGDH),
+-    CSR_OFF_FUNCS(PGD, CSRFL_READONLY, gen_helper_csrrd_pgd, NULL),
+-    CSR_OFF_FUNCS(PWCL, 0, NULL, gen_helper_csrwr_pwcl),
++    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
++    CSR_OFF(PWCL),
+     CSR_OFF(PWCH),
+     CSR_OFF(STLBPS),
+     CSR_OFF(RVACFG),
+-    CSR_OFF_FUNCS(CPUID, CSRFL_READONLY, gen_helper_csrrd_cpuid, NULL),
++    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
+     CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
+     CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
+     CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
+@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
+     CSR_OFF_ARRAY(SAVE, 14),
+     CSR_OFF_ARRAY(SAVE, 15),
+     CSR_OFF(TID),
+-    CSR_OFF_FUNCS(TCFG, CSRFL_IO, NULL, gen_helper_csrwr_tcfg),
+-    CSR_OFF_FUNCS(TVAL, CSRFL_READONLY | CSRFL_IO, gen_helper_csrrd_tval, NULL),
++    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
++    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
+     CSR_OFF(CNTC),
+-    CSR_OFF_FUNCS(TICLR, CSRFL_IO, NULL, gen_helper_csrwr_ticlr),
++    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
+     CSR_OFF(LLBCTL),
+     CSR_OFF(IMPCTL1),
+     CSR_OFF(IMPCTL2),
+--
+.43.5

-[PULL 5/5] target/loongarch: Fix CSR.DMW0-3.VSEG check
+[PULL 3/7] target/loongarch: Add generic csr function type
-From: Jiajie Chen <c@jia.je>
+Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite
 is not used in non-TCG mode. Generic csr function type is added here
 with parameter void type, so that it passes to compile with non-TCG mode.
-The previous code checks whether the highest 16 bits of virtual address
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-equal to that of CSR.DMW0-3. This is incorrect according to the spec,
+---
-and is corrected to compare only the highest four bits instead.
+ .../tcg/insn_trans/trans_privileged.c.inc     | 27 ++++++++++++-------
 file changed, 17 insertions(+), 10 deletions(-)
-Signed-off-by: Jiajie Chen <c@jia.je>
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20230614065556.2397513-1-c@jia.je>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
  target/loongarch/tlb_helper.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/tlb_helper.c
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-+++ b/target/loongarch/tlb_helper.c
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
  typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
  typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
 +typedef void (*GenCSRFunc)(void);
  typedef struct {
      int offset;
      int flags;
 -    GenCSRRead readfn;
 -    GenCSRWrite writefn;
 +    GenCSRFunc readfn;
 +    GenCSRFunc writefn;
  } CSRInfo;
  enum {
@@ -XXX,XX +XXX,XX @@ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
          return false;
      }
-     plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
+-    csr->readfn = readfn;
--    base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS;
+-    csr->writefn = writefn;
-+    base_v = address >> R_CSR_DMW_VSEG_SHIFT;
++    csr->readfn = (GenCSRFunc)readfn;
-     /* Check direct map window */
++    csr->writefn = (GenCSRFunc)writefn;
-     for (int i = 0; i < 4; i++) {
+     return true;
--        base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS;
+ }
-+        base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
-         if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
+@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
-             *physical = dmw_va2pa(address);
+ {
-             *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+     TCGv dest;
      const CSRInfo *csr;
 +    GenCSRRead readfn;
      if (check_plv(ctx)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
      } else {
          check_csr_flags(ctx, csr, false);
          dest = gpr_dst(ctx, a->rd, EXT_NONE);
 -        if (csr->readfn) {
 -            csr->readfn(dest, tcg_env);
 +        readfn = (GenCSRRead)csr->readfn;
 +        if (readfn) {
 +            readfn(dest, tcg_env);
          } else {
              tcg_gen_ld_tl(dest, tcg_env, csr->offset);
          }
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
  {
      TCGv dest, src1;
      const CSRInfo *csr;
 +    GenCSRWrite writefn;
      if (check_plv(ctx)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
          return false;
      }
      src1 = gpr_src(ctx, a->rd, EXT_NONE);
 -    if (csr->writefn) {
 +    writefn = (GenCSRWrite)csr->writefn;
 +    if (writefn) {
          dest = gpr_dst(ctx, a->rd, EXT_NONE);
 -        csr->writefn(dest, tcg_env, src1);
 +        writefn(dest, tcg_env, src1);
      } else {
          dest = tcg_temp_new();
          tcg_gen_ld_tl(dest, tcg_env, csr->offset);
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
  {
      TCGv src1, mask, oldv, newv, temp;
      const CSRInfo *csr;
 +    GenCSRWrite writefn;
      if (check_plv(ctx)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
      tcg_gen_andc_tl(temp, oldv, mask);
      tcg_gen_or_tl(newv, newv, temp);
 -    if (csr->writefn) {
 -        csr->writefn(oldv, tcg_env, newv);
 +    writefn = (GenCSRWrite)csr->writefn;
 +    if (writefn) {
 +        writefn(oldv, tcg_env, newv);
      } else {
          tcg_gen_st_tl(newv, tcg_env, csr->offset);
      }
 --
-.39.1
+.43.5

-New patch
+[PULL 4/7] target/loongarch: Add common header file for CSR registers
+Common header file csr.h is added here, it can be used by both
+TCG mode and kvm mode.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+---
+ target/loongarch/csr.h                        | 25 +++++++++++++++++++
+ .../tcg/insn_trans/trans_privileged.c.inc     | 16 +-----------
+files changed, 26 insertions(+), 15 deletions(-)
+ create mode 100644 target/loongarch/csr.h
+diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/target/loongarch/csr.h
+@@ -XXX,XX +XXX,XX @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Copyright (c) 2025 Loongson Technology Corporation Limited
++ */
++
++#ifndef TARGET_LOONGARCH_CSR_H
++#define TARGET_LOONGARCH_CSR_H
++
++#include "cpu-csr.h"
++
++typedef void (*GenCSRFunc)(void);
++enum {
++    CSRFL_READONLY = (1 << 0),
++    CSRFL_EXITTB   = (1 << 1),
++    CSRFL_IO       = (1 << 2),
++};
++
++typedef struct {
++    int offset;
++    int flags;
++    GenCSRFunc readfn;
++    GenCSRFunc writefn;
++} CSRInfo;
++
++#endif /* TARGET_LOONGARCH_CSR_H */
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+@@ -XXX,XX +XXX,XX @@
+  * LoongArch translation routines for the privileged instructions.
+  */
+-#include "cpu-csr.h"
++#include "csr.h"
+ #ifdef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
+ typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
+ typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
+-typedef void (*GenCSRFunc)(void);
+-
+-typedef struct {
+-    int offset;
+-    int flags;
+-    GenCSRFunc readfn;
+-    GenCSRFunc writefn;
+-} CSRInfo;
+-
+-enum {
+-    CSRFL_READONLY = (1 << 0),
+-    CSRFL_EXITTB   = (1 << 1),
+-    CSRFL_IO       = (1 << 2),
+-};
+ #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
+     [LOONGARCH_CSR_##NAME] = {                             \
+--
+.43.5

-[PULL 3/5] hw/loongarch: Add numa support
+[PULL 5/7] target/loongarch: Add common source file for CSR register
-From: Tianrui Zhao <zhaotianrui@loongson.cn>
+Common source file csr.c is added here, it can be used by both
 TCG mode and kvm mode. The common code is removed from file
 tcg/insn_trans/trans_privileged.c.inc to csrc.c
-. Implement some functions for LoongArch numa support;
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-. Implement fdt_add_memory_node() for fdt;
+---
-. build_srat() fills node_id and adds build numa memory.
+ target/loongarch/csr.c                        | 114 ++++++++++++++++++
  target/loongarch/csr.h                        |   1 +
  target/loongarch/meson.build                  |   1 +
  .../tcg/insn_trans/trans_privileged.c.inc     | 107 ----------------
 files changed, 116 insertions(+), 107 deletions(-)
  create mode 100644 target/loongarch/csr.c
-Reviewed-by: Song Gao <gaosong@loongson.cn>
+diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
-Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
+new file mode 100644
-Signed-off-by: Song Gao <gaosong@loongson.cn>
+index XXXXXXX..XXXXXXX
-Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn>
+--- /dev/null
----
++++ b/target/loongarch/csr.c
- hw/loongarch/Kconfig      |   1 +
+@@ -XXX,XX +XXX,XX @@
- hw/loongarch/acpi-build.c |  60 +++++++++++++++++-----
++/* SPDX-License-Identifier: GPL-2.0-or-later */
- hw/loongarch/virt.c       | 102 +++++++++++++++++++++++++++++++++-----
++/*
-files changed, 139 insertions(+), 24 deletions(-)
++ * Copyright (c) 2025 Loongson Technology Corporation Limited
++ */
-diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
++#include <stddef.h>
 +#include "qemu/osdep.h"
 +#include "cpu.h"
 +#include "csr.h"
 +
 +#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
 +    [LOONGARCH_CSR_##NAME] = {                             \
 +        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
 +        .flags = FL, .readfn = RD, .writefn = WR           \
 +    }
 +
 +#define CSR_OFF_ARRAY(NAME, N)                                \
 +    [LOONGARCH_CSR_##NAME(N)] = {                             \
 +        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
 +        .flags = 0, .readfn = NULL, .writefn = NULL           \
 +    }
 +
 +#define CSR_OFF_FLAGS(NAME, FL)   CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
 +#define CSR_OFF(NAME)             CSR_OFF_FLAGS(NAME, 0)
 +
 +static CSRInfo csr_info[] = {
 +    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
 +    CSR_OFF(PRMD),
 +    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
 +    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
 +    CSR_OFF(ECFG),
 +    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
 +    CSR_OFF(ERA),
 +    CSR_OFF(BADV),
 +    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
 +    CSR_OFF(EENTRY),
 +    CSR_OFF(TLBIDX),
 +    CSR_OFF(TLBEHI),
 +    CSR_OFF(TLBELO0),
 +    CSR_OFF(TLBELO1),
 +    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
 +    CSR_OFF(PGDL),
 +    CSR_OFF(PGDH),
 +    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
 +    CSR_OFF(PWCL),
 +    CSR_OFF(PWCH),
 +    CSR_OFF(STLBPS),
 +    CSR_OFF(RVACFG),
 +    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
 +    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
 +    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
 +    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
 +    CSR_OFF_ARRAY(SAVE, 0),
 +    CSR_OFF_ARRAY(SAVE, 1),
 +    CSR_OFF_ARRAY(SAVE, 2),
 +    CSR_OFF_ARRAY(SAVE, 3),
 +    CSR_OFF_ARRAY(SAVE, 4),
 +    CSR_OFF_ARRAY(SAVE, 5),
 +    CSR_OFF_ARRAY(SAVE, 6),
 +    CSR_OFF_ARRAY(SAVE, 7),
 +    CSR_OFF_ARRAY(SAVE, 8),
 +    CSR_OFF_ARRAY(SAVE, 9),
 +    CSR_OFF_ARRAY(SAVE, 10),
 +    CSR_OFF_ARRAY(SAVE, 11),
 +    CSR_OFF_ARRAY(SAVE, 12),
 +    CSR_OFF_ARRAY(SAVE, 13),
 +    CSR_OFF_ARRAY(SAVE, 14),
 +    CSR_OFF_ARRAY(SAVE, 15),
 +    CSR_OFF(TID),
 +    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
 +    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
 +    CSR_OFF(CNTC),
 +    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
 +    CSR_OFF(LLBCTL),
 +    CSR_OFF(IMPCTL1),
 +    CSR_OFF(IMPCTL2),
 +    CSR_OFF(TLBRENTRY),
 +    CSR_OFF(TLBRBADV),
 +    CSR_OFF(TLBRERA),
 +    CSR_OFF(TLBRSAVE),
 +    CSR_OFF(TLBRELO0),
 +    CSR_OFF(TLBRELO1),
 +    CSR_OFF(TLBREHI),
 +    CSR_OFF(TLBRPRMD),
 +    CSR_OFF(MERRCTL),
 +    CSR_OFF(MERRINFO1),
 +    CSR_OFF(MERRINFO2),
 +    CSR_OFF(MERRENTRY),
 +    CSR_OFF(MERRERA),
 +    CSR_OFF(MERRSAVE),
 +    CSR_OFF(CTAG),
 +    CSR_OFF_ARRAY(DMW, 0),
 +    CSR_OFF_ARRAY(DMW, 1),
 +    CSR_OFF_ARRAY(DMW, 2),
 +    CSR_OFF_ARRAY(DMW, 3),
 +    CSR_OFF(DBG),
 +    CSR_OFF(DERA),
 +    CSR_OFF(DSAVE),
 +};
 +
 +CSRInfo *get_csr(unsigned int csr_num)
 +{
 +    CSRInfo *csr;
 +
 +    if (csr_num >= ARRAY_SIZE(csr_info)) {
 +        return NULL;
 +    }
 +
 +    csr = &csr_info[csr_num];
 +    if (csr->offset == 0) {
 +        return NULL;
 +    }
 +
 +    return csr;
 +}
 diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/Kconfig
+--- a/target/loongarch/csr.h
-+++ b/hw/loongarch/Kconfig
++++ b/target/loongarch/csr.h
-@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-     select FW_CFG_DMA
+     GenCSRFunc writefn;
-     select DIMM
+ } CSRInfo;
-     select PFLASH_CFI01
-+    select ACPI_HMAT
++CSRInfo *get_csr(unsigned int csr_num);
-diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
+ #endif /* TARGET_LOONGARCH_CSR_H */
 diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/acpi-build.c
+--- a/target/loongarch/meson.build
-+++ b/hw/loongarch/acpi-build.c
++++ b/target/loongarch/meson.build
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ loongarch_system_ss = ss.source_set()
- #include "sysemu/tpm.h"
+ loongarch_system_ss.add(files(
- #include "hw/platform-bus.h"
+   'arch_dump.c',
- #include "hw/acpi/aml-build.h"
+   'cpu_helper.c',
-+#include "hw/acpi/hmat.h"
++  'csr.c',
+   'loongarch-qmp-cmds.c',
- #define ACPI_BUILD_ALIGN_SIZE             0x1000
+   'machine.c',
- #define ACPI_BUILD_TABLE_SIZE             0x20000
+ ))
-@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
- static void
+index XXXXXXX..XXXXXXX 100644
- build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
  typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
  typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
 -#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
 -    [LOONGARCH_CSR_##NAME] = {                             \
 -        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
 -        .flags = FL, .readfn = RD, .writefn = WR           \
 -    }
 -
 -#define CSR_OFF_ARRAY(NAME, N)                                \
 -    [LOONGARCH_CSR_##NAME(N)] = {                             \
 -        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
 -        .flags = 0, .readfn = NULL, .writefn = NULL           \
 -    }
 -
 -#define CSR_OFF_FLAGS(NAME, FL) \
 -    CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
 -
 -#define CSR_OFF(NAME) \
 -    CSR_OFF_FLAGS(NAME, 0)
 -
 -static CSRInfo csr_info[] = {
 -    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
 -    CSR_OFF(PRMD),
 -    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
 -    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
 -    CSR_OFF(ECFG),
 -    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
 -    CSR_OFF(ERA),
 -    CSR_OFF(BADV),
 -    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
 -    CSR_OFF(EENTRY),
 -    CSR_OFF(TLBIDX),
 -    CSR_OFF(TLBEHI),
 -    CSR_OFF(TLBELO0),
 -    CSR_OFF(TLBELO1),
 -    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
 -    CSR_OFF(PGDL),
 -    CSR_OFF(PGDH),
 -    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
 -    CSR_OFF(PWCL),
 -    CSR_OFF(PWCH),
 -    CSR_OFF(STLBPS),
 -    CSR_OFF(RVACFG),
 -    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
 -    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
 -    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
 -    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
 -    CSR_OFF_ARRAY(SAVE, 0),
 -    CSR_OFF_ARRAY(SAVE, 1),
 -    CSR_OFF_ARRAY(SAVE, 2),
 -    CSR_OFF_ARRAY(SAVE, 3),
 -    CSR_OFF_ARRAY(SAVE, 4),
 -    CSR_OFF_ARRAY(SAVE, 5),
 -    CSR_OFF_ARRAY(SAVE, 6),
 -    CSR_OFF_ARRAY(SAVE, 7),
 -    CSR_OFF_ARRAY(SAVE, 8),
 -    CSR_OFF_ARRAY(SAVE, 9),
 -    CSR_OFF_ARRAY(SAVE, 10),
 -    CSR_OFF_ARRAY(SAVE, 11),
 -    CSR_OFF_ARRAY(SAVE, 12),
 -    CSR_OFF_ARRAY(SAVE, 13),
 -    CSR_OFF_ARRAY(SAVE, 14),
 -    CSR_OFF_ARRAY(SAVE, 15),
 -    CSR_OFF(TID),
 -    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
 -    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
 -    CSR_OFF(CNTC),
 -    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
 -    CSR_OFF(LLBCTL),
 -    CSR_OFF(IMPCTL1),
 -    CSR_OFF(IMPCTL2),
 -    CSR_OFF(TLBRENTRY),
 -    CSR_OFF(TLBRBADV),
 -    CSR_OFF(TLBRERA),
 -    CSR_OFF(TLBRSAVE),
 -    CSR_OFF(TLBRELO0),
 -    CSR_OFF(TLBRELO1),
 -    CSR_OFF(TLBREHI),
 -    CSR_OFF(TLBRPRMD),
 -    CSR_OFF(MERRCTL),
 -    CSR_OFF(MERRINFO1),
 -    CSR_OFF(MERRINFO2),
 -    CSR_OFF(MERRENTRY),
 -    CSR_OFF(MERRERA),
 -    CSR_OFF(MERRSAVE),
 -    CSR_OFF(CTAG),
 -    CSR_OFF_ARRAY(DMW, 0),
 -    CSR_OFF_ARRAY(DMW, 1),
 -    CSR_OFF_ARRAY(DMW, 2),
 -    CSR_OFF_ARRAY(DMW, 3),
 -    CSR_OFF(DBG),
 -    CSR_OFF(DERA),
 -    CSR_OFF(DSAVE),
 -};
 -
  static bool check_plv(DisasContext *ctx)
  {
--    int i, arch_id;
+     if (ctx->plv == MMU_PLV_USER) {
-+    int i, arch_id, node_id;
+@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
-+    uint64_t mem_len, mem_base;
+     return false;
 +    int nb_numa_nodes = machine->numa_state->num_nodes;
      LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
 -    MachineState *ms = MACHINE(lams);
 -    MachineClass *mc = MACHINE_GET_CLASS(ms);
 -    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
 +    MachineClass *mc = MACHINE_GET_CLASS(lams);
 +    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
      AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
                          .oem_table_id = lams->oem_table_id };
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
      for (i = 0; i < arch_ids->len; ++i) {
          arch_id = arch_ids->cpus[i].arch_id;
 +        node_id = arch_ids->cpus[i].props.node_id;
          /* Processor Local APIC/SAPIC Affinity Structure */
          build_append_int_noprefix(table_data, 0, 1);  /* Type  */
          build_append_int_noprefix(table_data, 16, 1); /* Length */
          /* Proximity Domain [7:0] */
 -        build_append_int_noprefix(table_data, 0, 1);
 +        build_append_int_noprefix(table_data, node_id, 1);
          build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */
          /* Flags, Table 5-36 */
          build_append_int_noprefix(table_data, 1, 4);
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
          build_append_int_noprefix(table_data, 0, 4); /* Reserved */
      }
 +    /* Node0 */
      build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE,
 , MEM_AFFINITY_ENABLED);
 +    mem_base = VIRT_HIGHMEM_BASE;
 +    if (!nb_numa_nodes) {
 +        mem_len = machine->ram_size - VIRT_LOWMEM_SIZE;
 +    } else {
 +        mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE;
 +    }
 +    if (mem_len)
 +        build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_ENABLED);
 +
 +    /* Node1 - Nodemax */
 +    if (nb_numa_nodes) {
 +        mem_base += mem_len;
 +        for (i = 1; i < nb_numa_nodes; ++i) {
 +            if (machine->numa_state->nodes[i].node_mem > 0) {
 +                build_srat_memory(table_data, mem_base,
 +                                  machine->numa_state->nodes[i].node_mem, i,
 +                                  MEM_AFFINITY_ENABLED);
 +                mem_base += machine->numa_state->nodes[i].node_mem;
 +            }
 +        }
 +    }
 -    build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - VIRT_LOWMEM_SIZE,
 -                      0, MEM_AFFINITY_ENABLED);
 -
 -    if (ms->device_memory) {
 -        build_srat_memory(table_data, ms->device_memory->base,
 -                          memory_region_size(&ms->device_memory->mr),
 -                          0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
 +    if (machine->device_memory) {
 +        build_srat_memory(table_data, machine->device_memory->base,
 +                          memory_region_size(&machine->device_memory->mr),
 +                          nb_numa_nodes - 1,
 +                          MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
      }
      acpi_table_end(linker, &table);
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
      acpi_add_table(table_offsets, tables_blob);
      build_srat(tables_blob, tables->linker, machine);
 +    if (machine->numa_state->num_nodes) {
 +        if (machine->numa_state->have_numa_distance) {
 +            acpi_add_table(table_offsets, tables_blob);
 +            build_slit(tables_blob, tables->linker, machine, lams->oem_id,
 +                       lams->oem_table_id);
 +        }
 +        if (machine->numa_state->hmat_enabled) {
 +            acpi_add_table(table_offsets, tables_blob);
 +            build_hmat(tables_blob, tables->linker, machine->numa_state,
 +                       lams->oem_id, lams->oem_table_id);
 +        }
 +    }
 +
      acpi_add_table(table_offsets, tables_blob);
      {
          AcpiMcfgInfo mcfg = {
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/loongarch/virt.c
 +++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
      for (num = smp_cpus - 1; num >= 0; num--) {
          char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
          LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
 +        CPUState *cs = CPU(cpu);
          qemu_fdt_add_subnode(ms->fdt, nodename);
          qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
          qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
                                  cpu->dtb_compatible);
 +        if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
 +            qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
 +                ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
 +        }
          qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
          qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
                                qemu_fdt_alloc_phandle(ms->fdt));
@@ -XXX,XX +XXX,XX @@ static void fdt_add_irqchip_node(LoongArchMachineState *lams)
      g_free(nodename);
  }
-+static void fdt_add_memory_node(MachineState *ms,
+-static CSRInfo *get_csr(unsigned csr_num)
-+                                uint64_t base, uint64_t size, int node_id)
+-{
-+{
+-    CSRInfo *csr;
-+    char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
+-
-+
+-    if (csr_num >= ARRAY_SIZE(csr_info)) {
-+    qemu_fdt_add_subnode(ms->fdt, nodename);
+-        return NULL;
-+    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
+-    }
-+    qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
+-    csr = &csr_info[csr_num];
-+
+-    if (csr->offset == 0) {
-+    if (ms->numa_state && ms->numa_state->num_nodes) {
+-        return NULL;
-+        qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id);
+-    }
-+    }
+-    return csr;
-+
+-}
-+    g_free(nodename);
+-
-+}
+ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
-+
+                                GenCSRWrite writefn)
  #define PM_BASE 0x10080000
  #define PM_SIZE 0x100
  #define PM_CTRL 0x10
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
      const char *cpu_model = machine->cpu_type;
      ram_addr_t offset = 0;
      ram_addr_t ram_size = machine->ram_size;
 -    uint64_t highram_size = 0;
 +    uint64_t highram_size = 0, phyAddr = 0;
      MemoryRegion *address_space_mem = get_system_memory();
      LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
 +    int nb_numa_nodes = machine->numa_state->num_nodes;
 +    NodeInfo *numa_info = machine->numa_state->nodes;
      int i;
      hwaddr fdt_base;
      const CPUArchIdList *possible_cpus;
      MachineClass *mc = MACHINE_GET_CLASS(machine);
      CPUState *cpu;
 +    char *ramName = NULL;
      if (!cpu_model) {
          cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
          machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
      }
      fdt_add_cpu_nodes(lams);
 -    /* Add memory region */
 -    memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
 -                             machine->ram, 0, 256 * MiB);
 -    memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
 -    offset += 256 * MiB;
 -    memmap_add_entry(0, 256 * MiB, 1);
 -    highram_size = ram_size - 256 * MiB;
 -    memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
 -                             machine->ram, offset, highram_size);
 -    memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
 -    memmap_add_entry(0x90000000, highram_size, 1);
 +
 +    /* Node0 memory */
 +    memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
 +    fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
 +    memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram",
 +                             machine->ram, offset, VIRT_LOWMEM_SIZE);
 +    memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem);
 +
 +    offset += VIRT_LOWMEM_SIZE;
 +    if (nb_numa_nodes > 0) {
 +        assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
 +        highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
 +    } else {
 +        highram_size = ram_size - VIRT_LOWMEM_SIZE;
 +    }
 +    phyAddr = VIRT_HIGHMEM_BASE;
 +    memmap_add_entry(phyAddr, highram_size, 1);
 +    fdt_add_memory_node(machine, phyAddr, highram_size, 0);
 +    memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram",
 +                              machine->ram, offset, highram_size);
 +    memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem);
 +
 +    /* Node1 - Nodemax memory */
 +    offset += highram_size;
 +    phyAddr += highram_size;
 +
 +    for (i = 1; i < nb_numa_nodes; i++) {
 +        MemoryRegion *nodemem = g_new(MemoryRegion, 1);
 +        ramName = g_strdup_printf("loongarch.node%d.ram", i);
 +        memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
 +                                 offset,  numa_info[i].node_mem);
 +        memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
 +        memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
 +        fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
 +        offset += numa_info[i].node_mem;
 +        phyAddr += numa_info[i].node_mem;
 +    }
      /* initialize device memory address space */
      if (machine->ram_size < machine->maxram_size) {
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
      return ms->possible_cpus;
  }
 +static CpuInstanceProperties
 +virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 +{
 +    MachineClass *mc = MACHINE_GET_CLASS(ms);
 +    const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
 +
 +    assert(cpu_index < possible_cpus->len);
 +    return possible_cpus->cpus[cpu_index].props;
 +}
 +
 +static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
 +{
 +    int64_t nidx = 0;
 +
 +    if (ms->numa_state->num_nodes) {
 +        nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
 +        if (ms->numa_state->num_nodes <= nidx) {
 +            nidx = ms->numa_state->num_nodes - 1;
 +        }
 +    }
 +    return nidx;
 +}
 +
  static void loongarch_class_init(ObjectClass *oc, void *data)
  {
-     MachineClass *mc = MACHINE_CLASS(oc);
-@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
-     mc->default_boot_order = "c";
-     mc->no_cdrom = 1;
-     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
-+    mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
-+    mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
-+    mc->numa_mem_supported = true;
-+    mc->auto_enable_numa_with_memhp = true;
-+    mc->auto_enable_numa_with_memdev = true;
-     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
-     mc->default_nic = "virtio-net-pci";
-     hc->plug = loongarch_machine_device_plug_cb;
 --
-.39.1
+.43.5

-[PULL 1/5] hw/loongarch/virt: Add cpu arch_id support
+[PULL 6/7] target/loongarch: Set unused flag with CSR registers
-From: Tianrui Zhao <zhaotianrui@loongson.cn>
+On LA464, some CSR registers are not used such as CSR_SAVE8 -
 CSR_SAVE15, also CSR registers relative with MCE is not used now.
-With acpi madt table, there is cpu physical coreid, which may
+Flag CSRFL_UNUSED is added for these registers, so that it will
-be different with logical id in qemu. This patch adds cpu arch_id
+not dumped. In order to keep compatiblity, these CSR registers are
-support, and fill madt table with arch_id. For the present cpu
+not removed since it is used in vmstate already.
 arch_id is still equal to logical id.
-Reviewed-by: Song Gao <gaosong@loongson.cn>
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
 Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20230613120552.2471420-2-zhaotianrui@loongson.cn>
 ---
- hw/loongarch/acpi-build.c | 20 ++++++++++++++------
+ target/loongarch/cpu.c | 30 +++++++++++++++++++++++++++++-
- hw/loongarch/virt.c       | 34 ++++++++++++++++++++++++++++++++--
+ target/loongarch/csr.c | 13 +++++++++++++
-files changed, 46 insertions(+), 8 deletions(-)
+ target/loongarch/csr.h |  2 ++
 files changed, 44 insertions(+), 1 deletion(-)
-diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/acpi-build.c
+--- a/target/loongarch/cpu.c
-+++ b/hw/loongarch/acpi-build.c
++++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void
+@@ -XXX,XX +XXX,XX @@
- build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
+ #include "cpu.h"
  #include "internals.h"
  #include "fpu/softfloat-helpers.h"
 -#include "cpu-csr.h"
 +#include "csr.h"
  #ifndef CONFIG_USER_ONLY
  #include "system/reset.h"
  #endif
@@ -XXX,XX +XXX,XX @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
      return MMU_DA_IDX;
  }
 +static void loongarch_la464_init_csr(Object *obj)
 +{
 +#ifndef CONFIG_USER_ONLY
 +    static bool initialized;
 +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 +    CPULoongArchState *env = &cpu->env;
 +    int i, num;
 +
 +    if (!initialized) {
 +        initialized = true;
 +        num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM);
 +        for (i = num; i < 16; i++) {
 +            set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED);
 +        }
 +        set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED);
 +    }
 +#endif
 +}
 +
  static void loongarch_la464_initfn(Object *obj)
  {
-     MachineState *ms = MACHINE(lams);
+     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
--    int i;
+@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
-+    MachineClass *mc = MACHINE_GET_CLASS(ms);
+     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
-+    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
-+    int i, arch_id;
-     AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id,
++    loongarch_la464_init_csr(obj);
-                         .oem_table_id = lams->oem_table_id };
+     loongarch_cpu_post_init(obj);
+ }
-@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
-     build_append_int_noprefix(table_data, 0, 4);
+diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
-     build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/csr.c
--    for (i = 0; i < ms->smp.cpus; i++) {
++++ b/target/loongarch/csr.c
-+    for (i = 0; i < arch_ids->len; i++) {
+@@ -XXX,XX +XXX,XX @@ CSRInfo *get_csr(unsigned int csr_num)
-         /* Processor Core Interrupt Controller Structure */
-+        arch_id = arch_ids->cpus[i].arch_id;
+     return csr;
  }
 +
-         build_append_int_noprefix(table_data, 17, 1);    /* Type */
++bool set_csr_flag(unsigned int csr_num, int flag)
-         build_append_int_noprefix(table_data, 15, 1);    /* Length */
++{
-         build_append_int_noprefix(table_data, 1, 1);     /* Version */
++    CSRInfo *csr;
          build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */
 -        build_append_int_noprefix(table_data, i, 4);     /* Core ID */
 +        build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */
          build_append_int_noprefix(table_data, 1, 4);     /* Flags */
      }
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
  static void
  build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
  {
 -    uint64_t i;
 +    int i, arch_id;
      LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
      MachineState *ms = MACHINE(lams);
 +    MachineClass *mc = MACHINE_GET_CLASS(ms);
 +    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
      AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
                          .oem_table_id = lams->oem_table_id };
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
      build_append_int_noprefix(table_data, 1, 4); /* Reserved */
      build_append_int_noprefix(table_data, 0, 8); /* Reserved */
 -    for (i = 0; i < ms->smp.cpus; ++i) {
 +    for (i = 0; i < arch_ids->len; ++i) {
 +        arch_id = arch_ids->cpus[i].arch_id;
 +
-         /* Processor Local APIC/SAPIC Affinity Structure */
++    csr = get_csr(csr_num);
-         build_append_int_noprefix(table_data, 0, 1);  /* Type  */
++    if (!csr) {
-         build_append_int_noprefix(table_data, 16, 1); /* Length */
++        return false;
          /* Proximity Domain [7:0] */
          build_append_int_noprefix(table_data, 0, 1);
 -        build_append_int_noprefix(table_data, i, 1); /* APIC ID */
 +        build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */
          /* Flags, Table 5-36 */
          build_append_int_noprefix(table_data, 1, 4);
          build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/loongarch/virt.c
 +++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
      LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
      int i;
      hwaddr fdt_base;
 +    const CPUArchIdList *possible_cpus;
 +    MachineClass *mc = MACHINE_GET_CLASS(machine);
 +    CPUState *cpu;
      if (!cpu_model) {
          cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
      }
      create_fdt(lams);
      /* Init CPUs */
 -    for (i = 0; i < machine->smp.cpus; i++) {
 -        cpu_create(machine->cpu_type);
 +
 +    possible_cpus = mc->possible_cpu_arch_ids(machine);
 +    for (i = 0; i < possible_cpus->len; i++) {
 +        cpu = cpu_create(machine->cpu_type);
 +        cpu->cpu_index = i;
 +        machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
      }
      fdt_add_cpu_nodes(lams);
      /* Add memory region */
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
      return NULL;
  }
 +static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
 +{
 +    int n;
 +    unsigned int max_cpus = ms->smp.max_cpus;
 +
 +    if (ms->possible_cpus) {
 +        assert(ms->possible_cpus->len == max_cpus);
 +        return ms->possible_cpus;
 +    }
 +
-+    ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
++    csr->flags |= flag;
-+                                  sizeof(CPUArchId) * max_cpus);
++    return true;
 +    ms->possible_cpus->len = max_cpus;
 +    for (n = 0; n < ms->possible_cpus->len; n++) {
 +        ms->possible_cpus->cpus[n].type = ms->cpu_type;
 +        ms->possible_cpus->cpus[n].arch_id = n;
 +        ms->possible_cpus->cpus[n].props.has_core_id = true;
 +        ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;
 +    }
 +    return ms->possible_cpus;
 +}
-+
+diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
- static void loongarch_class_init(ObjectClass *oc, void *data)
+index XXXXXXX..XXXXXXX 100644
- {
+--- a/target/loongarch/csr.h
-     MachineClass *mc = MACHINE_CLASS(oc);
++++ b/target/loongarch/csr.h
-@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ enum {
-     mc->block_default_type = IF_VIRTIO;
+     CSRFL_READONLY = (1 << 0),
-     mc->default_boot_order = "c";
+     CSRFL_EXITTB   = (1 << 1),
-     mc->no_cdrom = 1;
+     CSRFL_IO       = (1 << 2),
-+    mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
++    CSRFL_UNUSED   = (1 << 3),
-     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
+ };
-     mc->default_nic = "virtio-net-pci";
-     hc->plug = loongarch_machine_device_plug_cb;
+ typedef struct {
@@ -XXX,XX +XXX,XX @@ typedef struct {
  } CSRInfo;
  CSRInfo *get_csr(unsigned int csr_num);
 +bool set_csr_flag(unsigned int csr_num, int flag);
  #endif /* TARGET_LOONGARCH_CSR_H */
 --
-.39.1
+.43.5

-[PULL 2/5] hw/intc: Set physical cpuid route for LoongArch ipi device
+[PULL 7/7] target/loongarch: Dump all generic CSR registers
-From: Tianrui Zhao <zhaotianrui@loongson.cn>
+CSR registers is import system control registers, it had better
 dump all CSR registers when VM is running in system mode.
-LoongArch ipi device uses physical cpuid to route to different
+Here is dump output example of CSR registers:
-vcpus rather logical cpuid, and the physical cpuid is the same
+ CSR000: CRMD   b4               PRMD   4                EUEN   0                MISC   0
-with cpuid in acpi dsdt and srat table.
+ CSR004: ECFG   71c1c            ESTAT  0                ERA    9000000002c31300 BADV   12022c0e0
  CSR008: BADI   2b0000
  CSR012: EENTRY 90000000046b0000
  CSR016: TLBIDX ffffffff8e000228 TLBEHI 120228000        TLBELO0 400000016f19001f TLBELO1 400000016f1a401f
  CSR024: ASID   a0004            PGDL   90000001016f0000 PGDH   9000000004680000 PGD    0
  CSR028: PWCL   5e56e            PWCH   2e4              STLBPS e                RVACFG 0
  CSR032: CPUID  0                PRCFG1 72f8             PRCFG2 3ffff000         PRCFG3 8073f2
  CSR048: SAVE0  0                SAVE1  af9c             SAVE2  12010d6a8        SAVE3  8300000
  CSR052: SAVE4  0                SAVE5  0                SAVE6  0                SAVE7  0
  CSR064: TID    0                TCFG   8f0ca15          TVAL   4cefd8b          CNTC   fffffffffe688aaa
  CSR068: TICLR  0
  CSR096: LLBCTL 1
  CSR136: TLBRENTRY 46ba000       TLBRBADV ffff8000130d81e2 TLBRERA 9000000003585cb8 TLBRSAVE ffff8000130d81e0
  CSR140: TLBRELO0 1fe00043       TLBRELO1 40             TLBREHI ffff8000130d800e TLBRPRMD 0
  CSR384: DMW0   8000000000000001 DMW1   9000000000000011 DMW2   0                DMW3   0
-Reviewed-by: Song Gao <gaosong@loongson.cn>
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
 Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++++-------
+ target/loongarch/cpu.c | 66 ++++++++++++++++++++++++++++++++----------
- hw/loongarch/virt.c     |  1 +
+ target/loongarch/csr.c |  2 ++
- target/loongarch/cpu.h  |  2 ++
+ target/loongarch/csr.h |  1 +
-files changed, 40 insertions(+), 7 deletions(-)
+files changed, 53 insertions(+), 16 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/target/loongarch/cpu.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
- #include "target/loongarch/internals.h"
+     return oc;
- #include "trace.h"
+ }
-+static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned);
++static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f)
 +{
 +#ifndef CONFIG_USER_ONLY
 +    CPULoongArchState *env = cpu_env(cs);
 +    CSRInfo *csr_info;
 +    int64_t *addr;
 +    int i, j, len, col = 0;
 +
- static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
++    qemu_fprintf(f, "\n");
  {
      IPICore *s = opaque;
@@ -XXX,XX +XXX,XX @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
                        data, MEMTXATTRS_UNSPECIFIED, NULL);
  }
 +static int archid_cmp(const void *a, const void *b)
 +{
 +   CPUArchId *archid_a = (CPUArchId *)a;
 +   CPUArchId *archid_b = (CPUArchId *)b;
 +
-+   return archid_a->arch_id - archid_b->arch_id;
++    /* Dump all generic CSR register */
 +    for (i = 0; i < LOONGARCH_CSR_DBG; i++) {
 +        csr_info = get_csr(i);
 +        if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) {
 +            if (i == (col + 3)) {
 +                qemu_fprintf(f, "\n");
 +            }
 +
 +            continue;
 +        }
 +
 +        if ((i >  (col + 3)) || (i == col)) {
 +            col = i & ~3;
 +            qemu_fprintf(f, " CSR%03d:", col);
 +        }
 +
 +        addr = (void *)env + csr_info->offset;
 +        qemu_fprintf(f, " %s ", csr_info->name);
 +        len = strlen(csr_info->name);
 +        for (; len < 6; len++) {
 +            qemu_fprintf(f, " ");
 +        }
 +
 +        qemu_fprintf(f, "%" PRIx64, *addr);
 +        j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1);
 +        len += j / 4 + 1;
 +        for (; len < 22; len++) {
 +                qemu_fprintf(f, " ");
 +        }
 +
 +        if (i == (col + 3)) {
 +            qemu_fprintf(f, "\n");
 +        }
 +    }
 +    qemu_fprintf(f, "\n");
 +#endif
 +}
 +
-+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 +{
 +    CPUArchId apic_id, *found_cpu;
 +
 +    apic_id.arch_id = id;
 +    found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
 +        ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
 +        archid_cmp);
 +
 +    return found_cpu;
 +}
 +
 +static CPUState *ipi_getcpu(int arch_id)
 +{
 +    MachineState *machine = MACHINE(qdev_get_machine());
 +    CPUArchId *archid;
 +
 +    archid = find_cpu_by_archid(machine, arch_id);
 +    return CPU(archid->cpu);
 +}
 +
  static void ipi_send(uint64_t val)
  {
-     uint32_t cpuid;
+     CPULoongArchState *env = cpu_env(cs);
-     uint8_t vector;
+@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
--    CPULoongArchState *env;
+         }
      CPUState *cs;
      LoongArchCPU *cpu;
 +    LoongArchIPI *s;
      cpuid = extract32(val, 16, 10);
      if (cpuid >= LOONGARCH_MAX_CPUS) {
@@ -XXX,XX +XXX,XX @@ static void ipi_send(uint64_t val)
      /* IPI status vector */
      vector = extract8(val, 0, 5);
 -    cs = qemu_get_cpu(cpuid);
 +    cs = ipi_getcpu(cpuid);
      cpu = LOONGARCH_CPU(cs);
 -    env = &cpu->env;
 -    address_space_stl(&env->address_space_iocsr, 0x1008,
 -                      BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);
 +    s = LOONGARCH_IPI(cpu->env.ipistate);
 +    loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4);
  }
  static void mail_send(uint64_t val)
@@ -XXX,XX +XXX,XX @@ static void mail_send(uint64_t val)
      }
-     addr = 0x1020 + (val & 0x1c);
+-    qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
--    cs = qemu_get_cpu(cpuid);
+-    qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
-+    cs = ipi_getcpu(cpuid);
+-    qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
-     cpu = LOONGARCH_CPU(cs);
+-    qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
-     env = &cpu->env;
+-    qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
-     send_ipi_data(env, val, addr);
+-    qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
-@@ -XXX,XX +XXX,XX @@ static void any_send(uint64_t val)
+-    qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
 -    qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
 -    qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
 -                 " PRCFG3=%016" PRIx64 "\n",
 -                 env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
 -    qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
 -    qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
 -    qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
 -    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
 -    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
 +    /* csr */
 +    loongarch_cpu_dump_csr(cs, f);
      /* fpr */
      if (flags & CPU_DUMP_FPU) {
 diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/csr.c
 +++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@
  #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
      [LOONGARCH_CSR_##NAME] = {                             \
 +        .name   = (stringify(NAME)),                       \
          .offset = offsetof(CPULoongArchState, CSR_##NAME), \
          .flags = FL, .readfn = RD, .writefn = WR           \
      }
-     addr = val & 0xffff;
+ #define CSR_OFF_ARRAY(NAME, N)                                \
--    cs = qemu_get_cpu(cpuid);
+     [LOONGARCH_CSR_##NAME(N)] = {                             \
-+    cs = ipi_getcpu(cpuid);
++        .name   = (stringify(NAME##N)),                       \
-     cpu = LOONGARCH_CPU(cs);
+         .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
-     env = &cpu->env;
+         .flags = 0, .readfn = NULL, .writefn = NULL           \
-     send_ipi_data(env, val, addr);
+     }
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
+diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/target/loongarch/csr.h
-+++ b/hw/loongarch/virt.c
++++ b/target/loongarch/csr.h
-@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
+@@ -XXX,XX +XXX,XX @@ enum {
-             memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
+ };
-                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
-                                 cpu));
+ typedef struct {
-+        env->ipistate = ipi;
++    const char *name;
-     }
+     int offset;
+     int flags;
-     /*
+     GenCSRFunc readfn;
 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/cpu.h
 +++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
      MemoryRegion iocsr_mem;
      bool load_elf;
      uint64_t elf_address;
 +    /* Store ipistate to access from this struct */
 +    DeviceState *ipistate;
  #endif
  } CPULoongArchState;
 --
-.39.1
+.43.5

The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:

Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200)

are available in the Git repository at:

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230616

for you to fetch changes up to 505aa8d8f29b79fcef77563bb4124208badbd8d4:

target/loongarch: Fix CSR.DMW0-3.VSEG check (2023-06-16 17:58:46 +0800)

----------------------------------------------------------------
pull-loongarch-20230616

* Fix CSR.DMW0-3.VSEG check
* Add cpu arch_id support
* Set physical cpuid route for LoongArch ipi device
* Add numa support
* Supplement cpu topology arguments

----------------------------------------------------------------
Jiajie Chen (1):
      target/loongarch: Fix CSR.DMW0-3.VSEG check

Tianrui Zhao (4):
      hw/loongarch/virt: Add cpu arch_id support
      hw/intc: Set physical cpuid route for LoongArch ipi device
      hw/loongarch: Add numa support
      hw/loongarch: Supplement cpu topology arguments

hw/intc/loongarch_ipi.c       |  44 +++++++++++--
 hw/loongarch/Kconfig          |   1 +
 hw/loongarch/acpi-build.c     |  78 ++++++++++++++++++-----
 hw/loongarch/virt.c           | 144 ++++++++++++++++++++++++++++++++++++++----
 target/loongarch/cpu.h        |   2 +
 target/loongarch/tlb_helper.c |   4 +-
 6 files changed, 235 insertions(+), 38 deletions(-)

From: Tianrui Zhao <zhaotianrui@loongson.cn>

With acpi madt table, there is cpu physical coreid, which may
be different with logical id in qemu. This patch adds cpu arch_id
support, and fill madt table with arch_id. For the present cpu
arch_id is still equal to logical id.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230613120552.2471420-2-zhaotianrui@loongson.cn>
---
 hw/loongarch/acpi-build.c | 20 ++++++++++++++------
 hw/loongarch/virt.c       | 34 ++++++++++++++++++++++++++++++++--
 2 files changed, 46 insertions(+), 8 deletions(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -XXX,XX +XXX,XX @@ static void
 build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
 {
     MachineState *ms = MACHINE(lams);
-    int i;
+    MachineClass *mc = MACHINE_GET_CLASS(ms);
+    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+    int i, arch_id;
     AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id,
                         .oem_table_id = lams->oem_table_id };
 
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
     build_append_int_noprefix(table_data, 0, 4);
     build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
 
-    for (i = 0; i < ms->smp.cpus; i++) {
+    for (i = 0; i < arch_ids->len; i++) {
         /* Processor Core Interrupt Controller Structure */
+        arch_id = arch_ids->cpus[i].arch_id;
+
         build_append_int_noprefix(table_data, 17, 1);    /* Type */
         build_append_int_noprefix(table_data, 15, 1);    /* Length */
         build_append_int_noprefix(table_data, 1, 1);     /* Version */
         build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */
-        build_append_int_noprefix(table_data, i, 4);     /* Core ID */
+        build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */
         build_append_int_noprefix(table_data, 1, 4);     /* Flags */
     }
 
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
 static void
 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
 {
-    uint64_t i;
+    int i, arch_id;
     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
     MachineState *ms = MACHINE(lams);
+    MachineClass *mc = MACHINE_GET_CLASS(ms);
+    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
     AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
                         .oem_table_id = lams->oem_table_id };
 
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
     build_append_int_noprefix(table_data, 1, 4); /* Reserved */
     build_append_int_noprefix(table_data, 0, 8); /* Reserved */
 
-    for (i = 0; i < ms->smp.cpus; ++i) {
+    for (i = 0; i < arch_ids->len; ++i) {
+        arch_id = arch_ids->cpus[i].arch_id;
+
         /* Processor Local APIC/SAPIC Affinity Structure */
         build_append_int_noprefix(table_data, 0, 1);  /* Type  */
         build_append_int_noprefix(table_data, 16, 1); /* Length */
         /* Proximity Domain [7:0] */
         build_append_int_noprefix(table_data, 0, 1);
-        build_append_int_noprefix(table_data, i, 1); /* APIC ID */
+        build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */
         /* Flags, Table 5-36 */
         build_append_int_noprefix(table_data, 1, 4);
         build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
     int i;
     hwaddr fdt_base;
+    const CPUArchIdList *possible_cpus;
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+    CPUState *cpu;
 
     if (!cpu_model) {
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
     }
     create_fdt(lams);
     /* Init CPUs */
-    for (i = 0; i < machine->smp.cpus; i++) {
-        cpu_create(machine->cpu_type);
+
+    possible_cpus = mc->possible_cpu_arch_ids(machine);
+    for (i = 0; i < possible_cpus->len; i++) {
+        cpu = cpu_create(machine->cpu_type);
+        cpu->cpu_index = i;
+        machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
     }
     fdt_add_cpu_nodes(lams);
     /* Add memory region */
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
     return NULL;
 }
 
+static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
+{
+    int n;
+    unsigned int max_cpus = ms->smp.max_cpus;
+
+    if (ms->possible_cpus) {
+        assert(ms->possible_cpus->len == max_cpus);
+        return ms->possible_cpus;
+    }
+
+    ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
+                                  sizeof(CPUArchId) * max_cpus);
+    ms->possible_cpus->len = max_cpus;
+    for (n = 0; n < ms->possible_cpus->len; n++) {
+        ms->possible_cpus->cpus[n].type = ms->cpu_type;
+        ms->possible_cpus->cpus[n].arch_id = n;
+        ms->possible_cpus->cpus[n].props.has_core_id = true;
+        ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;
+    }
+    return ms->possible_cpus;
+}
+
 static void loongarch_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
     mc->block_default_type = IF_VIRTIO;
     mc->default_boot_order = "c";
     mc->no_cdrom = 1;
+    mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
     mc->default_nic = "virtio-net-pci";
     hc->plug = loongarch_machine_device_plug_cb;
-- 
2.39.1

From: Tianrui Zhao <zhaotianrui@loongson.cn>

LoongArch ipi device uses physical cpuid to route to different
vcpus rather logical cpuid, and the physical cpuid is the same
with cpuid in acpi dsdt and srat table.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn>
---
 hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++++-------
 hw/loongarch/virt.c     |  1 +
 target/loongarch/cpu.h  |  2 ++
 3 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@
 #include "target/loongarch/internals.h"
 #include "trace.h"
 
+static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned);
+
 static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
 {
     IPICore *s = opaque;
@@ -XXX,XX +XXX,XX @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
                       data, MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
+static int archid_cmp(const void *a, const void *b)
+{
+   CPUArchId *archid_a = (CPUArchId *)a;
+   CPUArchId *archid_b = (CPUArchId *)b;
+
+   return archid_a->arch_id - archid_b->arch_id;
+}
+
+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+{
+    CPUArchId apic_id, *found_cpu;
+
+    apic_id.arch_id = id;
+    found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
+        ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
+        archid_cmp);
+
+    return found_cpu;
+}
+
+static CPUState *ipi_getcpu(int arch_id)
+{
+    MachineState *machine = MACHINE(qdev_get_machine());
+    CPUArchId *archid;
+
+    archid = find_cpu_by_archid(machine, arch_id);
+    return CPU(archid->cpu);
+}
+
 static void ipi_send(uint64_t val)
 {
     uint32_t cpuid;
     uint8_t vector;
-    CPULoongArchState *env;
     CPUState *cs;
     LoongArchCPU *cpu;
+    LoongArchIPI *s;
 
     cpuid = extract32(val, 16, 10);
     if (cpuid >= LOONGARCH_MAX_CPUS) {
@@ -XXX,XX +XXX,XX @@ static void ipi_send(uint64_t val)
     /* IPI status vector */
     vector = extract8(val, 0, 5);
 
-    cs = qemu_get_cpu(cpuid);
+    cs = ipi_getcpu(cpuid);
     cpu = LOONGARCH_CPU(cs);
-    env = &cpu->env;
-    address_space_stl(&env->address_space_iocsr, 0x1008,
-                      BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);
+    s = LOONGARCH_IPI(cpu->env.ipistate);
+    loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4);
 }
 
 static void mail_send(uint64_t val)
@@ -XXX,XX +XXX,XX @@ static void mail_send(uint64_t val)
     }
 
     addr = 0x1020 + (val & 0x1c);
-    cs = qemu_get_cpu(cpuid);
+    cs = ipi_getcpu(cpuid);
     cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
     send_ipi_data(env, val, addr);
@@ -XXX,XX +XXX,XX @@ static void any_send(uint64_t val)
     }
 
     addr = val & 0xffff;
-    cs = qemu_get_cpu(cpuid);
+    cs = ipi_getcpu(cpuid);
     cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
     send_ipi_data(env, val, addr);
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
             memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
                                 cpu));
+        env->ipistate = ipi;
     }
 
     /*
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     MemoryRegion iocsr_mem;
     bool load_elf;
     uint64_t elf_address;
+    /* Store ipistate to access from this struct */
+    DeviceState *ipistate;
 #endif
 } CPULoongArchState;
 
-- 
2.39.1

From: Tianrui Zhao <zhaotianrui@loongson.cn>

1. Implement some functions for LoongArch numa support;
2. Implement fdt_add_memory_node() for fdt;
3. build_srat() fills node_id and adds build numa memory.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn>
---
 hw/loongarch/Kconfig      |   1 +
 hw/loongarch/acpi-build.c |  60 +++++++++++++++++-----
 hw/loongarch/virt.c       | 102 +++++++++++++++++++++++++++++++++-----
 3 files changed, 139 insertions(+), 24 deletions(-)

diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
     select FW_CFG_DMA
     select DIMM
     select PFLASH_CFI01
+    select ACPI_HMAT
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/tpm.h"
 #include "hw/platform-bus.h"
 #include "hw/acpi/aml-build.h"
+#include "hw/acpi/hmat.h"
 
 #define ACPI_BUILD_ALIGN_SIZE             0x1000
 #define ACPI_BUILD_TABLE_SIZE             0x20000
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
 static void
 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
 {
-    int i, arch_id;
+    int i, arch_id, node_id;
+    uint64_t mem_len, mem_base;
+    int nb_numa_nodes = machine->numa_state->num_nodes;
     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
-    MachineState *ms = MACHINE(lams);
-    MachineClass *mc = MACHINE_GET_CLASS(ms);
-    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+    MachineClass *mc = MACHINE_GET_CLASS(lams);
+    const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
     AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
                         .oem_table_id = lams->oem_table_id };
 
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
 
     for (i = 0; i < arch_ids->len; ++i) {
         arch_id = arch_ids->cpus[i].arch_id;
+        node_id = arch_ids->cpus[i].props.node_id;
 
         /* Processor Local APIC/SAPIC Affinity Structure */
         build_append_int_noprefix(table_data, 0, 1);  /* Type  */
         build_append_int_noprefix(table_data, 16, 1); /* Length */
         /* Proximity Domain [7:0] */
-        build_append_int_noprefix(table_data, 0, 1);
+        build_append_int_noprefix(table_data, node_id, 1);
         build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */
         /* Flags, Table 5-36 */
         build_append_int_noprefix(table_data, 1, 4);
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
         build_append_int_noprefix(table_data, 0, 4); /* Reserved */
     }
 
+    /* Node0 */
     build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE,
                       0, MEM_AFFINITY_ENABLED);
+    mem_base = VIRT_HIGHMEM_BASE;
+    if (!nb_numa_nodes) {
+        mem_len = machine->ram_size - VIRT_LOWMEM_SIZE;
+    } else {
+        mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE;
+    }
+    if (mem_len)
+        build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_ENABLED);
+
+    /* Node1 - Nodemax */
+    if (nb_numa_nodes) {
+        mem_base += mem_len;
+        for (i = 1; i < nb_numa_nodes; ++i) {
+            if (machine->numa_state->nodes[i].node_mem > 0) {
+                build_srat_memory(table_data, mem_base,
+                                  machine->numa_state->nodes[i].node_mem, i,
+                                  MEM_AFFINITY_ENABLED);
+                mem_base += machine->numa_state->nodes[i].node_mem;
+            }
+        }
+    }
 
-    build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - VIRT_LOWMEM_SIZE,
-                      0, MEM_AFFINITY_ENABLED);
-
-    if (ms->device_memory) {
-        build_srat_memory(table_data, ms->device_memory->base,
-                          memory_region_size(&ms->device_memory->mr),
-                          0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
+    if (machine->device_memory) {
+        build_srat_memory(table_data, machine->device_memory->base,
+                          memory_region_size(&machine->device_memory->mr),
+                          nb_numa_nodes - 1,
+                          MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
     }
 
     acpi_table_end(linker, &table);
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
     acpi_add_table(table_offsets, tables_blob);
     build_srat(tables_blob, tables->linker, machine);
 
+    if (machine->numa_state->num_nodes) {
+        if (machine->numa_state->have_numa_distance) {
+            acpi_add_table(table_offsets, tables_blob);
+            build_slit(tables_blob, tables->linker, machine, lams->oem_id,
+                       lams->oem_table_id);
+        }
+        if (machine->numa_state->hmat_enabled) {
+            acpi_add_table(table_offsets, tables_blob);
+            build_hmat(tables_blob, tables->linker, machine->numa_state,
+                       lams->oem_id, lams->oem_table_id);
+        }
+    }
+
     acpi_add_table(table_offsets, tables_blob);
     {
         AcpiMcfgInfo mcfg = {
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
     for (num = smp_cpus - 1; num >= 0; num--) {
         char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
         LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
+        CPUState *cs = CPU(cpu);
 
         qemu_fdt_add_subnode(ms->fdt, nodename);
         qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
                                 cpu->dtb_compatible);
+        if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
+            qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
+                ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
+        }
         qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
         qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
                               qemu_fdt_alloc_phandle(ms->fdt));
@@ -XXX,XX +XXX,XX @@ static void fdt_add_irqchip_node(LoongArchMachineState *lams)
     g_free(nodename);
 }
 
+static void fdt_add_memory_node(MachineState *ms,
+                                uint64_t base, uint64_t size, int node_id)
+{
+    char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
+
+    qemu_fdt_add_subnode(ms->fdt, nodename);
+    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
+    qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
+
+    if (ms->numa_state && ms->numa_state->num_nodes) {
+        qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id);
+    }
+
+    g_free(nodename);
+}
+
 #define PM_BASE 0x10080000
 #define PM_SIZE 0x100
 #define PM_CTRL 0x10
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
     const char *cpu_model = machine->cpu_type;
     ram_addr_t offset = 0;
     ram_addr_t ram_size = machine->ram_size;
-    uint64_t highram_size = 0;
+    uint64_t highram_size = 0, phyAddr = 0;
     MemoryRegion *address_space_mem = get_system_memory();
     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
+    int nb_numa_nodes = machine->numa_state->num_nodes;
+    NodeInfo *numa_info = machine->numa_state->nodes;
     int i;
     hwaddr fdt_base;
     const CPUArchIdList *possible_cpus;
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     CPUState *cpu;
+    char *ramName = NULL;
 
     if (!cpu_model) {
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
         machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
     }
     fdt_add_cpu_nodes(lams);
-    /* Add memory region */
-    memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
-                             machine->ram, 0, 256 * MiB);
-    memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
-    offset += 256 * MiB;
-    memmap_add_entry(0, 256 * MiB, 1);
-    highram_size = ram_size - 256 * MiB;
-    memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
-                             machine->ram, offset, highram_size);
-    memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
-    memmap_add_entry(0x90000000, highram_size, 1);
+
+    /* Node0 memory */
+    memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
+    fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
+    memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram",
+                             machine->ram, offset, VIRT_LOWMEM_SIZE);
+    memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem);
+
+    offset += VIRT_LOWMEM_SIZE;
+    if (nb_numa_nodes > 0) {
+        assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
+        highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
+    } else {
+        highram_size = ram_size - VIRT_LOWMEM_SIZE;
+    }
+    phyAddr = VIRT_HIGHMEM_BASE;
+    memmap_add_entry(phyAddr, highram_size, 1);
+    fdt_add_memory_node(machine, phyAddr, highram_size, 0);
+    memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram",
+                              machine->ram, offset, highram_size);
+    memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem);
+
+    /* Node1 - Nodemax memory */
+    offset += highram_size;
+    phyAddr += highram_size;
+
+    for (i = 1; i < nb_numa_nodes; i++) {
+        MemoryRegion *nodemem = g_new(MemoryRegion, 1);
+        ramName = g_strdup_printf("loongarch.node%d.ram", i);
+        memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
+                                 offset,  numa_info[i].node_mem);
+        memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
+        memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
+        fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
+        offset += numa_info[i].node_mem;
+        phyAddr += numa_info[i].node_mem;
+    }
 
     /* initialize device memory address space */
     if (machine->ram_size < machine->maxram_size) {
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
     return ms->possible_cpus;
 }
 
+static CpuInstanceProperties
+virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
+{
+    MachineClass *mc = MACHINE_GET_CLASS(ms);
+    const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
+
+    assert(cpu_index < possible_cpus->len);
+    return possible_cpus->cpus[cpu_index].props;
+}
+
+static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
+{
+    int64_t nidx = 0;
+
+    if (ms->numa_state->num_nodes) {
+        nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
+        if (ms->numa_state->num_nodes <= nidx) {
+            nidx = ms->numa_state->num_nodes - 1;
+        }
+    }
+    return nidx;
+}
+
 static void loongarch_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
     mc->default_boot_order = "c";
     mc->no_cdrom = 1;
     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
+    mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+    mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
+    mc->numa_mem_supported = true;
+    mc->auto_enable_numa_with_memhp = true;
+    mc->auto_enable_numa_with_memdev = true;
     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
     mc->default_nic = "virtio-net-pci";
     hc->plug = loongarch_machine_device_plug_cb;
-- 
2.39.1

From: Tianrui Zhao <zhaotianrui@loongson.cn>

Supplement LoongArch cpu topology arguments, including support socket
and threads per core.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230613123251.2471878-1-zhaotianrui@loongson.cn>
---
 hw/loongarch/acpi-build.c | 4 ++++
 hw/loongarch/virt.c       | 9 ++++++++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
     acpi_add_table(table_offsets, tables_blob);
     build_madt(tables_blob, tables->linker, lams);
 
+    acpi_add_table(table_offsets, tables_blob);
+    build_pptt(tables_blob, tables->linker, machine,
+               lams->oem_id, lams->oem_table_id);
+
     acpi_add_table(table_offsets, tables_blob);
     build_srat(tables_blob, tables->linker, machine);
 
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
     for (n = 0; n < ms->possible_cpus->len; n++) {
         ms->possible_cpus->cpus[n].type = ms->cpu_type;
         ms->possible_cpus->cpus[n].arch_id = n;
+
+        ms->possible_cpus->cpus[n].props.has_socket_id = true;
+        ms->possible_cpus->cpus[n].props.socket_id  =
+                                   n / (ms->smp.cores * ms->smp.threads);
         ms->possible_cpus->cpus[n].props.has_core_id = true;
-        ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;
+        ms->possible_cpus->cpus[n].props.core_id =
+                                   n / ms->smp.threads % ms->smp.cores;
+        ms->possible_cpus->cpus[n].props.has_thread_id = true;
+        ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;
     }
     return ms->possible_cpus;
 }
-- 
2.39.1

From: Jiajie Chen <c@jia.je>

The previous code checks whether the highest 16 bits of virtual address
equal to that of CSR.DMW0-3. This is incorrect according to the spec,
and is corrected to compare only the highest four bits instead.

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230614065556.2397513-1-c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/tlb_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
     }
 
     plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
-    base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS;
+    base_v = address >> R_CSR_DMW_VSEG_SHIFT;
     /* Check direct map window */
     for (int i = 0; i < 4; i++) {
-        base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS;
+        base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
         if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
             *physical = dmw_va2pa(address);
             *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-- 
2.39.1

The following changes since commit cf86770c7aa31ebd6e56f4eeb25c34107f92c51e:

Merge tag 'pull-request-2025-01-21v2' of https://gitlab.com/thuth/qemu into staging (2025-01-22 09:59:02 -0500)

are available in the Git repository at:

https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250124

for you to fetch changes up to 3215fe8528de45a1794f0314623cc10bd8e8e19f:

target/loongarch: Dump all generic CSR registers (2025-01-24 14:49:24 +0800)

----------------------------------------------------------------
pull-loongarch-20250124 queue

----------------------------------------------------------------
Bibo Mao (7):
      target/loongarch: Add dynamic function access with CSR register
      target/loongarch: Remove static CSR function setting
      target/loongarch: Add generic csr function type
      target/loongarch: Add common header file for CSR registers
      target/loongarch: Add common source file for CSR register
      target/loongarch: Set unused flag with CSR registers
      target/loongarch: Dump all generic CSR registers

target/loongarch/cpu.c                             |  96 +++++++++---
 target/loongarch/csr.c                             | 129 +++++++++++++++++
 target/loongarch/csr.h                             |  29 ++++
 target/loongarch/meson.build                       |   1 +
 .../tcg/insn_trans/trans_privileged.c.inc          | 161 +++++----------------
 target/loongarch/tcg/tcg_loongarch.h               |  12 ++
 target/loongarch/tcg/translate.c                   |   5 +
 7 files changed, 294 insertions(+), 139 deletions(-)
 create mode 100644 target/loongarch/csr.c
 create mode 100644 target/loongarch/csr.h
 create mode 100644 target/loongarch/tcg/tcg_loongarch.h

With CSR register, dynamic function access is used for CSR register
access in TCG mode, so that csr info can be used by other modules.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 .../tcg/insn_trans/trans_privileged.c.inc     | 37 +++++++++++++++++--
 target/loongarch/tcg/tcg_loongarch.h          | 12 ++++++
 target/loongarch/tcg/translate.c              |  5 +++
 3 files changed, 51 insertions(+), 3 deletions(-)
 create mode 100644 target/loongarch/tcg/tcg_loongarch.h

diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ enum {
 #define CSR_OFF(NAME) \
     CSR_OFF_FLAGS(NAME, 0)
 
-static const CSRInfo csr_info[] = {
+static CSRInfo csr_info[] = {
     CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
     CSR_OFF(PRMD),
     CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
     return false;
 }
 
-static const CSRInfo *get_csr(unsigned csr_num)
+static CSRInfo *get_csr(unsigned csr_num)
 {
-    const CSRInfo *csr;
+    CSRInfo *csr;
 
     if (csr_num >= ARRAY_SIZE(csr_info)) {
         return NULL;
@@ -XXX,XX +XXX,XX @@ static const CSRInfo *get_csr(unsigned csr_num)
     return csr;
 }
 
+static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
+                               GenCSRWrite writefn)
+{
+    CSRInfo *csr;
+
+    csr = get_csr(csr_num);
+    if (!csr) {
+        return false;
+    }
+
+    csr->readfn = readfn;
+    csr->writefn = writefn;
+    return true;
+}
+
+#define SET_CSR_FUNC(NAME, read, write)                 \
+        set_csr_trans_func(LOONGARCH_CSR_##NAME, read, write)
+
+void loongarch_csr_translate_init(void)
+{
+    SET_CSR_FUNC(ESTAT, NULL, gen_helper_csrwr_estat);
+    SET_CSR_FUNC(ASID,  NULL, gen_helper_csrwr_asid);
+    SET_CSR_FUNC(PGD,   gen_helper_csrrd_pgd, NULL);
+    SET_CSR_FUNC(PWCL,  NULL, gen_helper_csrwr_pwcl);
+    SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL);
+    SET_CSR_FUNC(TCFG,  NULL, gen_helper_csrwr_tcfg);
+    SET_CSR_FUNC(TVAL,  gen_helper_csrrd_tval, NULL);
+    SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr);
+}
+#undef SET_CSR_FUNC
+
 static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write)
 {
     if ((csr->flags & CSRFL_READONLY) && write) {
diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/loongarch/tcg/tcg_loongarch.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch TCG interface
+ *
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
+ */
+#ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H
+#define TARGET_LOONGARCH_TCG_LOONGARCH_H
+
+void loongarch_csr_translate_init(void);
+
+#endif  /* TARGET_LOONGARCH_TCG_LOONGARCH_H */
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
 #include "fpu/softfloat.h"
+#include "tcg_loongarch.h"
 #include "translate.h"
 #include "internals.h"
 #include "vec.h"
@@ -XXX,XX +XXX,XX @@ void loongarch_translate_init(void)
                     offsetof(CPULoongArchState, lladdr), "lladdr");
     cpu_llval = tcg_global_mem_new(tcg_env,
                     offsetof(CPULoongArchState, llval), "llval");
+
+#ifndef CONFIG_USER_ONLY
+    loongarch_csr_translate_init();
+#endif
 }
-- 
2.43.5

Since CSR function setting is done dynamically in TCG mode, remove
static CSR function setting here.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 .../tcg/insn_trans/trans_privileged.c.inc        | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite
is not used in non-TCG mode. Generic csr function type is added here
with parameter void type, so that it passes to compile with non-TCG mode.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 .../tcg/insn_trans/trans_privileged.c.inc     | 27 ++++++++++++-------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
 
 typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
 typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
+typedef void (*GenCSRFunc)(void);
 
 typedef struct {
     int offset;
     int flags;
-    GenCSRRead readfn;
-    GenCSRWrite writefn;
+    GenCSRFunc readfn;
+    GenCSRFunc writefn;
 } CSRInfo;
 
 enum {
@@ -XXX,XX +XXX,XX @@ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
         return false;
     }
 
-    csr->readfn = readfn;
-    csr->writefn = writefn;
+    csr->readfn = (GenCSRFunc)readfn;
+    csr->writefn = (GenCSRFunc)writefn;
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
 {
     TCGv dest;
     const CSRInfo *csr;
+    GenCSRRead readfn;
 
     if (check_plv(ctx)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
     } else {
         check_csr_flags(ctx, csr, false);
         dest = gpr_dst(ctx, a->rd, EXT_NONE);
-        if (csr->readfn) {
-            csr->readfn(dest, tcg_env);
+        readfn = (GenCSRRead)csr->readfn;
+        if (readfn) {
+            readfn(dest, tcg_env);
         } else {
             tcg_gen_ld_tl(dest, tcg_env, csr->offset);
         }
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
 {
     TCGv dest, src1;
     const CSRInfo *csr;
+    GenCSRWrite writefn;
 
     if (check_plv(ctx)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
         return false;
     }
     src1 = gpr_src(ctx, a->rd, EXT_NONE);
-    if (csr->writefn) {
+    writefn = (GenCSRWrite)csr->writefn;
+    if (writefn) {
         dest = gpr_dst(ctx, a->rd, EXT_NONE);
-        csr->writefn(dest, tcg_env, src1);
+        writefn(dest, tcg_env, src1);
     } else {
         dest = tcg_temp_new();
         tcg_gen_ld_tl(dest, tcg_env, csr->offset);
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
 {
     TCGv src1, mask, oldv, newv, temp;
     const CSRInfo *csr;
+    GenCSRWrite writefn;
 
     if (check_plv(ctx)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
     tcg_gen_andc_tl(temp, oldv, mask);
     tcg_gen_or_tl(newv, newv, temp);
 
-    if (csr->writefn) {
-        csr->writefn(oldv, tcg_env, newv);
+    writefn = (GenCSRWrite)csr->writefn;
+    if (writefn) {
+        writefn(oldv, tcg_env, newv);
     } else {
         tcg_gen_st_tl(newv, tcg_env, csr->offset);
     }
-- 
2.43.5

Common header file csr.h is added here, it can be used by both
TCG mode and kvm mode.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/csr.h                        | 25 +++++++++++++++++++
 .../tcg/insn_trans/trans_privileged.c.inc     | 16 +-----------
 2 files changed, 26 insertions(+), 15 deletions(-)
 create mode 100644 target/loongarch/csr.h

diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
+ */
+
+#ifndef TARGET_LOONGARCH_CSR_H
+#define TARGET_LOONGARCH_CSR_H
+
+#include "cpu-csr.h"
+
+typedef void (*GenCSRFunc)(void);
+enum {
+    CSRFL_READONLY = (1 << 0),
+    CSRFL_EXITTB   = (1 << 1),
+    CSRFL_IO       = (1 << 2),
+};
+
+typedef struct {
+    int offset;
+    int flags;
+    GenCSRFunc readfn;
+    GenCSRFunc writefn;
+} CSRInfo;
+
+#endif /* TARGET_LOONGARCH_CSR_H */
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@
  * LoongArch translation routines for the privileged instructions.
  */
 
-#include "cpu-csr.h"
+#include "csr.h"
 
 #ifdef CONFIG_USER_ONLY
 
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
 
 typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
 typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
-typedef void (*GenCSRFunc)(void);
-
-typedef struct {
-    int offset;
-    int flags;
-    GenCSRFunc readfn;
-    GenCSRFunc writefn;
-} CSRInfo;
-
-enum {
-    CSRFL_READONLY = (1 << 0),
-    CSRFL_EXITTB   = (1 << 1),
-    CSRFL_IO       = (1 << 2),
-};
 
 #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
     [LOONGARCH_CSR_##NAME] = {                             \
-- 
2.43.5

Common source file csr.c is added here, it can be used by both
TCG mode and kvm mode. The common code is removed from file
tcg/insn_trans/trans_privileged.c.inc to csrc.c

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/csr.c                        | 114 ++++++++++++++++++
 target/loongarch/csr.h                        |   1 +
 target/loongarch/meson.build                  |   1 +
 .../tcg/insn_trans/trans_privileged.c.inc     | 107 ----------------
 4 files changed, 116 insertions(+), 107 deletions(-)
 create mode 100644 target/loongarch/csr.c

diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
+ */
+#include <stddef.h>
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "csr.h"
+
+#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
+    [LOONGARCH_CSR_##NAME] = {                             \
+        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
+        .flags = FL, .readfn = RD, .writefn = WR           \
+    }
+
+#define CSR_OFF_ARRAY(NAME, N)                                \
+    [LOONGARCH_CSR_##NAME(N)] = {                             \
+        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
+        .flags = 0, .readfn = NULL, .writefn = NULL           \
+    }
+
+#define CSR_OFF_FLAGS(NAME, FL)   CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
+#define CSR_OFF(NAME)             CSR_OFF_FLAGS(NAME, 0)
+
+static CSRInfo csr_info[] = {
+    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
+    CSR_OFF(PRMD),
+    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
+    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
+    CSR_OFF(ECFG),
+    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
+    CSR_OFF(ERA),
+    CSR_OFF(BADV),
+    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
+    CSR_OFF(EENTRY),
+    CSR_OFF(TLBIDX),
+    CSR_OFF(TLBEHI),
+    CSR_OFF(TLBELO0),
+    CSR_OFF(TLBELO1),
+    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
+    CSR_OFF(PGDL),
+    CSR_OFF(PGDH),
+    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
+    CSR_OFF(PWCL),
+    CSR_OFF(PWCH),
+    CSR_OFF(STLBPS),
+    CSR_OFF(RVACFG),
+    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
+    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
+    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
+    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
+    CSR_OFF_ARRAY(SAVE, 0),
+    CSR_OFF_ARRAY(SAVE, 1),
+    CSR_OFF_ARRAY(SAVE, 2),
+    CSR_OFF_ARRAY(SAVE, 3),
+    CSR_OFF_ARRAY(SAVE, 4),
+    CSR_OFF_ARRAY(SAVE, 5),
+    CSR_OFF_ARRAY(SAVE, 6),
+    CSR_OFF_ARRAY(SAVE, 7),
+    CSR_OFF_ARRAY(SAVE, 8),
+    CSR_OFF_ARRAY(SAVE, 9),
+    CSR_OFF_ARRAY(SAVE, 10),
+    CSR_OFF_ARRAY(SAVE, 11),
+    CSR_OFF_ARRAY(SAVE, 12),
+    CSR_OFF_ARRAY(SAVE, 13),
+    CSR_OFF_ARRAY(SAVE, 14),
+    CSR_OFF_ARRAY(SAVE, 15),
+    CSR_OFF(TID),
+    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
+    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
+    CSR_OFF(CNTC),
+    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
+    CSR_OFF(LLBCTL),
+    CSR_OFF(IMPCTL1),
+    CSR_OFF(IMPCTL2),
+    CSR_OFF(TLBRENTRY),
+    CSR_OFF(TLBRBADV),
+    CSR_OFF(TLBRERA),
+    CSR_OFF(TLBRSAVE),
+    CSR_OFF(TLBRELO0),
+    CSR_OFF(TLBRELO1),
+    CSR_OFF(TLBREHI),
+    CSR_OFF(TLBRPRMD),
+    CSR_OFF(MERRCTL),
+    CSR_OFF(MERRINFO1),
+    CSR_OFF(MERRINFO2),
+    CSR_OFF(MERRENTRY),
+    CSR_OFF(MERRERA),
+    CSR_OFF(MERRSAVE),
+    CSR_OFF(CTAG),
+    CSR_OFF_ARRAY(DMW, 0),
+    CSR_OFF_ARRAY(DMW, 1),
+    CSR_OFF_ARRAY(DMW, 2),
+    CSR_OFF_ARRAY(DMW, 3),
+    CSR_OFF(DBG),
+    CSR_OFF(DERA),
+    CSR_OFF(DSAVE),
+};
+
+CSRInfo *get_csr(unsigned int csr_num)
+{
+    CSRInfo *csr;
+
+    if (csr_num >= ARRAY_SIZE(csr_info)) {
+        return NULL;
+    }
+
+    csr = &csr_info[csr_num];
+    if (csr->offset == 0) {
+        return NULL;
+    }
+
+    return csr;
+}
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.h
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
     GenCSRFunc writefn;
 } CSRInfo;
 
+CSRInfo *get_csr(unsigned int csr_num);
 #endif /* TARGET_LOONGARCH_CSR_H */
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -XXX,XX +XXX,XX @@ loongarch_system_ss = ss.source_set()
 loongarch_system_ss.add(files(
   'arch_dump.c',
   'cpu_helper.c',
+  'csr.c',
   'loongarch-qmp-cmds.c',
   'machine.c',
 ))
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
 typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
 typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
 
-#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
-    [LOONGARCH_CSR_##NAME] = {                             \
-        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
-        .flags = FL, .readfn = RD, .writefn = WR           \
-    }
-
-#define CSR_OFF_ARRAY(NAME, N)                                \
-    [LOONGARCH_CSR_##NAME(N)] = {                             \
-        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
-        .flags = 0, .readfn = NULL, .writefn = NULL           \
-    }
-
-#define CSR_OFF_FLAGS(NAME, FL) \
-    CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
-
-#define CSR_OFF(NAME) \
-    CSR_OFF_FLAGS(NAME, 0)
-
-static CSRInfo csr_info[] = {
-    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
-    CSR_OFF(PRMD),
-    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
-    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
-    CSR_OFF(ECFG),
-    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
-    CSR_OFF(ERA),
-    CSR_OFF(BADV),
-    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
-    CSR_OFF(EENTRY),
-    CSR_OFF(TLBIDX),
-    CSR_OFF(TLBEHI),
-    CSR_OFF(TLBELO0),
-    CSR_OFF(TLBELO1),
-    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
-    CSR_OFF(PGDL),
-    CSR_OFF(PGDH),
-    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
-    CSR_OFF(PWCL),
-    CSR_OFF(PWCH),
-    CSR_OFF(STLBPS),
-    CSR_OFF(RVACFG),
-    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
-    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
-    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
-    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
-    CSR_OFF_ARRAY(SAVE, 0),
-    CSR_OFF_ARRAY(SAVE, 1),
-    CSR_OFF_ARRAY(SAVE, 2),
-    CSR_OFF_ARRAY(SAVE, 3),
-    CSR_OFF_ARRAY(SAVE, 4),
-    CSR_OFF_ARRAY(SAVE, 5),
-    CSR_OFF_ARRAY(SAVE, 6),
-    CSR_OFF_ARRAY(SAVE, 7),
-    CSR_OFF_ARRAY(SAVE, 8),
-    CSR_OFF_ARRAY(SAVE, 9),
-    CSR_OFF_ARRAY(SAVE, 10),
-    CSR_OFF_ARRAY(SAVE, 11),
-    CSR_OFF_ARRAY(SAVE, 12),
-    CSR_OFF_ARRAY(SAVE, 13),
-    CSR_OFF_ARRAY(SAVE, 14),
-    CSR_OFF_ARRAY(SAVE, 15),
-    CSR_OFF(TID),
-    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
-    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
-    CSR_OFF(CNTC),
-    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
-    CSR_OFF(LLBCTL),
-    CSR_OFF(IMPCTL1),
-    CSR_OFF(IMPCTL2),
-    CSR_OFF(TLBRENTRY),
-    CSR_OFF(TLBRBADV),
-    CSR_OFF(TLBRERA),
-    CSR_OFF(TLBRSAVE),
-    CSR_OFF(TLBRELO0),
-    CSR_OFF(TLBRELO1),
-    CSR_OFF(TLBREHI),
-    CSR_OFF(TLBRPRMD),
-    CSR_OFF(MERRCTL),
-    CSR_OFF(MERRINFO1),
-    CSR_OFF(MERRINFO2),
-    CSR_OFF(MERRENTRY),
-    CSR_OFF(MERRERA),
-    CSR_OFF(MERRSAVE),
-    CSR_OFF(CTAG),
-    CSR_OFF_ARRAY(DMW, 0),
-    CSR_OFF_ARRAY(DMW, 1),
-    CSR_OFF_ARRAY(DMW, 2),
-    CSR_OFF_ARRAY(DMW, 3),
-    CSR_OFF(DBG),
-    CSR_OFF(DERA),
-    CSR_OFF(DSAVE),
-};
-
 static bool check_plv(DisasContext *ctx)
 {
     if (ctx->plv == MMU_PLV_USER) {
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
     return false;
 }
 
-static CSRInfo *get_csr(unsigned csr_num)
-{
-    CSRInfo *csr;
-
-    if (csr_num >= ARRAY_SIZE(csr_info)) {
-        return NULL;
-    }
-    csr = &csr_info[csr_num];
-    if (csr->offset == 0) {
-        return NULL;
-    }
-    return csr;
-}
-
 static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
                                GenCSRWrite writefn)
 {
-- 
2.43.5

On LA464, some CSR registers are not used such as CSR_SAVE8 -
CSR_SAVE15, also CSR registers relative with MCE is not used now.

Flag CSRFL_UNUSED is added for these registers, so that it will
not dumped. In order to keep compatiblity, these CSR registers are
not removed since it is used in vmstate already.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c | 30 +++++++++++++++++++++++++++++-
 target/loongarch/csr.c | 13 +++++++++++++
 target/loongarch/csr.h |  2 ++
 3 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "internals.h"
 #include "fpu/softfloat-helpers.h"
-#include "cpu-csr.h"
+#include "csr.h"
 #ifndef CONFIG_USER_ONLY
 #include "system/reset.h"
 #endif
@@ -XXX,XX +XXX,XX @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
     return MMU_DA_IDX;
 }
 
+static void loongarch_la464_init_csr(Object *obj)
+{
+#ifndef CONFIG_USER_ONLY
+    static bool initialized;
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+    int i, num;
+
+    if (!initialized) {
+        initialized = true;
+        num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM);
+        for (i = num; i < 16; i++) {
+            set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED);
+        }
+        set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED);
+    }
+#endif
+}
+
 static void loongarch_la464_initfn(Object *obj)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
 
+    loongarch_la464_init_csr(obj);
     loongarch_cpu_post_init(obj);
 }
 
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.c
+++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@ CSRInfo *get_csr(unsigned int csr_num)
 
     return csr;
 }
+
+bool set_csr_flag(unsigned int csr_num, int flag)
+{
+    CSRInfo *csr;
+
+    csr = get_csr(csr_num);
+    if (!csr) {
+        return false;
+    }
+
+    csr->flags |= flag;
+    return true;
+}
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.h
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@ enum {
     CSRFL_READONLY = (1 << 0),
     CSRFL_EXITTB   = (1 << 1),
     CSRFL_IO       = (1 << 2),
+    CSRFL_UNUSED   = (1 << 3),
 };
 
 typedef struct {
@@ -XXX,XX +XXX,XX @@ typedef struct {
 } CSRInfo;
 
 CSRInfo *get_csr(unsigned int csr_num);
+bool set_csr_flag(unsigned int csr_num, int flag);
 #endif /* TARGET_LOONGARCH_CSR_H */
-- 
2.43.5

CSR registers is import system control registers, it had better
dump all CSR registers when VM is running in system mode.

Here is dump output example of CSR registers:
 CSR000: CRMD   b4               PRMD   4                EUEN   0                MISC   0
 CSR004: ECFG   71c1c            ESTAT  0                ERA    9000000002c31300 BADV   12022c0e0
 CSR008: BADI   2b0000
 CSR012: EENTRY 90000000046b0000
 CSR016: TLBIDX ffffffff8e000228 TLBEHI 120228000        TLBELO0 400000016f19001f TLBELO1 400000016f1a401f
 CSR024: ASID   a0004            PGDL   90000001016f0000 PGDH   9000000004680000 PGD    0
 CSR028: PWCL   5e56e            PWCH   2e4              STLBPS e                RVACFG 0
 CSR032: CPUID  0                PRCFG1 72f8             PRCFG2 3ffff000         PRCFG3 8073f2
 CSR048: SAVE0  0                SAVE1  af9c             SAVE2  12010d6a8        SAVE3  8300000
 CSR052: SAVE4  0                SAVE5  0                SAVE6  0                SAVE7  0
 CSR064: TID    0                TCFG   8f0ca15          TVAL   4cefd8b          CNTC   fffffffffe688aaa
 CSR068: TICLR  0
 CSR096: LLBCTL 1
 CSR136: TLBRENTRY 46ba000       TLBRBADV ffff8000130d81e2 TLBRERA 9000000003585cb8 TLBRSAVE ffff8000130d81e0
 CSR140: TLBRELO0 1fe00043       TLBRELO1 40             TLBREHI ffff8000130d800e TLBRPRMD 0
 CSR384: DMW0   8000000000000001 DMW1   9000000000000011 DMW2   0                DMW3   0

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c | 66 ++++++++++++++++++++++++++++++++----------
 target/loongarch/csr.c |  2 ++
 target/loongarch/csr.h |  1 +
 3 files changed, 53 insertions(+), 16 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
+static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f)
+{
+#ifndef CONFIG_USER_ONLY
+    CPULoongArchState *env = cpu_env(cs);
+    CSRInfo *csr_info;
+    int64_t *addr;
+    int i, j, len, col = 0;
+
+    qemu_fprintf(f, "\n");
+
+    /* Dump all generic CSR register */
+    for (i = 0; i < LOONGARCH_CSR_DBG; i++) {
+        csr_info = get_csr(i);
+        if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) {
+            if (i == (col + 3)) {
+                qemu_fprintf(f, "\n");
+            }
+
+            continue;
+        }
+
+        if ((i >  (col + 3)) || (i == col)) {
+            col = i & ~3;
+            qemu_fprintf(f, " CSR%03d:", col);
+        }
+
+        addr = (void *)env + csr_info->offset;
+        qemu_fprintf(f, " %s ", csr_info->name);
+        len = strlen(csr_info->name);
+        for (; len < 6; len++) {
+            qemu_fprintf(f, " ");
+        }
+
+        qemu_fprintf(f, "%" PRIx64, *addr);
+        j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1);
+        len += j / 4 + 1;
+        for (; len < 22; len++) {
+                qemu_fprintf(f, " ");
+        }
+
+        if (i == (col + 3)) {
+            qemu_fprintf(f, "\n");
+        }
+    }
+    qemu_fprintf(f, "\n");
+#endif
+}
+
 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     CPULoongArchState *env = cpu_env(cs);
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         }
     }
 
-    qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
-    qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
-    qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
-    qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
-    qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
-    qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
-    qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
-    qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
-    qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
-                 " PRCFG3=%016" PRIx64 "\n",
-                 env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
-    qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
-    qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
-    qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
-    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
-    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
+    /* csr */
+    loongarch_cpu_dump_csr(cs, f);
 
     /* fpr */
     if (flags & CPU_DUMP_FPU) {
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.c
+++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@
 
 #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
     [LOONGARCH_CSR_##NAME] = {                             \
+        .name   = (stringify(NAME)),                       \
         .offset = offsetof(CPULoongArchState, CSR_##NAME), \
         .flags = FL, .readfn = RD, .writefn = WR           \
     }
 
 #define CSR_OFF_ARRAY(NAME, N)                                \
     [LOONGARCH_CSR_##NAME(N)] = {                             \
+        .name   = (stringify(NAME##N)),                       \
         .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
         .flags = 0, .readfn = NULL, .writefn = NULL           \
     }
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.h
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 typedef struct {
+    const char *name;
     int offset;
     int flags;
     GenCSRFunc readfn;
-- 
2.43.5