The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:

Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200)

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230616

for you to fetch changes up to 505aa8d8f29b79fcef77563bb4124208badbd8d4:

target/loongarch: Fix CSR.DMW0-3.VSEG check (2023-06-16 17:58:46 +0800)

pull-loongarch-20230616

* Fix CSR.DMW0-3.VSEG check

* Add cpu arch_id support

* Set physical cpuid route for LoongArch ipi device

* Add numa support

* Supplement cpu topology arguments

Jiajie Chen (1):

target/loongarch: Fix CSR.DMW0-3.VSEG check

Tianrui Zhao (4):

hw/loongarch/virt: Add cpu arch_id support

hw/intc: Set physical cpuid route for LoongArch ipi device

hw/loongarch: Add numa support

hw/loongarch: Supplement cpu topology arguments

hw/intc/loongarch_ipi.c | 44 +++++++++++--

hw/loongarch/Kconfig | 1 +

hw/loongarch/acpi-build.c | 78 ++++++++++++++++++-----

hw/loongarch/virt.c | 144 ++++++++++++++++++++++++++++++++++++++----

target/loongarch/cpu.h | 2 +

target/loongarch/tlb_helper.c | 4 +-

6 files changed, 235 insertions(+), 38 deletions(-)

From: Jiajie Chen <c@jia.je>

The previous code checks whether the highest 16 bits of virtual address

equal to that of CSR.DMW0-3. This is incorrect according to the spec,

and is corrected to compare only the highest four bits instead.

Signed-off-by: Jiajie Chen <c@jia.je>

Reviewed-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20230614065556.2397513-1-c@jia.je>

Signed-off-by: Song Gao <gaosong@loongson.cn>

target/loongarch/tlb_helper.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c

--- a/target/loongarch/tlb_helper.c

+++ b/target/loongarch/tlb_helper.c

@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,

2.39.1

From: Tianrui Zhao <zhaotianrui@loongson.cn>

Supplement LoongArch cpu topology arguments, including support socket

and threads per core.

@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)

for (n = 0; n < ms->possible_cpus->len; n++) {

ms->possible_cpus->cpus[n].type = ms->cpu_type;

ms->possible_cpus->cpus[n].arch_id = n;

+

+ ms->possible_cpus->cpus[n].props.has_socket_id = true;

+ ms->possible_cpus->cpus[n].props.socket_id =

+ n / (ms->smp.cores * ms->smp.threads);

ms->possible_cpus->cpus[n].props.has_core_id = true;

- ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;

+ ms->possible_cpus->cpus[n].props.core_id =

+ n / ms->smp.threads % ms->smp.cores;

+ ms->possible_cpus->cpus[n].props.has_thread_id = true;

+ ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;

}

return ms->possible_cpus;

2.39.1

From: Tianrui Zhao <zhaotianrui@loongson.cn>

1. Implement some functions for LoongArch numa support;

2. Implement fdt_add_memory_node() for fdt;

3. build_srat() fills node_id and adds build numa memory.

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)

for (num = smp_cpus - 1; num >= 0; num--) {

char *nodename = g_strdup_printf("/cpus/cpu@%d", num);

LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));

+ CPUState *cs = CPU(cpu);

+ if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",

+ ms->possible_cpus->cpus[cs->cpu_index].props.node_id);

+ }

qemu_fdt_alloc_phandle(ms->fdt));

@@ -XXX,XX +XXX,XX @@ static void fdt_add_irqchip_node(LoongArchMachineState *lams)

g_free(nodename);

2.39.1

From: Tianrui Zhao <zhaotianrui@loongson.cn>

With acpi madt table, there is cpu physical coreid, which may

be different with logical id in qemu. This patch adds cpu arch_id

support, and fill madt table with arch_id. For the present cpu

arch_id is still equal to logical id.

Reviewed-by: Song Gao <gaosong@loongson.cn>

Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20230613120552.2471420-2-zhaotianrui@loongson.cn>

---

hw/loongarch/acpi-build.c | 20 ++++++++++++++------

hw/loongarch/virt.c | 34 ++++++++++++++++++++++++++++++++--

2 files changed, 46 insertions(+), 8 deletions(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c

--- a/hw/loongarch/acpi-build.c

+++ b/hw/loongarch/acpi-build.c

@@ -XXX,XX +XXX,XX @@ static void

build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)

{

MachineState *ms = MACHINE(lams);

- int i;

+ MachineClass *mc = MACHINE_GET_CLASS(ms);

+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);

+ int i, arch_id;

AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id,

.oem_table_id = lams->oem_table_id };

@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)

build_append_int_noprefix(table_data, 0, 4);

build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */

- for (i = 0; i < ms->smp.cpus; i++) {

+ for (i = 0; i < arch_ids->len; i++) {

/* Processor Core Interrupt Controller Structure */

+ arch_id = arch_ids->cpus[i].arch_id;

+

build_append_int_noprefix(table_data, 17, 1); /* Type */

build_append_int_noprefix(table_data, 15, 1); /* Length */

build_append_int_noprefix(table_data, 1, 1); /* Version */

build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */

- build_append_int_noprefix(table_data, i, 4); /* Core ID */

+ build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */

build_append_int_noprefix(table_data, 1, 4); /* Flags */

@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)

static void

build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)

{

- uint64_t i;

+ int i, arch_id;

LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);

MachineState *ms = MACHINE(lams);

+ MachineClass *mc = MACHINE_GET_CLASS(ms);

+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);

AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,

.oem_table_id = lams->oem_table_id };

@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)

build_append_int_noprefix(table_data, 1, 4); /* Reserved */

build_append_int_noprefix(table_data, 0, 8); /* Reserved */

- for (i = 0; i < ms->smp.cpus; ++i) {

+ for (i = 0; i < arch_ids->len; ++i) {

+ arch_id = arch_ids->cpus[i].arch_id;

+

/* Processor Local APIC/SAPIC Affinity Structure */

build_append_int_noprefix(table_data, 0, 1); /* Type */

build_append_int_noprefix(table_data, 16, 1); /* Length */

/* Proximity Domain [7:0] */

build_append_int_noprefix(table_data, 0, 1);

- build_append_int_noprefix(table_data, i, 1); /* APIC ID */

+ build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */

/* Flags, Table 5-36 */

build_append_int_noprefix(table_data, 1, 4);

build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c

--- a/hw/loongarch/virt.c

+++ b/hw/loongarch/virt.c

@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)

LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);

int i;

hwaddr fdt_base;

+ const CPUArchIdList *possible_cpus;

+ MachineClass *mc = MACHINE_GET_CLASS(machine);

+ CPUState *cpu;

if (!cpu_model) {

cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");

@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)

create_fdt(lams);

/* Init CPUs */

- for (i = 0; i < machine->smp.cpus; i++) {

- cpu_create(machine->cpu_type);

+

+ possible_cpus = mc->possible_cpu_arch_ids(machine);

+ for (i = 0; i < possible_cpus->len; i++) {

+ cpu = cpu_create(machine->cpu_type);

+ cpu->cpu_index = i;

+ machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);

}

fdt_add_cpu_nodes(lams);

/* Add memory region */

@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,

return NULL;

}

+static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)

+{

+ int n;

+ unsigned int max_cpus = ms->smp.max_cpus;

+

+ if (ms->possible_cpus) {

+ assert(ms->possible_cpus->len == max_cpus);

+ return ms->possible_cpus;

+ ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +

+ sizeof(CPUArchId) * max_cpus);

+ ms->possible_cpus->len = max_cpus;

+ for (n = 0; n < ms->possible_cpus->len; n++) {

+ ms->possible_cpus->cpus[n].type = ms->cpu_type;

+ ms->possible_cpus->cpus[n].arch_id = n;

+ ms->possible_cpus->cpus[n].props.has_core_id = true;

+ ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;

+ }

+ return ms->possible_cpus;

+}

+

static void loongarch_class_init(ObjectClass *oc, void *data)

{

MachineClass *mc = MACHINE_CLASS(oc);

@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)

mc->block_default_type = IF_VIRTIO;

mc->default_boot_order = "c";

mc->no_cdrom = 1;

+ mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;

mc->get_hotplug_handler = virt_machine_get_hotplug_handler;

mc->default_nic = "virtio-net-pci";

hc->plug = loongarch_machine_device_plug_cb;

2.39.1

From: Tianrui Zhao <zhaotianrui@loongson.cn>

LoongArch ipi device uses physical cpuid to route to different

vcpus rather logical cpuid, and the physical cpuid is the same

with cpuid in acpi dsdt and srat table.

Reviewed-by: Song Gao <gaosong@loongson.cn>

Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn>

---

hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++++-------

hw/loongarch/virt.c | 1 +

target/loongarch/cpu.h | 2 ++

3 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c

--- a/hw/intc/loongarch_ipi.c

+++ b/hw/intc/loongarch_ipi.c

@@ -XXX,XX +XXX,XX @@

#include "target/loongarch/internals.h"

#include "trace.h"

+static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned);

static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)

IPICore *s = opaque;

@@ -XXX,XX +XXX,XX @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)

data, MEMTXATTRS_UNSPECIFIED, NULL);

+static int archid_cmp(const void *a, const void *b)

+{

+ CPUArchId *archid_a = (CPUArchId *)a;

+ CPUArchId *archid_b = (CPUArchId *)b;

+ return archid_a->arch_id - archid_b->arch_id;

+}

+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)

+{

+ CPUArchId apic_id, *found_cpu;

+ apic_id.arch_id = id;

+ found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,

+ ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),

+ archid_cmp);

+

+ return found_cpu;

+}

+

+static CPUState *ipi_getcpu(int arch_id)

+{

+ MachineState *machine = MACHINE(qdev_get_machine());

+ CPUArchId *archid;

+

+ archid = find_cpu_by_archid(machine, arch_id);

+ return CPU(archid->cpu);

+}

+

static void ipi_send(uint64_t val)

{

uint32_t cpuid;

uint8_t vector;

- CPULoongArchState *env;

CPUState *cs;

LoongArchCPU *cpu;

+ LoongArchIPI *s;

cpuid = extract32(val, 16, 10);

if (cpuid >= LOONGARCH_MAX_CPUS) {

@@ -XXX,XX +XXX,XX @@ static void ipi_send(uint64_t val)

/* IPI status vector */

vector = extract8(val, 0, 5);

- cs = qemu_get_cpu(cpuid);

+ cs = ipi_getcpu(cpuid);

cpu = LOONGARCH_CPU(cs);

- env = &cpu->env;

- address_space_stl(&env->address_space_iocsr, 0x1008,

- BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);

+ s = LOONGARCH_IPI(cpu->env.ipistate);

+ loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4);

static void mail_send(uint64_t val)

@@ -XXX,XX +XXX,XX @@ static void mail_send(uint64_t val)

}

addr = 0x1020 + (val & 0x1c);

- cs = qemu_get_cpu(cpuid);

+ cs = ipi_getcpu(cpuid);

cpu = LOONGARCH_CPU(cs);

env = &cpu->env;

send_ipi_data(env, val, addr);

@@ -XXX,XX +XXX,XX @@ static void any_send(uint64_t val)

}

addr = val & 0xffff;

- cs = qemu_get_cpu(cpuid);

+ cs = ipi_getcpu(cpuid);

cpu = LOONGARCH_CPU(cs);

env = &cpu->env;

send_ipi_data(env, val, addr);

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/loongarch/virt.c

+++ b/hw/loongarch/virt.c

@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)

memory_region_add_subregion(&env->system_iocsr, APIC_BASE,

sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),

cpu));

+ env->ipistate = ipi;

}

/*

@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {

MemoryRegion iocsr_mem;

bool load_elf;

uint64_t elf_address;

+ /* Store ipistate to access from this struct */

+ DeviceState *ipistate;

#endif

} CPULoongArchState;

2.39.1