[PULL 0/5] loongarch-to-apply queue
[PULL 00/18] loongarch-to-apply queue
1
The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:
1
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
2
2
3
Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200)
3
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230616
7
https://gitlab.com/bibo-mao/qemu.git pull-loongarch-20241213
8
8
9
for you to fetch changes up to 505aa8d8f29b79fcef77563bb4124208badbd8d4:
9
for you to fetch changes up to 78aa256571aa06f32001bd80635a1858187c609b:
10
10
11
target/loongarch: Fix CSR.DMW0-3.VSEG check (2023-06-16 17:58:46 +0800)
11
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic (2024-12-13 14:39:39 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
pull-loongarch-20230616
14
pull-loongarch-20241213
15
16
* Fix CSR.DMW0-3.VSEG check
17
* Add cpu arch_id support
18
* Set physical cpuid route for LoongArch ipi device
19
* Add numa support
20
* Supplement cpu topology arguments
21
15
22
----------------------------------------------------------------
16
----------------------------------------------------------------
23
Jiajie Chen (1):
17
Bibo Mao (8):
24
target/loongarch: Fix CSR.DMW0-3.VSEG check
18
include: Add loongarch_pic_common header file
19
include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
20
hw/intc/loongarch_pch: Merge instance_init() into realize()
21
hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
22
hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
23
hw/intc/loongarch_pch: Inherit from loongarch_pic_common
24
hw/intc/loongarch_pch: Add pre_save and post_load interfaces
25
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
25
26
26
Tianrui Zhao (4):
27
hw/intc/loongarch_pch_pic.c | 106 +++++++++++----------------------
27
hw/loongarch/virt: Add cpu arch_id support
28
hw/intc/loongarch_pic_common.c | 97 ++++++++++++++++++++++++++++++
28
hw/intc: Set physical cpuid route for LoongArch ipi device
29
hw/intc/meson.build | 2 +-
29
hw/loongarch: Add numa support
30
hw/loongarch/virt.c | 2 +-
30
hw/loongarch: Supplement cpu topology arguments
31
include/hw/intc/loongarch_pch_pic.h | 70 +++++-----------------
31
32
include/hw/intc/loongarch_pic_common.h | 82 +++++++++++++++++++++++++
32
hw/intc/loongarch_ipi.c | 44 +++++++++++--
33
6 files changed, 230 insertions(+), 129 deletions(-)
33
hw/loongarch/Kconfig | 1 +
34
create mode 100644 hw/intc/loongarch_pic_common.c
34
hw/loongarch/acpi-build.c | 78 ++++++++++++++++++-----
35
create mode 100644 include/hw/intc/loongarch_pic_common.h
35
hw/loongarch/virt.c | 144 ++++++++++++++++++++++++++++++++++++++----
36
target/loongarch/cpu.h | 2 +
37
target/loongarch/tlb_helper.c | 4 +-
38
6 files changed, 235 insertions(+), 38 deletions(-)
diff view generated by jsdifflib
New patch
[PULL 01/18] include: Add loongarch_pic_common header file
1
Add common header file hw/intc/loongarch_pic_common.h, and move
2
some macro definition from hw/intc/loongarch_pch_pic.h to the common
3
header file.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 36 +++-------------------
9
include/hw/intc/loongarch_pic_common.h | 42 ++++++++++++++++++++++++++
10
2 files changed, 47 insertions(+), 31 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_pic_common.h
12
13
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/loongarch_pch_pic.h
16
+++ b/include/hw/intc/loongarch_pch_pic.h
17
@@ -XXX,XX +XXX,XX @@
18
* Copyright (c) 2021 Loongson Technology Corporation Limited
19
*/
20
21
-#include "hw/sysbus.h"
22
+#ifndef HW_LOONGARCH_PCH_PIC_H
23
+#define HW_LOONGARCH_PCH_PIC_H
24
+
25
+#include "hw/intc/loongarch_pic_common.h"
26
27
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
28
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
29
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
30
31
-#define PCH_PIC_INT_ID_VAL 0x7000000UL
32
-#define PCH_PIC_INT_ID_VER 0x1UL
33
-
34
-#define PCH_PIC_INT_ID_LO 0x00
35
-#define PCH_PIC_INT_ID_HI 0x04
36
-#define PCH_PIC_INT_MASK_LO 0x20
37
-#define PCH_PIC_INT_MASK_HI 0x24
38
-#define PCH_PIC_HTMSI_EN_LO 0x40
39
-#define PCH_PIC_HTMSI_EN_HI 0x44
40
-#define PCH_PIC_INT_EDGE_LO 0x60
41
-#define PCH_PIC_INT_EDGE_HI 0x64
42
-#define PCH_PIC_INT_CLEAR_LO 0x80
43
-#define PCH_PIC_INT_CLEAR_HI 0x84
44
-#define PCH_PIC_AUTO_CTRL0_LO 0xc0
45
-#define PCH_PIC_AUTO_CTRL0_HI 0xc4
46
-#define PCH_PIC_AUTO_CTRL1_LO 0xe0
47
-#define PCH_PIC_AUTO_CTRL1_HI 0xe4
48
-#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
49
-#define PCH_PIC_ROUTE_ENTRY_END 0x13f
50
-#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
51
-#define PCH_PIC_HTMSI_VEC_END 0x23f
52
-#define PCH_PIC_INT_STATUS_LO 0x3a0
53
-#define PCH_PIC_INT_STATUS_HI 0x3a4
54
-#define PCH_PIC_INT_POL_LO 0x3e0
55
-#define PCH_PIC_INT_POL_HI 0x3e4
56
-
57
-#define STATUS_LO_START 0
58
-#define STATUS_HI_START 0x4
59
-#define POL_LO_START 0x40
60
-#define POL_HI_START 0x44
61
struct LoongArchPCHPIC {
62
SysBusDevice parent_obj;
63
qemu_irq parent_irq[64];
64
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
65
MemoryRegion iomem8;
66
unsigned int irq_num;
67
};
68
+#endif /* HW_LOONGARCH_PCH_PIC_H */
69
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/include/hw/intc/loongarch_pic_common.h
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * LoongArch 7A1000 I/O interrupt controller definitions
78
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+#ifndef HW_LOONGARCH_PIC_COMMON_H
82
+#define HW_LOONGARCH_PIC_COMMON_H
83
+
84
+#include "hw/pci-host/ls7a.h"
85
+#include "hw/sysbus.h"
86
+
87
+#define PCH_PIC_INT_ID_VAL 0x7000000UL
88
+#define PCH_PIC_INT_ID_VER 0x1UL
89
+#define PCH_PIC_INT_ID_LO 0x00
90
+#define PCH_PIC_INT_ID_HI 0x04
91
+#define PCH_PIC_INT_MASK_LO 0x20
92
+#define PCH_PIC_INT_MASK_HI 0x24
93
+#define PCH_PIC_HTMSI_EN_LO 0x40
94
+#define PCH_PIC_HTMSI_EN_HI 0x44
95
+#define PCH_PIC_INT_EDGE_LO 0x60
96
+#define PCH_PIC_INT_EDGE_HI 0x64
97
+#define PCH_PIC_INT_CLEAR_LO 0x80
98
+#define PCH_PIC_INT_CLEAR_HI 0x84
99
+#define PCH_PIC_AUTO_CTRL0_LO 0xc0
100
+#define PCH_PIC_AUTO_CTRL0_HI 0xc4
101
+#define PCH_PIC_AUTO_CTRL1_LO 0xe0
102
+#define PCH_PIC_AUTO_CTRL1_HI 0xe4
103
+#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
104
+#define PCH_PIC_ROUTE_ENTRY_END 0x13f
105
+#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
106
+#define PCH_PIC_HTMSI_VEC_END 0x23f
107
+#define PCH_PIC_INT_STATUS_LO 0x3a0
108
+#define PCH_PIC_INT_STATUS_HI 0x3a4
109
+#define PCH_PIC_INT_POL_LO 0x3e0
110
+#define PCH_PIC_INT_POL_HI 0x3e4
111
+
112
+#define STATUS_LO_START 0
113
+#define STATUS_HI_START 0x4
114
+#define POL_LO_START 0x40
115
+#define POL_HI_START 0x44
116
+#endif /* HW_LOONGARCH_PIC_COMMON_H */
117
--
118
2.43.5
diff view generated by jsdifflib
New patch
[PULL 02/18] include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
1
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
2
to file loongarch_pic_common.h, and rename structure name with
3
LoongArchPICCommonState.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 27 +------------------------
9
include/hw/intc/loongarch_pic_common.h | 28 ++++++++++++++++++++++++++
10
2 files changed, 29 insertions(+), 26 deletions(-)
11
12
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/intc/loongarch_pch_pic.h
15
+++ b/include/hw/intc/loongarch_pch_pic.h
16
@@ -XXX,XX +XXX,XX @@
17
18
#include "hw/intc/loongarch_pic_common.h"
19
20
+#define LoongArchPCHPIC LoongArchPICCommonState
21
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
22
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
23
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
24
25
-struct LoongArchPCHPIC {
26
- SysBusDevice parent_obj;
27
- qemu_irq parent_irq[64];
28
- uint64_t int_mask; /*0x020 interrupt mask register*/
29
- uint64_t htmsi_en; /*0x040 1=msi*/
30
- uint64_t intedge; /*0x060 edge=1 level =0*/
31
- uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
32
- uint64_t auto_crtl0; /*0x0c0*/
33
- uint64_t auto_crtl1; /*0x0e0*/
34
- uint64_t last_intirr; /* edge detection */
35
- uint64_t intirr; /* 0x380 interrupt request register */
36
- uint64_t intisr; /* 0x3a0 interrupt service register */
37
- /*
38
- * 0x3e0 interrupt level polarity selection
39
- * register 0 for high level trigger
40
- */
41
- uint64_t int_polarity;
42
-
43
- uint8_t route_entry[64]; /*0x100 - 0x138*/
44
- uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
45
-
46
- MemoryRegion iomem32_low;
47
- MemoryRegion iomem32_high;
48
- MemoryRegion iomem8;
49
- unsigned int irq_num;
50
-};
51
#endif /* HW_LOONGARCH_PCH_PIC_H */
52
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/intc/loongarch_pic_common.h
55
+++ b/include/hw/intc/loongarch_pic_common.h
56
@@ -XXX,XX +XXX,XX @@
57
#define STATUS_HI_START 0x4
58
#define POL_LO_START 0x40
59
#define POL_HI_START 0x44
60
+
61
+struct LoongArchPICCommonState {
62
+ SysBusDevice parent_obj;
63
+
64
+ qemu_irq parent_irq[64];
65
+ uint64_t int_mask; /* 0x020 interrupt mask register */
66
+ uint64_t htmsi_en; /* 0x040 1=msi */
67
+ uint64_t intedge; /* 0x060 edge=1 level=0 */
68
+ uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
69
+ uint64_t auto_crtl0; /* 0x0c0 */
70
+ uint64_t auto_crtl1; /* 0x0e0 */
71
+ uint64_t last_intirr; /* edge detection */
72
+ uint64_t intirr; /* 0x380 interrupt request register */
73
+ uint64_t intisr; /* 0x3a0 interrupt service register */
74
+ /*
75
+ * 0x3e0 interrupt level polarity selection
76
+ * register 0 for high level trigger
77
+ */
78
+ uint64_t int_polarity;
79
+
80
+ uint8_t route_entry[64]; /* 0x100 - 0x138 */
81
+ uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
82
+
83
+ MemoryRegion iomem32_low;
84
+ MemoryRegion iomem32_high;
85
+ MemoryRegion iomem8;
86
+ unsigned int irq_num;
87
+};
88
#endif /* HW_LOONGARCH_PIC_COMMON_H */
89
--
90
2.43.5
diff view generated by jsdifflib
New patch
[PULL 03/18] hw/intc/loongarch_pch: Merge instance_init() into realize()
1
Memory region is created in instance_init(), merge it into function
2
realize(). There is no special class_init() for loongarch_pch object.
1
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
hw/intc/loongarch_pch_pic.c | 15 ++++-----------
8
1 file changed, 4 insertions(+), 11 deletions(-)
9
10
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/intc/loongarch_pch_pic.c
13
+++ b/hw/intc/loongarch_pch_pic.c
14
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
15
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
16
{
17
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
18
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
19
20
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
21
error_setg(errp, "Invalid 'pic_irq_num'");
22
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
23
24
qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
25
qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
26
-}
27
-
28
-static void loongarch_pch_pic_init(Object *obj)
29
-{
30
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
31
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
32
-
33
- memory_region_init_io(&s->iomem32_low, obj,
34
+ memory_region_init_io(&s->iomem32_low, OBJECT(dev),
35
&loongarch_pch_pic_reg32_low_ops,
36
s, PCH_PIC_NAME(.reg32_part1), 0x100);
37
- memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
38
+ memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops,
39
s, PCH_PIC_NAME(.reg8), 0x2a0);
40
- memory_region_init_io(&s->iomem32_high, obj,
41
+ memory_region_init_io(&s->iomem32_high, OBJECT(dev),
42
&loongarch_pch_pic_reg32_high_ops,
43
s, PCH_PIC_NAME(.reg32_part2), 0xc60);
44
sysbus_init_mmio(sbd, &s->iomem32_low);
45
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_pch_pic_info = {
46
.name = TYPE_LOONGARCH_PCH_PIC,
47
.parent = TYPE_SYS_BUS_DEVICE,
48
.instance_size = sizeof(LoongArchPCHPIC),
49
- .instance_init = loongarch_pch_pic_init,
50
.class_init = loongarch_pch_pic_class_init,
51
};
52
53
--
54
2.43.5
diff view generated by jsdifflib
[PULL 5/5] target/loongarch: Fix CSR.DMW0-3.VSEG check
[PULL 04/18] hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
1
From: Jiajie Chen <c@jia.je>
1
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
2
vmstate_loongarch_pic_common, and with pic property rename
3
loongarch_pch_pic_properties with loongarch_pic_common_properties.
2
4
3
The previous code checks whether the highest 16 bits of virtual address
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
equal to that of CSR.DMW0-3. This is incorrect according to the spec,
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
and is corrected to compare only the highest four bits instead.
7
---
8
hw/intc/loongarch_pch_pic.c | 52 +++++++++++++++++++++++--------------
9
1 file changed, 32 insertions(+), 20 deletions(-)
6
10
7
Signed-off-by: Jiajie Chen <c@jia.je>
11
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
8
Reviewed-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20230614065556.2397513-1-c@jia.je>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
12
target/loongarch/tlb_helper.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/target/loongarch/tlb_helper.c
13
--- a/hw/intc/loongarch_pch_pic.c
18
+++ b/target/loongarch/tlb_helper.c
14
+++ b/hw/intc/loongarch_pch_pic.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
16
s->int_polarity = 0x0;
17
}
18
19
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
20
+{
21
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
22
+
23
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
24
+ error_setg(errp, "Invalid 'pic_irq_num'");
25
+ return;
26
+ }
27
+}
28
+
29
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
30
{
31
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
32
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
33
+ Error *local_err = NULL;
34
35
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
36
- error_setg(errp, "Invalid 'pic_irq_num'");
37
+ loongarch_pic_common_realize(dev, &local_err);
38
+ if (local_err) {
39
+ error_propagate(errp, local_err);
40
return;
20
}
41
}
21
42
22
plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
43
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
23
- base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS;
44
24
+ base_v = address >> R_CSR_DMW_VSEG_SHIFT;
45
}
25
/* Check direct map window */
46
26
for (int i = 0; i < 4; i++) {
47
-static Property loongarch_pch_pic_properties[] = {
27
- base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS;
48
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
28
+ base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
49
+static Property loongarch_pic_common_properties[] = {
29
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
50
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
30
*physical = dmw_va2pa(address);
51
DEFINE_PROP_END_OF_LIST(),
31
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
52
};
53
54
-static const VMStateDescription vmstate_loongarch_pch_pic = {
55
- .name = TYPE_LOONGARCH_PCH_PIC,
56
+static const VMStateDescription vmstate_loongarch_pic_common = {
57
+ .name = "loongarch_pch_pic",
58
.version_id = 1,
59
.minimum_version_id = 1,
60
.fields = (const VMStateField[]) {
61
- VMSTATE_UINT64(int_mask, LoongArchPCHPIC),
62
- VMSTATE_UINT64(htmsi_en, LoongArchPCHPIC),
63
- VMSTATE_UINT64(intedge, LoongArchPCHPIC),
64
- VMSTATE_UINT64(intclr, LoongArchPCHPIC),
65
- VMSTATE_UINT64(auto_crtl0, LoongArchPCHPIC),
66
- VMSTATE_UINT64(auto_crtl1, LoongArchPCHPIC),
67
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
68
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
69
- VMSTATE_UINT64(last_intirr, LoongArchPCHPIC),
70
- VMSTATE_UINT64(intirr, LoongArchPCHPIC),
71
- VMSTATE_UINT64(intisr, LoongArchPCHPIC),
72
- VMSTATE_UINT64(int_polarity, LoongArchPCHPIC),
73
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
74
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
75
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
76
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
77
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
78
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
79
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
80
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
81
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
82
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
83
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
84
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
85
VMSTATE_END_OF_LIST()
86
}
87
};
88
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
89
90
dc->realize = loongarch_pch_pic_realize;
91
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
92
- dc->vmsd = &vmstate_loongarch_pch_pic;
93
- device_class_set_props(dc, loongarch_pch_pic_properties);
94
+ dc->vmsd = &vmstate_loongarch_pic_common;
95
+ device_class_set_props(dc, loongarch_pic_common_properties);
96
}
97
98
static const TypeInfo loongarch_pch_pic_info = {
32
--
99
--
33
2.39.1
100
2.43.5
diff view generated by jsdifflib
New patch
[PULL 05/18] hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
1
Move some common functions to file loongarch_pic_common.c, the common
2
functions include loongarch_pic_common_realize(), property structure
3
loongarch_pic_common_properties and vmstate structure
4
vmstate_loongarch_pic_common.
1
5
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
8
---
9
hw/intc/loongarch_pch_pic.c | 37 +-----------------------------
10
hw/intc/loongarch_pic_common.c | 41 ++++++++++++++++++++++++++++++++++
11
2 files changed, 42 insertions(+), 36 deletions(-)
12
create mode 100644 hw/intc/loongarch_pic_common.c
13
14
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/loongarch_pch_pic.c
17
+++ b/hw/intc/loongarch_pch_pic.c
18
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
19
s->int_polarity = 0x0;
20
}
21
22
-static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
23
-{
24
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
25
-
26
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
27
- error_setg(errp, "Invalid 'pic_irq_num'");
28
- return;
29
- }
30
-}
31
-
32
+#include "loongarch_pic_common.c"
33
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
34
{
35
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
36
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
37
38
}
39
40
-static Property loongarch_pic_common_properties[] = {
41
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
42
- DEFINE_PROP_END_OF_LIST(),
43
-};
44
-
45
-static const VMStateDescription vmstate_loongarch_pic_common = {
46
- .name = "loongarch_pch_pic",
47
- .version_id = 1,
48
- .minimum_version_id = 1,
49
- .fields = (const VMStateField[]) {
50
- VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
51
- VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
52
- VMSTATE_UINT64(intedge, LoongArchPICCommonState),
53
- VMSTATE_UINT64(intclr, LoongArchPICCommonState),
54
- VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
55
- VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
56
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
57
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
58
- VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
59
- VMSTATE_UINT64(intirr, LoongArchPICCommonState),
60
- VMSTATE_UINT64(intisr, LoongArchPICCommonState),
61
- VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
62
- VMSTATE_END_OF_LIST()
63
- }
64
-};
65
-
66
static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
67
{
68
DeviceClass *dc = DEVICE_CLASS(klass);
69
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/hw/intc/loongarch_pic_common.c
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * QEMU Loongson 7A1000 I/O interrupt controller.
78
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
82
+{
83
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
84
+
85
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
86
+ error_setg(errp, "Invalid 'pic_irq_num'");
87
+ return;
88
+ }
89
+}
90
+
91
+static Property loongarch_pic_common_properties[] = {
92
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
93
+ DEFINE_PROP_END_OF_LIST(),
94
+};
95
+
96
+static const VMStateDescription vmstate_loongarch_pic_common = {
97
+ .name = "loongarch_pch_pic",
98
+ .version_id = 1,
99
+ .minimum_version_id = 1,
100
+ .fields = (const VMStateField[]) {
101
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
102
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
103
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
104
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
105
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
106
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
107
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
108
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
109
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
110
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
111
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
112
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
113
+ VMSTATE_END_OF_LIST()
114
+ }
115
+};
116
--
117
2.43.5
diff view generated by jsdifflib
[PULL 1/5] hw/loongarch/virt: Add cpu arch_id support
[PULL 06/18] hw/intc/loongarch_pch: Inherit from loongarch_pic_common
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
2
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
3
its own realize() function.
2
4
3
With acpi madt table, there is cpu physical coreid, which may
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
be different with logical id in qemu. This patch adds cpu arch_id
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
support, and fill madt table with arch_id. For the present cpu
7
---
6
arch_id is still equal to logical id.
8
hw/intc/loongarch_pch_pic.c | 38 ++++++++++++--------------
9
hw/intc/loongarch_pic_common.c | 32 +++++++++++++++++++++-
10
hw/intc/meson.build | 2 +-
11
include/hw/intc/loongarch_pch_pic.h | 21 +++++++++++---
12
include/hw/intc/loongarch_pic_common.h | 10 +++++++
13
5 files changed, 77 insertions(+), 26 deletions(-)
7
14
8
Reviewed-by: Song Gao <gaosong@loongson.cn>
15
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
9
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
Message-Id: <20230613120552.2471420-2-zhaotianrui@loongson.cn>
12
---
13
hw/loongarch/acpi-build.c | 20 ++++++++++++++------
14
hw/loongarch/virt.c | 34 ++++++++++++++++++++++++++++++++--
15
2 files changed, 46 insertions(+), 8 deletions(-)
16
17
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/loongarch/acpi-build.c
17
--- a/hw/intc/loongarch_pch_pic.c
20
+++ b/hw/loongarch/acpi-build.c
18
+++ b/hw/intc/loongarch_pch_pic.c
21
@@ -XXX,XX +XXX,XX @@ static void
19
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
22
build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
20
s->int_polarity = 0x0;
21
}
22
23
-#include "loongarch_pic_common.c"
24
-static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
25
+static void loongarch_pic_realize(DeviceState *dev, Error **errp)
23
{
26
{
24
MachineState *ms = MACHINE(lams);
27
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
25
- int i;
28
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
26
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
29
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
27
+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
30
+ LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev);
28
+ int i, arch_id;
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
29
AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id,
32
Error *local_err = NULL;
30
.oem_table_id = lams->oem_table_id };
33
31
34
- loongarch_pic_common_realize(dev, &local_err);
32
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
35
+ lpc->parent_realize(dev, &local_err);
33
build_append_int_noprefix(table_data, 0, 4);
36
if (local_err) {
34
build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
37
error_propagate(errp, local_err);
35
38
return;
36
- for (i = 0; i < ms->smp.cpus; i++) {
39
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
37
+ for (i = 0; i < arch_ids->len; i++) {
40
38
/* Processor Core Interrupt Controller Structure */
41
}
39
+ arch_id = arch_ids->cpus[i].arch_id;
42
43
-static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
44
+static void loongarch_pic_class_init(ObjectClass *klass, void *data)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
+ LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass);
48
49
- dc->realize = loongarch_pch_pic_realize;
50
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
51
- dc->vmsd = &vmstate_loongarch_pic_common;
52
- device_class_set_props(dc, loongarch_pic_common_properties);
53
+ device_class_set_parent_realize(dc, loongarch_pic_realize,
54
+ &lpc->parent_realize);
55
}
56
57
-static const TypeInfo loongarch_pch_pic_info = {
58
- .name = TYPE_LOONGARCH_PCH_PIC,
59
- .parent = TYPE_SYS_BUS_DEVICE,
60
- .instance_size = sizeof(LoongArchPCHPIC),
61
- .class_init = loongarch_pch_pic_class_init,
62
+static const TypeInfo loongarch_pic_types[] = {
63
+ {
64
+ .name = TYPE_LOONGARCH_PIC,
65
+ .parent = TYPE_LOONGARCH_PIC_COMMON,
66
+ .instance_size = sizeof(LoongarchPICState),
67
+ .class_size = sizeof(LoongarchPICClass),
68
+ .class_init = loongarch_pic_class_init,
69
+ }
70
};
71
72
-static void loongarch_pch_pic_register_types(void)
73
-{
74
- type_register_static(&loongarch_pch_pic_info);
75
-}
76
-
77
-type_init(loongarch_pch_pic_register_types)
78
+DEFINE_TYPES(loongarch_pic_types)
79
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/intc/loongarch_pic_common.c
82
+++ b/hw/intc/loongarch_pic_common.c
83
@@ -XXX,XX +XXX,XX @@
84
* Copyright (C) 2024 Loongson Technology Corporation Limited
85
*/
86
87
+#include "qemu/osdep.h"
88
+#include "qapi/error.h"
89
+#include "hw/intc/loongarch_pic_common.h"
90
+#include "hw/qdev-properties.h"
91
+#include "migration/vmstate.h"
40
+
92
+
41
build_append_int_noprefix(table_data, 17, 1); /* Type */
93
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
42
build_append_int_noprefix(table_data, 15, 1); /* Length */
94
{
43
build_append_int_noprefix(table_data, 1, 1); /* Version */
95
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
44
build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
45
- build_append_int_noprefix(table_data, i, 4); /* Core ID */
97
46
+ build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */
98
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
47
build_append_int_noprefix(table_data, 1, 4); /* Flags */
99
error_setg(errp, "Invalid 'pic_irq_num'");
100
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
101
VMSTATE_END_OF_LIST()
48
}
102
}
49
103
};
50
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
51
static void
52
build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
53
{
54
- uint64_t i;
55
+ int i, arch_id;
56
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
57
MachineState *ms = MACHINE(lams);
58
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
59
+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
60
AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
61
.oem_table_id = lams->oem_table_id };
62
63
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
64
build_append_int_noprefix(table_data, 1, 4); /* Reserved */
65
build_append_int_noprefix(table_data, 0, 8); /* Reserved */
66
67
- for (i = 0; i < ms->smp.cpus; ++i) {
68
+ for (i = 0; i < arch_ids->len; ++i) {
69
+ arch_id = arch_ids->cpus[i].arch_id;
70
+
104
+
71
/* Processor Local APIC/SAPIC Affinity Structure */
105
+static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
72
build_append_int_noprefix(table_data, 0, 1); /* Type */
106
+{
73
build_append_int_noprefix(table_data, 16, 1); /* Length */
107
+ DeviceClass *dc = DEVICE_CLASS(klass);
74
/* Proximity Domain [7:0] */
108
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
75
build_append_int_noprefix(table_data, 0, 1);
76
- build_append_int_noprefix(table_data, i, 1); /* APIC ID */
77
+ build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */
78
/* Flags, Table 5-36 */
79
build_append_int_noprefix(table_data, 1, 4);
80
build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
81
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/loongarch/virt.c
84
+++ b/hw/loongarch/virt.c
85
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
86
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
87
int i;
88
hwaddr fdt_base;
89
+ const CPUArchIdList *possible_cpus;
90
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
91
+ CPUState *cpu;
92
93
if (!cpu_model) {
94
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
95
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
96
}
97
create_fdt(lams);
98
/* Init CPUs */
99
- for (i = 0; i < machine->smp.cpus; i++) {
100
- cpu_create(machine->cpu_type);
101
+
109
+
102
+ possible_cpus = mc->possible_cpu_arch_ids(machine);
110
+ device_class_set_parent_realize(dc, loongarch_pic_common_realize,
103
+ for (i = 0; i < possible_cpus->len; i++) {
111
+ &lpcc->parent_realize);
104
+ cpu = cpu_create(machine->cpu_type);
112
+ device_class_set_props(dc, loongarch_pic_common_properties);
105
+ cpu->cpu_index = i;
113
+ dc->vmsd = &vmstate_loongarch_pic_common;
106
+ machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
107
}
108
fdt_add_cpu_nodes(lams);
109
/* Add memory region */
110
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
111
return NULL;
112
}
113
114
+static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
115
+{
116
+ int n;
117
+ unsigned int max_cpus = ms->smp.max_cpus;
118
+
119
+ if (ms->possible_cpus) {
120
+ assert(ms->possible_cpus->len == max_cpus);
121
+ return ms->possible_cpus;
122
+ }
123
+
124
+ ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
125
+ sizeof(CPUArchId) * max_cpus);
126
+ ms->possible_cpus->len = max_cpus;
127
+ for (n = 0; n < ms->possible_cpus->len; n++) {
128
+ ms->possible_cpus->cpus[n].type = ms->cpu_type;
129
+ ms->possible_cpus->cpus[n].arch_id = n;
130
+ ms->possible_cpus->cpus[n].props.has_core_id = true;
131
+ ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;
132
+ }
133
+ return ms->possible_cpus;
134
+}
114
+}
135
+
115
+
136
static void loongarch_class_init(ObjectClass *oc, void *data)
116
+static const TypeInfo loongarch_pic_common_types[] = {
137
{
117
+ {
138
MachineClass *mc = MACHINE_CLASS(oc);
118
+ .name = TYPE_LOONGARCH_PIC_COMMON,
139
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
119
+ .parent = TYPE_SYS_BUS_DEVICE,
140
mc->block_default_type = IF_VIRTIO;
120
+ .instance_size = sizeof(LoongArchPICCommonState),
141
mc->default_boot_order = "c";
121
+ .class_size = sizeof(LoongArchPICCommonClass),
142
mc->no_cdrom = 1;
122
+ .class_init = loongarch_pic_common_class_init,
143
+ mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
123
+ .abstract = true,
144
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
124
+ }
145
mc->default_nic = "virtio-net-pci";
125
+};
146
hc->plug = loongarch_machine_device_plug_cb;
126
+
127
+DEFINE_TYPES(loongarch_pic_common_types)
128
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/intc/meson.build
131
+++ b/hw/intc/meson.build
132
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
133
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
134
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
135
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
136
-specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
137
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c', 'loongarch_pic_common.c'))
138
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
139
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
140
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
141
index XXXXXXX..XXXXXXX 100644
142
--- a/include/hw/intc/loongarch_pch_pic.h
143
+++ b/include/hw/intc/loongarch_pch_pic.h
144
@@ -XXX,XX +XXX,XX @@
145
146
#include "hw/intc/loongarch_pic_common.h"
147
148
-#define LoongArchPCHPIC LoongArchPICCommonState
149
-#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
150
-#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
151
-OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
152
+#define TYPE_LOONGARCH_PIC "loongarch_pic"
153
+#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PIC#name
154
+OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
155
+
156
+struct LoongarchPICState {
157
+ LoongArchPICCommonState parent_obj;
158
+};
159
+
160
+struct LoongarchPICClass {
161
+ LoongArchPICCommonClass parent_class;
162
+
163
+ DeviceRealize parent_realize;
164
+};
165
+
166
+#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
167
+typedef struct LoongArchPICCommonState LoongArchPCHPIC;
168
+#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
169
170
#endif /* HW_LOONGARCH_PCH_PIC_H */
171
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
172
index XXXXXXX..XXXXXXX 100644
173
--- a/include/hw/intc/loongarch_pic_common.h
174
+++ b/include/hw/intc/loongarch_pic_common.h
175
@@ -XXX,XX +XXX,XX @@
176
#define POL_LO_START 0x40
177
#define POL_HI_START 0x44
178
179
+#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
180
+OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
181
+ LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
182
+
183
struct LoongArchPICCommonState {
184
SysBusDevice parent_obj;
185
186
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonState {
187
MemoryRegion iomem8;
188
unsigned int irq_num;
189
};
190
+
191
+struct LoongArchPICCommonClass {
192
+ SysBusDeviceClass parent_class;
193
+
194
+ DeviceRealize parent_realize;
195
+};
196
#endif /* HW_LOONGARCH_PIC_COMMON_H */
147
--
197
--
148
2.39.1
198
2.43.5
diff view generated by jsdifflib
[PULL 3/5] hw/loongarch: Add numa support
[PULL 07/18] hw/intc/loongarch_pch: Add pre_save and post_load interfaces
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
Add vmstate pre_save and post_load interfaces, which can be used
2
by pic kvm driver in future.
2
3
3
1. Implement some functions for LoongArch numa support;
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
2. Implement fdt_add_memory_node() for fdt;
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
3. build_srat() fills node_id and adds build numa memory.
6
---
7
hw/intc/loongarch_pic_common.c | 26 ++++++++++++++++++++++++++
8
include/hw/intc/loongarch_pic_common.h | 2 ++
9
2 files changed, 28 insertions(+)
6
10
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
11
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
8
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn>
11
---
12
hw/loongarch/Kconfig | 1 +
13
hw/loongarch/acpi-build.c | 60 +++++++++++++++++-----
14
hw/loongarch/virt.c | 102 +++++++++++++++++++++++++++++++++-----
15
3 files changed, 139 insertions(+), 24 deletions(-)
16
17
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/loongarch/Kconfig
13
--- a/hw/intc/loongarch_pic_common.c
20
+++ b/hw/loongarch/Kconfig
14
+++ b/hw/intc/loongarch_pic_common.c
21
@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
22
select FW_CFG_DMA
23
select DIMM
24
select PFLASH_CFI01
25
+ select ACPI_HMAT
26
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/loongarch/acpi-build.c
29
+++ b/hw/loongarch/acpi-build.c
30
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
31
#include "sysemu/tpm.h"
16
#include "hw/qdev-properties.h"
32
#include "hw/platform-bus.h"
17
#include "migration/vmstate.h"
33
#include "hw/acpi/aml-build.h"
18
34
+#include "hw/acpi/hmat.h"
19
+static int loongarch_pic_pre_save(void *opaque)
35
20
+{
36
#define ACPI_BUILD_ALIGN_SIZE 0x1000
21
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
37
#define ACPI_BUILD_TABLE_SIZE 0x20000
22
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
38
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
39
static void
40
build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
41
{
42
- int i, arch_id;
43
+ int i, arch_id, node_id;
44
+ uint64_t mem_len, mem_base;
45
+ int nb_numa_nodes = machine->numa_state->num_nodes;
46
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
47
- MachineState *ms = MACHINE(lams);
48
- MachineClass *mc = MACHINE_GET_CLASS(ms);
49
- const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
50
+ MachineClass *mc = MACHINE_GET_CLASS(lams);
51
+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
52
AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
53
.oem_table_id = lams->oem_table_id };
54
55
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
56
57
for (i = 0; i < arch_ids->len; ++i) {
58
arch_id = arch_ids->cpus[i].arch_id;
59
+ node_id = arch_ids->cpus[i].props.node_id;
60
61
/* Processor Local APIC/SAPIC Affinity Structure */
62
build_append_int_noprefix(table_data, 0, 1); /* Type */
63
build_append_int_noprefix(table_data, 16, 1); /* Length */
64
/* Proximity Domain [7:0] */
65
- build_append_int_noprefix(table_data, 0, 1);
66
+ build_append_int_noprefix(table_data, node_id, 1);
67
build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */
68
/* Flags, Table 5-36 */
69
build_append_int_noprefix(table_data, 1, 4);
70
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
71
build_append_int_noprefix(table_data, 0, 4); /* Reserved */
72
}
73
74
+ /* Node0 */
75
build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE,
76
0, MEM_AFFINITY_ENABLED);
77
+ mem_base = VIRT_HIGHMEM_BASE;
78
+ if (!nb_numa_nodes) {
79
+ mem_len = machine->ram_size - VIRT_LOWMEM_SIZE;
80
+ } else {
81
+ mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE;
82
+ }
83
+ if (mem_len)
84
+ build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_ENABLED);
85
+
23
+
86
+ /* Node1 - Nodemax */
24
+ if (lpcc->pre_save) {
87
+ if (nb_numa_nodes) {
25
+ return lpcc->pre_save(s);
88
+ mem_base += mem_len;
89
+ for (i = 1; i < nb_numa_nodes; ++i) {
90
+ if (machine->numa_state->nodes[i].node_mem > 0) {
91
+ build_srat_memory(table_data, mem_base,
92
+ machine->numa_state->nodes[i].node_mem, i,
93
+ MEM_AFFINITY_ENABLED);
94
+ mem_base += machine->numa_state->nodes[i].node_mem;
95
+ }
96
+ }
97
+ }
98
99
- build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - VIRT_LOWMEM_SIZE,
100
- 0, MEM_AFFINITY_ENABLED);
101
-
102
- if (ms->device_memory) {
103
- build_srat_memory(table_data, ms->device_memory->base,
104
- memory_region_size(&ms->device_memory->mr),
105
- 0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
106
+ if (machine->device_memory) {
107
+ build_srat_memory(table_data, machine->device_memory->base,
108
+ memory_region_size(&machine->device_memory->mr),
109
+ nb_numa_nodes - 1,
110
+ MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
111
}
112
113
acpi_table_end(linker, &table);
114
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
115
acpi_add_table(table_offsets, tables_blob);
116
build_srat(tables_blob, tables->linker, machine);
117
118
+ if (machine->numa_state->num_nodes) {
119
+ if (machine->numa_state->have_numa_distance) {
120
+ acpi_add_table(table_offsets, tables_blob);
121
+ build_slit(tables_blob, tables->linker, machine, lams->oem_id,
122
+ lams->oem_table_id);
123
+ }
124
+ if (machine->numa_state->hmat_enabled) {
125
+ acpi_add_table(table_offsets, tables_blob);
126
+ build_hmat(tables_blob, tables->linker, machine->numa_state,
127
+ lams->oem_id, lams->oem_table_id);
128
+ }
129
+ }
26
+ }
130
+
27
+
131
acpi_add_table(table_offsets, tables_blob);
28
+ return 0;
132
{
29
+}
133
AcpiMcfgInfo mcfg = {
30
+
134
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
31
+static int loongarch_pic_post_load(void *opaque, int version_id)
135
index XXXXXXX..XXXXXXX 100644
136
--- a/hw/loongarch/virt.c
137
+++ b/hw/loongarch/virt.c
138
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
139
for (num = smp_cpus - 1; num >= 0; num--) {
140
char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
141
LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
142
+ CPUState *cs = CPU(cpu);
143
144
qemu_fdt_add_subnode(ms->fdt, nodename);
145
qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
146
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
147
cpu->dtb_compatible);
148
+ if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
149
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
150
+ ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
151
+ }
152
qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
153
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
154
qemu_fdt_alloc_phandle(ms->fdt));
155
@@ -XXX,XX +XXX,XX @@ static void fdt_add_irqchip_node(LoongArchMachineState *lams)
156
g_free(nodename);
157
}
158
159
+static void fdt_add_memory_node(MachineState *ms,
160
+ uint64_t base, uint64_t size, int node_id)
161
+{
32
+{
162
+ char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
33
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
34
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
163
+
35
+
164
+ qemu_fdt_add_subnode(ms->fdt, nodename);
36
+ if (lpcc->post_load) {
165
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
37
+ return lpcc->post_load(s, version_id);
166
+ qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
167
+
168
+ if (ms->numa_state && ms->numa_state->num_nodes) {
169
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id);
170
+ }
38
+ }
171
+
39
+
172
+ g_free(nodename);
40
+ return 0;
173
+}
41
+}
174
+
42
+
175
#define PM_BASE 0x10080000
43
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
176
#define PM_SIZE 0x100
177
#define PM_CTRL 0x10
178
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
179
const char *cpu_model = machine->cpu_type;
180
ram_addr_t offset = 0;
181
ram_addr_t ram_size = machine->ram_size;
182
- uint64_t highram_size = 0;
183
+ uint64_t highram_size = 0, phyAddr = 0;
184
MemoryRegion *address_space_mem = get_system_memory();
185
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
186
+ int nb_numa_nodes = machine->numa_state->num_nodes;
187
+ NodeInfo *numa_info = machine->numa_state->nodes;
188
int i;
189
hwaddr fdt_base;
190
const CPUArchIdList *possible_cpus;
191
MachineClass *mc = MACHINE_GET_CLASS(machine);
192
CPUState *cpu;
193
+ char *ramName = NULL;
194
195
if (!cpu_model) {
196
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
197
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
198
machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
199
}
200
fdt_add_cpu_nodes(lams);
201
- /* Add memory region */
202
- memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
203
- machine->ram, 0, 256 * MiB);
204
- memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
205
- offset += 256 * MiB;
206
- memmap_add_entry(0, 256 * MiB, 1);
207
- highram_size = ram_size - 256 * MiB;
208
- memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
209
- machine->ram, offset, highram_size);
210
- memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
211
- memmap_add_entry(0x90000000, highram_size, 1);
212
+
213
+ /* Node0 memory */
214
+ memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
215
+ fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
216
+ memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram",
217
+ machine->ram, offset, VIRT_LOWMEM_SIZE);
218
+ memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem);
219
+
220
+ offset += VIRT_LOWMEM_SIZE;
221
+ if (nb_numa_nodes > 0) {
222
+ assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
223
+ highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
224
+ } else {
225
+ highram_size = ram_size - VIRT_LOWMEM_SIZE;
226
+ }
227
+ phyAddr = VIRT_HIGHMEM_BASE;
228
+ memmap_add_entry(phyAddr, highram_size, 1);
229
+ fdt_add_memory_node(machine, phyAddr, highram_size, 0);
230
+ memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram",
231
+ machine->ram, offset, highram_size);
232
+ memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem);
233
+
234
+ /* Node1 - Nodemax memory */
235
+ offset += highram_size;
236
+ phyAddr += highram_size;
237
+
238
+ for (i = 1; i < nb_numa_nodes; i++) {
239
+ MemoryRegion *nodemem = g_new(MemoryRegion, 1);
240
+ ramName = g_strdup_printf("loongarch.node%d.ram", i);
241
+ memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
242
+ offset, numa_info[i].node_mem);
243
+ memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
244
+ memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
245
+ fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
246
+ offset += numa_info[i].node_mem;
247
+ phyAddr += numa_info[i].node_mem;
248
+ }
249
250
/* initialize device memory address space */
251
if (machine->ram_size < machine->maxram_size) {
252
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
253
return ms->possible_cpus;
254
}
255
256
+static CpuInstanceProperties
257
+virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
258
+{
259
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
260
+ const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
261
+
262
+ assert(cpu_index < possible_cpus->len);
263
+ return possible_cpus->cpus[cpu_index].props;
264
+}
265
+
266
+static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
267
+{
268
+ int64_t nidx = 0;
269
+
270
+ if (ms->numa_state->num_nodes) {
271
+ nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
272
+ if (ms->numa_state->num_nodes <= nidx) {
273
+ nidx = ms->numa_state->num_nodes - 1;
274
+ }
275
+ }
276
+ return nidx;
277
+}
278
+
279
static void loongarch_class_init(ObjectClass *oc, void *data)
280
{
44
{
281
MachineClass *mc = MACHINE_CLASS(oc);
45
LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
282
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
46
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
283
mc->default_boot_order = "c";
47
.name = "loongarch_pch_pic",
284
mc->no_cdrom = 1;
48
.version_id = 1,
285
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
49
.minimum_version_id = 1,
286
+ mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
50
+ .pre_save = loongarch_pic_pre_save,
287
+ mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
51
+ .post_load = loongarch_pic_post_load,
288
+ mc->numa_mem_supported = true;
52
.fields = (const VMStateField[]) {
289
+ mc->auto_enable_numa_with_memhp = true;
53
VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
290
+ mc->auto_enable_numa_with_memdev = true;
54
VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
291
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
55
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
292
mc->default_nic = "virtio-net-pci";
56
index XXXXXXX..XXXXXXX 100644
293
hc->plug = loongarch_machine_device_plug_cb;
57
--- a/include/hw/intc/loongarch_pic_common.h
58
+++ b/include/hw/intc/loongarch_pic_common.h
59
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonClass {
60
SysBusDeviceClass parent_class;
61
62
DeviceRealize parent_realize;
63
+ int (*pre_save)(LoongArchPICCommonState *s);
64
+ int (*post_load)(LoongArchPICCommonState *s, int version_id);
65
};
66
#endif /* HW_LOONGARCH_PIC_COMMON_H */
294
--
67
--
295
2.39.1
68
2.43.5
diff view generated by jsdifflib
[PULL 4/5] hw/loongarch: Supplement cpu topology arguments
[PULL 08/18] hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
2
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
3
separately. Also remove unnecessary header files.
2
4
3
Supplement LoongArch cpu topology arguments, including support socket
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
and threads per core.
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
hw/intc/loongarch_pch_pic.c | 24 ++++++++++--------------
9
hw/loongarch/virt.c | 2 +-
10
include/hw/intc/loongarch_pch_pic.h | 4 ----
11
3 files changed, 11 insertions(+), 19 deletions(-)
5
12
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
8
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
Message-Id: <20230613123251.2471878-1-zhaotianrui@loongson.cn>
11
---
12
hw/loongarch/acpi-build.c | 4 ++++
13
hw/loongarch/virt.c | 9 ++++++++-
14
2 files changed, 12 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/loongarch/acpi-build.c
15
--- a/hw/intc/loongarch_pch_pic.c
19
+++ b/hw/loongarch/acpi-build.c
16
+++ b/hw/intc/loongarch_pch_pic.c
20
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
17
@@ -XXX,XX +XXX,XX @@
21
acpi_add_table(table_offsets, tables_blob);
18
22
build_madt(tables_blob, tables->linker, lams);
19
#include "qemu/osdep.h"
23
20
#include "qemu/bitops.h"
24
+ acpi_add_table(table_offsets, tables_blob);
21
-#include "hw/sysbus.h"
25
+ build_pptt(tables_blob, tables->linker, machine,
22
-#include "hw/loongarch/virt.h"
26
+ lams->oem_id, lams->oem_table_id);
23
-#include "hw/pci-host/ls7a.h"
27
+
24
#include "hw/irq.h"
28
acpi_add_table(table_offsets, tables_blob);
25
#include "hw/intc/loongarch_pch_pic.h"
29
build_srat(tables_blob, tables->linker, machine);
26
-#include "hw/qdev-properties.h"
30
27
-#include "migration/vmstate.h"
28
#include "trace.h"
29
#include "qapi/error.h"
30
31
-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
32
+static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
33
+ int level)
34
{
35
uint64_t val;
36
int irq;
37
@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
38
39
static void pch_pic_irq_handler(void *opaque, int irq, int level)
40
{
41
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
42
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
43
uint64_t mask = 1ULL << irq;
44
45
assert(irq < s->irq_num);
46
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
47
static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
48
unsigned size)
49
{
50
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
51
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
52
uint64_t val = 0;
53
uint32_t offset = addr & 0xfff;
54
55
@@ -XXX,XX +XXX,XX @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
56
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
57
uint64_t value, unsigned size)
58
{
59
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
60
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
61
uint32_t offset, old_valid, data = (uint32_t)value;
62
uint64_t old, int_mask;
63
offset = addr & 0xfff;
64
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
65
static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
66
unsigned size)
67
{
68
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
69
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
70
uint64_t val = 0;
71
uint32_t offset = addr & 0xfff;
72
73
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
74
static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
75
uint64_t value, unsigned size)
76
{
77
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
78
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
79
uint32_t offset, data = (uint32_t)value;
80
offset = addr & 0xfff;
81
82
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
83
static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
84
unsigned size)
85
{
86
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
87
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
88
uint64_t val = 0;
89
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
90
int64_t offset_tmp;
91
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
92
static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
93
uint64_t data, unsigned size)
94
{
95
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
97
int32_t offset_tmp;
98
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
99
100
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
101
102
static void loongarch_pch_pic_reset(DeviceState *d)
103
{
104
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
105
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
106
int i;
107
108
s->int_mask = -1;
31
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
109
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
32
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/loongarch/virt.c
111
--- a/hw/loongarch/virt.c
34
+++ b/hw/loongarch/virt.c
112
+++ b/hw/loongarch/virt.c
35
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
113
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
36
for (n = 0; n < ms->possible_cpus->len; n++) {
114
/* Add Extend I/O Interrupt Controller node */
37
ms->possible_cpus->cpus[n].type = ms->cpu_type;
115
fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
38
ms->possible_cpus->cpus[n].arch_id = n;
116
39
+
117
- pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
40
+ ms->possible_cpus->cpus[n].props.has_socket_id = true;
118
+ pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
41
+ ms->possible_cpus->cpus[n].props.socket_id =
119
num = VIRT_PCH_PIC_IRQ_NUM;
42
+ n / (ms->smp.cores * ms->smp.threads);
120
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
43
ms->possible_cpus->cpus[n].props.has_core_id = true;
121
d = SYS_BUS_DEVICE(pch_pic);
44
- ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores;
122
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
45
+ ms->possible_cpus->cpus[n].props.core_id =
123
index XXXXXXX..XXXXXXX 100644
46
+ n / ms->smp.threads % ms->smp.cores;
124
--- a/include/hw/intc/loongarch_pch_pic.h
47
+ ms->possible_cpus->cpus[n].props.has_thread_id = true;
125
+++ b/include/hw/intc/loongarch_pch_pic.h
48
+ ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;
126
@@ -XXX,XX +XXX,XX @@ struct LoongarchPICClass {
49
}
127
DeviceRealize parent_realize;
50
return ms->possible_cpus;
128
};
51
}
129
130
-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
131
-typedef struct LoongArchPICCommonState LoongArchPCHPIC;
132
-#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
133
-
134
#endif /* HW_LOONGARCH_PCH_PIC_H */
52
--
135
--
53
2.39.1
136
2.43.5
54
55
diff view generated by jsdifflib
New patch
[PULL 09/18] include: Add loongarch_extioi_common header file
1
Add common header file include/hw/intc/loongarch_extioi_common.h, and
2
move some macro definition from include/hw/intc/loongarch_extioi.h to
3
the common header file.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_extioi.h | 50 +------------------
9
include/hw/intc/loongarch_extioi_common.h | 58 +++++++++++++++++++++++
10
2 files changed, 59 insertions(+), 49 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_extioi_common.h
12
13
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/loongarch_extioi.h
16
+++ b/include/hw/intc/loongarch_extioi.h
17
@@ -XXX,XX +XXX,XX @@
18
* Copyright (C) 2021 Loongson Technology Corporation Limited
19
*/
20
21
-#include "hw/sysbus.h"
22
-#include "hw/loongarch/virt.h"
23
-
24
#ifndef LOONGARCH_EXTIOI_H
25
#define LOONGARCH_EXTIOI_H
26
27
-#define LS3A_INTC_IP 8
28
-#define EXTIOI_IRQS (256)
29
-#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
30
-/* irq from EXTIOI is routed to no more than 4 cpus */
31
-#define EXTIOI_CPUS (4)
32
-/* map to ipnum per 32 irqs */
33
-#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
34
-#define EXTIOI_IRQS_COREMAP_SIZE 256
35
-#define EXTIOI_IRQS_NODETYPE_COUNT 16
36
-#define EXTIOI_IRQS_GROUP_COUNT 8
37
-
38
-#define APIC_OFFSET 0x400
39
-#define APIC_BASE (0x1000ULL + APIC_OFFSET)
40
-
41
-#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
42
-#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
43
-#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
44
-#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
45
-#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
46
-#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
47
-#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
48
-#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
49
-#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
50
-#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
51
-#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
52
-#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
53
-#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
54
-#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
55
-#define EXTIOI_SIZE 0x800
56
-
57
-#define EXTIOI_VIRT_BASE (0x40000000)
58
-#define EXTIOI_VIRT_SIZE (0x1000)
59
-#define EXTIOI_VIRT_FEATURES (0x0)
60
-#define EXTIOI_HAS_VIRT_EXTENSION (0)
61
-#define EXTIOI_HAS_ENABLE_OPTION (1)
62
-#define EXTIOI_HAS_INT_ENCODE (2)
63
-#define EXTIOI_HAS_CPU_ENCODE (3)
64
-#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
65
- | BIT(EXTIOI_HAS_ENABLE_OPTION) \
66
- | BIT(EXTIOI_HAS_CPU_ENCODE))
67
-#define EXTIOI_VIRT_CONFIG (0x4)
68
-#define EXTIOI_ENABLE (1)
69
-#define EXTIOI_ENABLE_INT_ENCODE (2)
70
-#define EXTIOI_ENABLE_CPU_ENCODE (3)
71
-#define EXTIOI_VIRT_COREMAP_START (0x40)
72
-#define EXTIOI_VIRT_COREMAP_END (0x240)
73
+#include "hw/intc/loongarch_extioi_common.h"
74
75
typedef struct ExtIOICore {
76
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
77
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
78
new file mode 100644
79
index XXXXXXX..XXXXXXX
80
--- /dev/null
81
+++ b/include/hw/intc/loongarch_extioi_common.h
82
@@ -XXX,XX +XXX,XX @@
83
+/* SPDX-License-Identifier: GPL-2.0-or-later */
84
+/*
85
+ * LoongArch 3A5000 ext interrupt controller definitions
86
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
87
+ */
88
+
89
+#ifndef LOONGARCH_EXTIOI_COMMON_H
90
+#define LOONGARCH_EXTIOI_COMMON_H
91
+
92
+#include "hw/sysbus.h"
93
+#include "hw/loongarch/virt.h"
94
+
95
+#define LS3A_INTC_IP 8
96
+#define EXTIOI_IRQS (256)
97
+#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
98
+/* irq from EXTIOI is routed to no more than 4 cpus */
99
+#define EXTIOI_CPUS (4)
100
+/* map to ipnum per 32 irqs */
101
+#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
102
+#define EXTIOI_IRQS_COREMAP_SIZE 256
103
+#define EXTIOI_IRQS_NODETYPE_COUNT 16
104
+#define EXTIOI_IRQS_GROUP_COUNT 8
105
+
106
+#define APIC_OFFSET 0x400
107
+#define APIC_BASE (0x1000ULL + APIC_OFFSET)
108
+#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
109
+#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
110
+#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
111
+#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
112
+#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
113
+#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
114
+#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
115
+#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
116
+#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
117
+#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
118
+#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
119
+#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
120
+#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
121
+#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
122
+#define EXTIOI_SIZE 0x800
123
+
124
+#define EXTIOI_VIRT_BASE (0x40000000)
125
+#define EXTIOI_VIRT_SIZE (0x1000)
126
+#define EXTIOI_VIRT_FEATURES (0x0)
127
+#define EXTIOI_HAS_VIRT_EXTENSION (0)
128
+#define EXTIOI_HAS_ENABLE_OPTION (1)
129
+#define EXTIOI_HAS_INT_ENCODE (2)
130
+#define EXTIOI_HAS_CPU_ENCODE (3)
131
+#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
132
+ | BIT(EXTIOI_HAS_ENABLE_OPTION) \
133
+ | BIT(EXTIOI_HAS_CPU_ENCODE))
134
+#define EXTIOI_VIRT_CONFIG (0x4)
135
+#define EXTIOI_ENABLE (1)
136
+#define EXTIOI_ENABLE_INT_ENCODE (2)
137
+#define EXTIOI_ENABLE_CPU_ENCODE (3)
138
+#define EXTIOI_VIRT_COREMAP_START (0x40)
139
+#define EXTIOI_VIRT_COREMAP_END (0x240)
140
+#endif /* LOONGARCH_EXTIOI_H */
141
--
142
2.43.5
diff view generated by jsdifflib
New patch
[PULL 10/18] include: Move struct LoongArchExtIOI to header file loongarch_extioi_common
1
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
2
to file loongarch_extioi_common.h.
1
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
include/hw/intc/loongarch_extioi.h | 26 ----------------------
8
include/hw/intc/loongarch_extioi_common.h | 27 +++++++++++++++++++++++
9
2 files changed, 27 insertions(+), 26 deletions(-)
10
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/intc/loongarch_extioi.h
14
+++ b/include/hw/intc/loongarch_extioi.h
15
@@ -XXX,XX +XXX,XX @@
16
17
#include "hw/intc/loongarch_extioi_common.h"
18
19
-typedef struct ExtIOICore {
20
- uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
21
- DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
22
- qemu_irq parent_irq[LS3A_INTC_IP];
23
-} ExtIOICore;
24
-
25
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
26
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
27
-struct LoongArchExtIOI {
28
- SysBusDevice parent_obj;
29
- uint32_t num_cpu;
30
- uint32_t features;
31
- uint32_t status;
32
- /* hardware state */
33
- uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
34
- uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
35
- uint32_t isr[EXTIOI_IRQS / 32];
36
- uint32_t enable[EXTIOI_IRQS / 32];
37
- uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
38
- uint32_t coremap[EXTIOI_IRQS / 4];
39
- uint32_t sw_pending[EXTIOI_IRQS / 32];
40
- uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
41
- uint8_t sw_coremap[EXTIOI_IRQS];
42
- qemu_irq irq[EXTIOI_IRQS];
43
- ExtIOICore *cpu;
44
- MemoryRegion extioi_system_mem;
45
- MemoryRegion virt_extend;
46
-};
47
#endif /* LOONGARCH_EXTIOI_H */
48
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_extioi_common.h
51
+++ b/include/hw/intc/loongarch_extioi_common.h
52
@@ -XXX,XX +XXX,XX @@
53
#define EXTIOI_ENABLE_CPU_ENCODE (3)
54
#define EXTIOI_VIRT_COREMAP_START (0x40)
55
#define EXTIOI_VIRT_COREMAP_END (0x240)
56
+
57
+typedef struct ExtIOICore {
58
+ uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
59
+ DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
60
+ qemu_irq parent_irq[LS3A_INTC_IP];
61
+} ExtIOICore;
62
+
63
+struct LoongArchExtIOI {
64
+ SysBusDevice parent_obj;
65
+ uint32_t num_cpu;
66
+ uint32_t features;
67
+ uint32_t status;
68
+ /* hardware state */
69
+ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
70
+ uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
71
+ uint32_t isr[EXTIOI_IRQS / 32];
72
+ uint32_t enable[EXTIOI_IRQS / 32];
73
+ uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
74
+ uint32_t coremap[EXTIOI_IRQS / 4];
75
+ uint32_t sw_pending[EXTIOI_IRQS / 32];
76
+ uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
77
+ uint8_t sw_coremap[EXTIOI_IRQS];
78
+ qemu_irq irq[EXTIOI_IRQS];
79
+ ExtIOICore *cpu;
80
+ MemoryRegion extioi_system_mem;
81
+ MemoryRegion virt_extend;
82
+};
83
#endif /* LOONGARCH_EXTIOI_H */
84
--
85
2.43.5
diff view generated by jsdifflib
New patch
[PULL 11/18] include: Rename LoongArchExtIOI with LoongArchExtIOICommonState
1
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
2
since it is defined in file loongarch_extioi_common.h
1
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
include/hw/intc/loongarch_extioi.h | 1 +
8
include/hw/intc/loongarch_extioi_common.h | 2 +-
9
2 files changed, 2 insertions(+), 1 deletion(-)
10
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/intc/loongarch_extioi.h
14
+++ b/include/hw/intc/loongarch_extioi.h
15
@@ -XXX,XX +XXX,XX @@
16
17
#include "hw/intc/loongarch_extioi_common.h"
18
19
+#define LoongArchExtIOI LoongArchExtIOICommonState
20
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
21
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
22
#endif /* LOONGARCH_EXTIOI_H */
23
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/intc/loongarch_extioi_common.h
26
+++ b/include/hw/intc/loongarch_extioi_common.h
27
@@ -XXX,XX +XXX,XX @@ typedef struct ExtIOICore {
28
qemu_irq parent_irq[LS3A_INTC_IP];
29
} ExtIOICore;
30
31
-struct LoongArchExtIOI {
32
+struct LoongArchExtIOICommonState {
33
SysBusDevice parent_obj;
34
uint32_t num_cpu;
35
uint32_t features;
36
--
37
2.43.5
diff view generated by jsdifflib
[PULL 2/5] hw/intc: Set physical cpuid route for LoongArch ipi device
[PULL 12/18] hw/intc/loongarch_extioi: Rename LoongArchExtIOI with LoongArchExtIOICommonState
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
With some structure such as vmstate and property, rename LoongArchExtIOI
2
with LoongArchExtIOICommonState, these common structure will be moved
3
to common file.
2
4
3
LoongArch ipi device uses physical cpuid to route to different
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
vcpus rather logical cpuid, and the physical cpuid is the same
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
with cpuid in acpi dsdt and srat table.
7
---
8
hw/intc/loongarch_extioi.c | 41 +++++++++++++++++++++++---------------
9
1 file changed, 25 insertions(+), 16 deletions(-)
6
10
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
11
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
8
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn>
11
---
12
hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++++-------
13
hw/loongarch/virt.c | 1 +
14
target/loongarch/cpu.h | 2 ++
15
3 files changed, 40 insertions(+), 7 deletions(-)
16
17
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/loongarch_ipi.c
13
--- a/hw/intc/loongarch_extioi.c
20
+++ b/hw/intc/loongarch_ipi.c
14
+++ b/hw/intc/loongarch_extioi.c
21
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static int vmstate_extioi_post_load(void *opaque, int version_id)
22
#include "target/loongarch/internals.h"
16
return 0;
23
#include "trace.h"
24
25
+static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned);
26
+
27
static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
28
{
29
IPICore *s = opaque;
30
@@ -XXX,XX +XXX,XX @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
31
data, MEMTXATTRS_UNSPECIFIED, NULL);
32
}
17
}
33
18
34
+static int archid_cmp(const void *a, const void *b)
19
+static int loongarch_extioi_common_post_load(void *opaque, int version_id)
35
+{
20
+{
36
+ CPUArchId *archid_a = (CPUArchId *)a;
21
+ return vmstate_extioi_post_load(opaque, version_id);
37
+ CPUArchId *archid_b = (CPUArchId *)b;
38
+
39
+ return archid_a->arch_id - archid_b->arch_id;
40
+}
22
+}
41
+
23
+
42
+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
24
static const VMStateDescription vmstate_extioi_core = {
43
+{
25
.name = "extioi-core",
44
+ CPUArchId apic_id, *found_cpu;
26
.version_id = 1,
45
+
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
46
+ apic_id.arch_id = id;
28
};
47
+ found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
29
48
+ ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
30
static const VMStateDescription vmstate_loongarch_extioi = {
49
+ archid_cmp);
31
- .name = TYPE_LOONGARCH_EXTIOI,
50
+
32
+ .name = "loongarch.extioi",
51
+ return found_cpu;
33
.version_id = 3,
52
+}
34
.minimum_version_id = 3,
53
+
35
- .post_load = vmstate_extioi_post_load,
54
+static CPUState *ipi_getcpu(int arch_id)
36
+ .post_load = loongarch_extioi_common_post_load,
55
+{
37
.fields = (const VMStateField[]) {
56
+ MachineState *machine = MACHINE(qdev_get_machine());
38
- VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
57
+ CPUArchId *archid;
39
- VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
58
+
40
+ VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
59
+ archid = find_cpu_by_archid(machine, arch_id);
41
+ EXTIOI_IRQS_GROUP_COUNT),
60
+ return CPU(archid->cpu);
42
+ VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
61
+}
43
EXTIOI_IRQS_NODETYPE_COUNT / 2),
62
+
44
- VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
63
static void ipi_send(uint64_t val)
45
- VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
64
{
46
- VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
65
uint32_t cpuid;
47
- VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
66
uint8_t vector;
48
-
67
- CPULoongArchState *env;
49
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
68
CPUState *cs;
50
- vmstate_extioi_core, ExtIOICore),
69
LoongArchCPU *cpu;
51
- VMSTATE_UINT32(features, LoongArchExtIOI),
70
+ LoongArchIPI *s;
52
- VMSTATE_UINT32(status, LoongArchExtIOI),
71
53
+ VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
72
cpuid = extract32(val, 16, 10);
54
+ EXTIOI_IRQS / 32),
73
if (cpuid >= LOONGARCH_MAX_CPUS) {
55
+ VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
74
@@ -XXX,XX +XXX,XX @@ static void ipi_send(uint64_t val)
56
+ EXTIOI_IRQS / 32),
75
/* IPI status vector */
57
+ VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
76
vector = extract8(val, 0, 5);
58
+ EXTIOI_IRQS_IPMAP_SIZE / 4),
77
59
+ VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
78
- cs = qemu_get_cpu(cpuid);
60
+ EXTIOI_IRQS / 4),
79
+ cs = ipi_getcpu(cpuid);
61
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
80
cpu = LOONGARCH_CPU(cs);
62
+ num_cpu, vmstate_extioi_core, ExtIOICore),
81
- env = &cpu->env;
63
+ VMSTATE_UINT32(features, LoongArchExtIOICommonState),
82
- address_space_stl(&env->address_space_iocsr, 0x1008,
64
+ VMSTATE_UINT32(status, LoongArchExtIOICommonState),
83
- BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);
65
VMSTATE_END_OF_LIST()
84
+ s = LOONGARCH_IPI(cpu->env.ipistate);
85
+ loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4);
86
}
87
88
static void mail_send(uint64_t val)
89
@@ -XXX,XX +XXX,XX @@ static void mail_send(uint64_t val)
90
}
66
}
91
67
};
92
addr = 0x1020 + (val & 0x1c);
68
93
- cs = qemu_get_cpu(cpuid);
69
static Property extioi_properties[] = {
94
+ cs = ipi_getcpu(cpuid);
70
- DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
95
cpu = LOONGARCH_CPU(cs);
71
- DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
96
env = &cpu->env;
72
- EXTIOI_HAS_VIRT_EXTENSION, 0),
97
send_ipi_data(env, val, addr);
73
+ DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
98
@@ -XXX,XX +XXX,XX @@ static void any_send(uint64_t val)
74
+ DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
99
}
75
+ features, EXTIOI_HAS_VIRT_EXTENSION, 0),
100
76
DEFINE_PROP_END_OF_LIST(),
101
addr = val & 0xffff;
77
};
102
- cs = qemu_get_cpu(cpuid);
103
+ cs = ipi_getcpu(cpuid);
104
cpu = LOONGARCH_CPU(cs);
105
env = &cpu->env;
106
send_ipi_data(env, val, addr);
107
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/loongarch/virt.c
110
+++ b/hw/loongarch/virt.c
111
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
112
memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
113
sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
114
cpu));
115
+ env->ipistate = ipi;
116
}
117
118
/*
119
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/loongarch/cpu.h
122
+++ b/target/loongarch/cpu.h
123
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
124
MemoryRegion iocsr_mem;
125
bool load_elf;
126
uint64_t elf_address;
127
+ /* Store ipistate to access from this struct */
128
+ DeviceState *ipistate;
129
#endif
130
} CPULoongArchState;
131
78
132
--
79
--
133
2.39.1
80
2.43.5
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.