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[PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model

Tao Su posted 7 patches 2 years, 7 months ago
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Marcelo Tosatti <mtosatti@redhat.com>
[PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model
Posted by Tao Su 2 years, 7 months ago 
From: Lei Wang <lei4.wang@intel.com>

Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
fixes.

Add version 2 of SapphireRapids CPU model with those bits enabled also.

Signed-off-by: Lei Wang <lei4.wang@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 target/i386/cpu.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b5321240c6..f84fd20bb1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "Intel Xeon Processor (SapphireRapids)",
         .versions = (X86CPUVersionDefinition[]) {
             { .version = 1 },
-            { /* end of list */ },
-        },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "sbdr-ssdp-no", "on" },
+                    { "fbsdp-no", "on" },
+                    { "psdp-no", "on" },
+                    { /* end of list */ }
+                }
+            },
+            { /* end of list */ }
+        }
     },
     {
         .name = "Denverton",
-- 
2.34.1
Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model
Posted by Igor Mammedov 2 years, 7 months ago 
On Fri, 16 Jun 2023 11:23:09 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> From: Lei Wang <lei4.wang@intel.com>
> 
> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> fixes.
> 
> Add version 2 of SapphireRapids CPU model with those bits enabled also.

don't we need to update stepping value to 8 as well?

> 
> Signed-off-by: Lei Wang <lei4.wang@intel.com>
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> ---
>  target/i386/cpu.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index b5321240c6..f84fd20bb1 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>          .model_id = "Intel Xeon Processor (SapphireRapids)",
>          .versions = (X86CPUVersionDefinition[]) {
>              { .version = 1 },
> -            { /* end of list */ },
> -        },
> +            {
> +                .version = 2,
> +                .props = (PropValue[]) {
> +                    { "sbdr-ssdp-no", "on" },
> +                    { "fbsdp-no", "on" },
> +                    { "psdp-no", "on" },
> +                    { /* end of list */ }
> +                }
> +            },
> +            { /* end of list */ }
> +        }
>      },
>      {
>          .name = "Denverton",
Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model
Posted by Xiaoyao Li 2 years, 7 months ago 
On 6/26/2023 9:15 PM, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:09 +0800
> Tao Su <tao1.su@linux.intel.com> wrote:
> 
>> From: Lei Wang <lei4.wang@intel.com>
>>
>> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
>> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
>> fixes.
>>
>> Add version 2 of SapphireRapids CPU model with those bits enabled also.
> 
> don't we need to update stepping value to 8 as well?

No need.

The commit message is misleading. There 3 bits and some other bits in 
MSR_IA32_ARCH_CAPABILITIES are not tied to CPU stepping. Instead, they 
are enumerated with newer microcode.

>>
>> Signed-off-by: Lei Wang <lei4.wang@intel.com>
>> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
>> ---
>>   target/i386/cpu.c | 13 +++++++++++--
>>   1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index b5321240c6..f84fd20bb1 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>>           .model_id = "Intel Xeon Processor (SapphireRapids)",
>>           .versions = (X86CPUVersionDefinition[]) {
>>               { .version = 1 },
>> -            { /* end of list */ },
>> -        },
>> +            {
>> +                .version = 2,
>> +                .props = (PropValue[]) {
>> +                    { "sbdr-ssdp-no", "on" },
>> +                    { "fbsdp-no", "on" },
>> +                    { "psdp-no", "on" },
>> +                    { /* end of list */ }
>> +                }
>> +            },
>> +            { /* end of list */ }
>> +        }
>>       },
>>       {
>>           .name = "Denverton",
>
Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model
Posted by Igor Mammedov 2 years, 7 months ago 
On Tue, 27 Jun 2023 14:10:17 +0800
Xiaoyao Li <xiaoyao.li@intel.com> wrote:

> On 6/26/2023 9:15 PM, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:09 +0800
> > Tao Su <tao1.su@linux.intel.com> wrote:
> >   
> >> From: Lei Wang <lei4.wang@intel.com>
> >>
> >> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> >> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> >> fixes.
> >>
> >> Add version 2 of SapphireRapids CPU model with those bits enabled also.  
> > 
> > don't we need to update stepping value to 8 as well?  
> 
> No need.
> 
> The commit message is misleading. There 3 bits and some other bits in 
> MSR_IA32_ARCH_CAPABILITIES are not tied to CPU stepping. Instead, they 
> are enumerated with newer microcode.

It that case fix commit message please.

> 
> >>
> >> Signed-off-by: Lei Wang <lei4.wang@intel.com>
> >> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> >> ---
> >>   target/i386/cpu.c | 13 +++++++++++--
> >>   1 file changed, 11 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index b5321240c6..f84fd20bb1 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> >>           .model_id = "Intel Xeon Processor (SapphireRapids)",
> >>           .versions = (X86CPUVersionDefinition[]) {
> >>               { .version = 1 },
> >> -            { /* end of list */ },
> >> -        },
> >> +            {
> >> +                .version = 2,
> >> +                .props = (PropValue[]) {
> >> +                    { "sbdr-ssdp-no", "on" },
> >> +                    { "fbsdp-no", "on" },
> >> +                    { "psdp-no", "on" },
> >> +                    { /* end of list */ }
> >> +                }
> >> +            },
> >> +            { /* end of list */ }
> >> +        }
> >>       },
> >>       {
> >>           .name = "Denverton",  
> >   
>

Patchew 2.1-devel-b67e4c2

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