[PULL 0/1] loongarch-to-apply queue
[PULL 0/5] loongarch-to-apply queue
1
The following changes since commit 848a6caa88b9f082c89c9b41afa975761262981d:
1
The following changes since commit 8844bb8d896595ee1d25d21c770e6e6f29803097:
2
2
3
Merge tag 'migration-20230602-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-06-02 17:33:29 -0700)
3
Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu into staging (2023-05-13 11:23:14 +0100)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230605
7
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230515
8
8
9
for you to fetch changes up to 8555ddc671203969b0e6eb651e538d02a9a79b3a:
9
for you to fetch changes up to 7ef0eb35a4e6961d7e40f03f16ed241c95ae93f9:
10
10
11
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes (2023-06-05 11:08:55 +0800)
11
hw/intc: Add NULL pointer check on LoongArch ipi device (2023-05-15 19:09:33 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Fixes Coverity CID: 1512452, 1512453
14
pull-loongarch-20230515
15
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
16
15
17
----------------------------------------------------------------
16
----------------------------------------------------------------
18
Jiaxun Yang (1):
17
Alexander Bulekov (1):
19
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
18
loongarch: mark loongarch_ipi_iocsr re-entrnacy safe
20
19
21
hw/intc/loongarch_ipi.c | 6 +++---
20
Song Gao (4):
22
include/hw/intc/loongarch_ipi.h | 4 +++-
21
tests/avocado: Add LoongArch machine start test
23
2 files changed, 6 insertions(+), 4 deletions(-)
22
hw/loongarch/virt: Modify ipi as percpu device
23
hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine
24
hw/intc: Add NULL pointer check on LoongArch ipi device
25
26
MAINTAINERS | 1 +
27
hw/intc/loongarch_extioi.c | 4 +-
28
hw/intc/loongarch_ipi.c | 86 +++++++++++++++++++++-----------------
29
hw/intc/trace-events | 1 +
30
hw/loongarch/virt.c | 25 ++++++-----
31
include/hw/intc/loongarch_extioi.h | 10 +++--
32
include/hw/intc/loongarch_ipi.h | 10 ++---
33
include/hw/loongarch/virt.h | 3 +-
34
tests/avocado/machine_loongarch.py | 58 +++++++++++++++++++++++++
35
9 files changed, 136 insertions(+), 62 deletions(-)
36
create mode 100644 tests/avocado/machine_loongarch.py
diff view generated by jsdifflib
New patch
[PULL 1/5] loongarch: mark loongarch_ipi_iocsr re-entrnacy safe
1
From: Alexander Bulekov <alxndr@bu.edu>
1
2
3
loongarch_ipi_iocsr MRs rely on re-entrant IO through the ipi_send
4
function. As such, mark these MRs re-entrancy-safe.
5
6
Fixes: a2e1753b80 ("memory: prevent dma-reentracy issues")
7
Signed-off-by: Alexander Bulekov <alxndr@bu.edu>
8
Reviewed-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20230506112145.3563708-1-alxndr@bu.edu>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
12
hw/intc/loongarch_ipi.c | 4 ++++
13
1 file changed, 4 insertions(+)
14
15
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/loongarch_ipi.c
18
+++ b/hw/intc/loongarch_ipi.c
19
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
20
for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
21
memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
22
&lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
23
+
24
+ /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
25
+ s->ipi_iocsr_mem[cpu].disable_reentrancy_guard = true;
26
+
27
sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
28
29
memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
30
--
31
2.39.1
diff view generated by jsdifflib
New patch
[PULL 2/5] tests/avocado: Add LoongArch machine start test
1
Add a new test in tests/avocado to check LoongArch virt machine start.
1
2
3
Reviewed-by: Thomas Huth <thuth@redhat.com>
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Reviewed-by: Cédric Le Goater <clg@redhat.com>
6
Message-Id: <20230513012744.1885728-1-gaosong@loongson.cn>
7
---
8
MAINTAINERS | 1 +
9
tests/avocado/machine_loongarch.py | 58 ++++++++++++++++++++++++++++++
10
2 files changed, 59 insertions(+)
11
create mode 100644 tests/avocado/machine_loongarch.py
12
13
diff --git a/MAINTAINERS b/MAINTAINERS
14
index XXXXXXX..XXXXXXX 100644
15
--- a/MAINTAINERS
16
+++ b/MAINTAINERS
17
@@ -XXX,XX +XXX,XX @@ M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
18
S: Maintained
19
F: target/loongarch/
20
F: tests/tcg/loongarch64/
21
+F: tests/avocado/machine_loongarch.py
22
23
M68K TCG CPUs
24
M: Laurent Vivier <laurent@vivier.eu>
25
diff --git a/tests/avocado/machine_loongarch.py b/tests/avocado/machine_loongarch.py
26
new file mode 100644
27
index XXXXXXX..XXXXXXX
28
--- /dev/null
29
+++ b/tests/avocado/machine_loongarch.py
30
@@ -XXX,XX +XXX,XX @@
31
+# SPDX-License-Identifier: GPL-2.0-or-later
32
+#
33
+# LoongArch virt test.
34
+#
35
+# Copyright (c) 2023 Loongson Technology Corporation Limited
36
+#
37
+
38
+from avocado_qemu import QemuSystemTest
39
+from avocado_qemu import exec_command_and_wait_for_pattern
40
+from avocado_qemu import wait_for_console_pattern
41
+
42
+class LoongArchMachine(QemuSystemTest):
43
+ KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
44
+
45
+ timeout = 120
46
+
47
+ def wait_for_console_pattern(self, success_message, vm=None):
48
+ wait_for_console_pattern(self, success_message,
49
+ failure_message='Kernel panic - not syncing',
50
+ vm=vm)
51
+
52
+ def test_loongarch64_devices(self):
53
+
54
+ """
55
+ :avocado: tags=arch:loongarch64
56
+ :avocado: tags=machine:virt
57
+ """
58
+
59
+ kernel_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
60
+ 'releases/download/binary-files/vmlinuz.efi')
61
+ kernel_hash = '951b485b16e3788b6db03a3e1793c067009e31a2'
62
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
63
+
64
+ initrd_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
65
+ 'releases/download/binary-files/ramdisk')
66
+ initrd_hash = 'c67658d9b2a447ce7db2f73ba3d373c9b2b90ab2'
67
+ initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
68
+
69
+ bios_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
70
+ 'releases/download/binary-files/QEMU_EFI.fd')
71
+ bios_hash = ('dfc1bfba4853cd763b9d392d0031827e8addbca8')
72
+ bios_path = self.fetch_asset(bios_url, asset_hash=bios_hash)
73
+
74
+ self.vm.set_console()
75
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
76
+ 'root=/dev/ram rdinit=/sbin/init console=ttyS0,115200')
77
+ self.vm.add_args('-nographic',
78
+ '-smp', '4',
79
+ '-m', '1024',
80
+ '-cpu', 'la464',
81
+ '-kernel', kernel_path,
82
+ '-initrd', initrd_path,
83
+ '-bios', bios_path,
84
+ '-append', kernel_command_line)
85
+ self.vm.launch()
86
+ self.wait_for_console_pattern('Run /sbin/init as init process')
87
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
88
+ 'processor        : 3')
89
--
90
2.39.1
91
92
diff view generated by jsdifflib
[PULL 1/1] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
[PULL 3/5] hw/loongarch/virt: Modify ipi as percpu device
1
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
1
ipi is used to communicate between cpus, this patch modified
2
loongarch ipi device as percpu device, so that there are
3
2 MemoryRegions with ipi device, rather than 2*cpus
4
MemoryRegions, which may be large than QDEV_MAX_MMIO if
5
more cpus are added on loongarch virt machine.
2
6
3
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Loongson 3A5000's IPI implementation have 4 mailboxes per
5
core.
6
7
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
8
percpu device"), the number of IPI mailboxes was reduced to
9
one, which mismatches actual hardware.
10
11
It won't affect LoongArch based system as LoongArch boot code
12
only uses the first mailbox, however MIPS based Loongson boot
13
code uses all 4 mailboxes.
14
15
Fixes Coverity CID: 1512452, 1512453
16
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
17
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
18
Reviewed-by: Song Gao <gaosong@loongson.cn>
19
Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com>
20
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20230512100421.1867848-2-gaosong@loongson.cn>
21
---
10
---
22
hw/intc/loongarch_ipi.c | 6 +++---
11
hw/intc/loongarch_ipi.c | 44 ++++++++++++---------------------
23
include/hw/intc/loongarch_ipi.h | 4 +++-
12
hw/loongarch/virt.c | 12 ++++-----
24
2 files changed, 6 insertions(+), 4 deletions(-)
13
include/hw/intc/loongarch_ipi.h | 10 +++-----
14
include/hw/loongarch/virt.h | 1 -
15
4 files changed, 26 insertions(+), 41 deletions(-)
25
16
26
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
17
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
27
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/intc/loongarch_ipi.c
19
--- a/hw/intc/loongarch_ipi.c
29
+++ b/hw/intc/loongarch_ipi.c
20
+++ b/hw/intc/loongarch_ipi.c
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
21
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_ipi64_ops = {
22
23
static void loongarch_ipi_init(Object *obj)
24
{
25
- int cpu;
26
- LoongArchMachineState *lams;
27
LoongArchIPI *s = LOONGARCH_IPI(obj);
28
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
29
- Object *machine = qdev_get_machine();
30
- ObjectClass *mc = object_get_class(machine);
31
- /* 'lams' should be initialized */
32
- if (!strcmp(MACHINE_CLASS(mc)->name, "none")) {
33
- return;
34
- }
35
- lams = LOONGARCH_MACHINE(machine);
36
- for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
37
- memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
38
- &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
39
40
- /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
41
- s->ipi_iocsr_mem[cpu].disable_reentrancy_guard = true;
42
+ memory_region_init_io(&s->ipi_iocsr_mem, obj, &loongarch_ipi_ops,
43
+ &s->ipi_core, "loongarch_ipi_iocsr", 0x48);
44
45
- sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
46
+ /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
47
+ s->ipi_iocsr_mem.disable_reentrancy_guard = true;
48
49
- memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
50
- &lams->ipi_core[cpu], "loongarch_ipi64_iocsr", 0x118);
51
- sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem[cpu]);
52
- qdev_init_gpio_out(DEVICE(obj), &lams->ipi_core[cpu].irq, 1);
53
- }
54
+ sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
55
+
56
+ memory_region_init_io(&s->ipi64_iocsr_mem, obj, &loongarch_ipi64_ops,
57
+ &s->ipi_core, "loongarch_ipi64_iocsr", 0x118);
58
+ sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
59
+ qdev_init_gpio_out(DEVICE(obj), &s->ipi_core.irq, 1);
60
}
31
61
32
static const VMStateDescription vmstate_ipi_core = {
62
static const VMStateDescription vmstate_ipi_core = {
33
.name = "ipi-single",
63
.name = "ipi-single",
34
- .version_id = 1,
64
- .version_id = 0,
35
- .minimum_version_id = 1,
65
- .minimum_version_id = 0,
36
+ .version_id = 2,
66
+ .version_id = 1,
37
+ .minimum_version_id = 2,
67
+ .minimum_version_id = 1,
38
.fields = (VMStateField[]) {
68
.fields = (VMStateField[]) {
39
VMSTATE_UINT32(status, IPICore),
69
VMSTATE_UINT32(status, IPICore),
40
VMSTATE_UINT32(en, IPICore),
70
VMSTATE_UINT32(en, IPICore),
41
VMSTATE_UINT32(set, IPICore),
71
VMSTATE_UINT32(set, IPICore),
42
VMSTATE_UINT32(clear, IPICore),
72
VMSTATE_UINT32(clear, IPICore),
43
- VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
73
- VMSTATE_UINT32_ARRAY(buf, IPICore, MAX_IPI_MBX_NUM * 2),
44
+ VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
74
+ VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
45
VMSTATE_END_OF_LIST()
75
VMSTATE_END_OF_LIST()
46
}
76
}
47
};
77
};
78
79
static const VMStateDescription vmstate_loongarch_ipi = {
80
.name = TYPE_LOONGARCH_IPI,
81
- .version_id = 0,
82
- .minimum_version_id = 0,
83
+ .version_id = 1,
84
+ .minimum_version_id = 1,
85
.fields = (VMStateField[]) {
86
- VMSTATE_STRUCT_ARRAY(ipi_core, LoongArchMachineState,
87
- MAX_IPI_CORE_NUM, 0,
88
- vmstate_ipi_core, IPICore),
89
+ VMSTATE_STRUCT(ipi_core, LoongArchIPI, 0, vmstate_ipi_core, IPICore),
90
VMSTATE_END_OF_LIST()
91
}
92
};
93
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/hw/loongarch/virt.c
96
+++ b/hw/loongarch/virt.c
97
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
98
CPUState *cpu_state;
99
int cpu, pin, i, start, num;
100
101
- ipi = qdev_new(TYPE_LOONGARCH_IPI);
102
- sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
103
-
104
extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
105
sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
106
107
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
108
lacpu = LOONGARCH_CPU(cpu_state);
109
env = &(lacpu->env);
110
111
+ ipi = qdev_new(TYPE_LOONGARCH_IPI);
112
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
113
+
114
/* connect ipi irq to cpu irq */
115
- qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
116
+ qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI));
117
/* IPI iocsr memory region */
118
memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
119
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
120
- cpu * 2));
121
+ 0));
122
memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
123
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
124
- cpu * 2 + 1));
125
+ 1));
126
/* extioi iocsr memory region */
127
memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
128
sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
48
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
129
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
49
index XXXXXXX..XXXXXXX 100644
130
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_ipi.h
131
--- a/include/hw/intc/loongarch_ipi.h
51
+++ b/include/hw/intc/loongarch_ipi.h
132
+++ b/include/hw/intc/loongarch_ipi.h
52
@@ -XXX,XX +XXX,XX @@
133
@@ -XXX,XX +XXX,XX @@
53
#define MAIL_SEND_OFFSET 0
134
#define MAIL_SEND_OFFSET 0
54
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
135
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
55
136
56
+#define IPI_MBX_NUM 4
137
-#define MAX_IPI_CORE_NUM 4
57
+
138
-#define MAX_IPI_MBX_NUM 4
139
-
58
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
140
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
59
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
141
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
60
142
61
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
143
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
62
uint32_t set;
144
uint32_t set;
63
uint32_t clear;
145
uint32_t clear;
64
/* 64bit buf divide into 2 32bit buf */
146
/* 64bit buf divide into 2 32bit buf */
65
- uint32_t buf[2];
147
- uint32_t buf[MAX_IPI_MBX_NUM * 2];
66
+ uint32_t buf[IPI_MBX_NUM * 2];
148
+ uint32_t buf[2];
67
qemu_irq irq;
149
qemu_irq irq;
68
} IPICore;
150
} IPICore;
69
151
152
struct LoongArchIPI {
153
SysBusDevice parent_obj;
154
- MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM];
155
- MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM];
156
+ MemoryRegion ipi_iocsr_mem;
157
+ MemoryRegion ipi64_iocsr_mem;
158
+ IPICore ipi_core;
159
};
160
161
#endif
162
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
163
index XXXXXXX..XXXXXXX 100644
164
--- a/include/hw/loongarch/virt.h
165
+++ b/include/hw/loongarch/virt.h
166
@@ -XXX,XX +XXX,XX @@ struct LoongArchMachineState {
167
/*< private >*/
168
MachineState parent_obj;
169
170
- IPICore ipi_core[MAX_IPI_CORE_NUM];
171
MemoryRegion lowmem;
172
MemoryRegion highmem;
173
MemoryRegion isa_io;
70
--
174
--
71
2.39.1
175
2.39.1
176
177
diff view generated by jsdifflib
New patch
[PULL 4/5] hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine
1
Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi
2
only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that
3
loongarch virt machine supports more cpus.
1
4
5
Interrupts from external devices can only be routed cpu 0-3 because
6
of extioi limits, cpu internal interrupt such as timer/ipi can be
7
triggered on all cpus.
8
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Song Gao <gaosong@loongson.cn>
12
Message-Id: <20230512100421.1867848-3-gaosong@loongson.cn>
13
---
14
hw/intc/loongarch_extioi.c | 4 ++--
15
hw/loongarch/virt.c | 13 +++++++++----
16
include/hw/intc/loongarch_extioi.h | 10 ++++++----
17
include/hw/loongarch/virt.h | 2 +-
18
4 files changed, 18 insertions(+), 11 deletions(-)
19
20
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/loongarch_extioi.c
23
+++ b/hw/intc/loongarch_extioi.c
24
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_extioi = {
25
.minimum_version_id = 1,
26
.fields = (VMStateField[]) {
27
VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
28
- VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, LOONGARCH_MAX_VCPUS,
29
+ VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, EXTIOI_CPUS,
30
EXTIOI_IRQS_GROUP_COUNT),
31
VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
32
EXTIOI_IRQS_NODETYPE_COUNT / 2),
33
@@ -XXX,XX +XXX,XX @@ static void loongarch_extioi_instance_init(Object *obj)
34
35
qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
36
37
- for (cpu = 0; cpu < LOONGARCH_MAX_VCPUS; cpu++) {
38
+ for (cpu = 0; cpu < EXTIOI_CPUS; cpu++) {
39
memory_region_init_io(&s->extioi_iocsr_mem[cpu], OBJECT(s), &extioi_ops,
40
s, "extioi_iocsr", 0x900);
41
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_iocsr_mem[cpu]);
42
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/loongarch/virt.c
45
+++ b/hw/loongarch/virt.c
46
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
47
memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
48
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
49
1));
50
- /* extioi iocsr memory region */
51
- memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
52
+ /*
53
+     * extioi iocsr memory region
54
+     * only one extioi is added on loongarch virt machine
55
+     * external device interrupt can only be routed to cpu 0-3
56
+     */
57
+    if (cpu < EXTIOI_CPUS)
58
+ memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
59
sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
60
cpu));
61
}
62
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
63
* connect ext irq to the cpu irq
64
* cpu_pin[9:2] <= intc_pin[7:0]
65
*/
66
- for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
67
+ for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) {
68
cpudev = DEVICE(qemu_get_cpu(cpu));
69
for (pin = 0; pin < LS3A_INTC_IP; pin++) {
70
qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
71
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
72
mc->default_ram_size = 1 * GiB;
73
mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
74
mc->default_ram_id = "loongarch.ram";
75
- mc->max_cpus = LOONGARCH_MAX_VCPUS;
76
+ mc->max_cpus = LOONGARCH_MAX_CPUS;
77
mc->is_default = 1;
78
mc->default_kernel_irqchip_split = false;
79
mc->block_default_type = IF_VIRTIO;
80
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
81
index XXXXXXX..XXXXXXX 100644
82
--- a/include/hw/intc/loongarch_extioi.h
83
+++ b/include/hw/intc/loongarch_extioi.h
84
@@ -XXX,XX +XXX,XX @@
85
#define LS3A_INTC_IP 8
86
#define EXTIOI_IRQS (256)
87
#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
88
+/* irq from EXTIOI is routed to no more than 4 cpus */
89
+#define EXTIOI_CPUS (4)
90
/* map to ipnum per 32 irqs */
91
#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
92
#define EXTIOI_IRQS_COREMAP_SIZE 256
93
@@ -XXX,XX +XXX,XX @@ struct LoongArchExtIOI {
94
uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
95
uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
96
uint32_t isr[EXTIOI_IRQS / 32];
97
- uint32_t coreisr[LOONGARCH_MAX_VCPUS][EXTIOI_IRQS_GROUP_COUNT];
98
+ uint32_t coreisr[EXTIOI_CPUS][EXTIOI_IRQS_GROUP_COUNT];
99
uint32_t enable[EXTIOI_IRQS / 32];
100
uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
101
uint32_t coremap[EXTIOI_IRQS / 4];
102
uint32_t sw_pending[EXTIOI_IRQS / 32];
103
- DECLARE_BITMAP(sw_isr[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP], EXTIOI_IRQS);
104
+ DECLARE_BITMAP(sw_isr[EXTIOI_CPUS][LS3A_INTC_IP], EXTIOI_IRQS);
105
uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
106
uint8_t sw_coremap[EXTIOI_IRQS];
107
- qemu_irq parent_irq[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP];
108
+ qemu_irq parent_irq[EXTIOI_CPUS][LS3A_INTC_IP];
109
qemu_irq irq[EXTIOI_IRQS];
110
- MemoryRegion extioi_iocsr_mem[LOONGARCH_MAX_VCPUS];
111
+ MemoryRegion extioi_iocsr_mem[EXTIOI_CPUS];
112
MemoryRegion extioi_system_mem;
113
};
114
#endif /* LOONGARCH_EXTIOI_H */
115
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
116
index XXXXXXX..XXXXXXX 100644
117
--- a/include/hw/loongarch/virt.h
118
+++ b/include/hw/loongarch/virt.h
119
@@ -XXX,XX +XXX,XX @@
120
#include "hw/intc/loongarch_ipi.h"
121
#include "hw/block/flash.h"
122
123
-#define LOONGARCH_MAX_VCPUS 4
124
+#define LOONGARCH_MAX_CPUS 256
125
126
#define VIRT_ISA_IO_BASE 0x18000000UL
127
#define VIRT_ISA_IO_SIZE 0x0004000
128
--
129
2.39.1
130
131
diff view generated by jsdifflib
New patch
[PULL 5/5] hw/intc: Add NULL pointer check on LoongArch ipi device
1
When ipi mailbox is used, cpu_index is decoded from iocsr register.
2
cpu maybe does not exist. This patch adds NULL pointer check on
3
ipi device.
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20230512100421.1867848-4-gaosong@loongson.cn>
9
---
10
hw/intc/loongarch_ipi.c | 40 +++++++++++++++++++++++++++++-----------
11
hw/intc/trace-events | 1 +
12
2 files changed, 30 insertions(+), 11 deletions(-)
13
14
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/loongarch_ipi.c
17
+++ b/hw/intc/loongarch_ipi.c
18
@@ -XXX,XX +XXX,XX @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
19
20
static void ipi_send(uint64_t val)
21
{
22
- int cpuid, data;
23
+ uint32_t cpuid;
24
+ uint8_t vector;
25
CPULoongArchState *env;
26
CPUState *cs;
27
LoongArchCPU *cpu;
28
29
- cpuid = (val >> 16) & 0x3ff;
30
+ cpuid = extract32(val, 16, 10);
31
+ if (cpuid >= LOONGARCH_MAX_CPUS) {
32
+ trace_loongarch_ipi_unsupported_cpuid("IOCSR_IPI_SEND", cpuid);
33
+ return;
34
+ }
35
+
36
/* IPI status vector */
37
- data = 1 << (val & 0x1f);
38
+ vector = extract8(val, 0, 5);
39
+
40
cs = qemu_get_cpu(cpuid);
41
cpu = LOONGARCH_CPU(cs);
42
env = &cpu->env;
43
address_space_stl(&env->address_space_iocsr, 0x1008,
44
- data, MEMTXATTRS_UNSPECIFIED, NULL);
45
-
46
+ BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);
47
}
48
49
static void mail_send(uint64_t val)
50
{
51
- int cpuid;
52
+ uint32_t cpuid;
53
hwaddr addr;
54
CPULoongArchState *env;
55
CPUState *cs;
56
LoongArchCPU *cpu;
57
58
- cpuid = (val >> 16) & 0x3ff;
59
+ cpuid = extract32(val, 16, 10);
60
+ if (cpuid >= LOONGARCH_MAX_CPUS) {
61
+ trace_loongarch_ipi_unsupported_cpuid("IOCSR_MAIL_SEND", cpuid);
62
+ return;
63
+ }
64
+
65
addr = 0x1020 + (val & 0x1c);
66
cs = qemu_get_cpu(cpuid);
67
cpu = LOONGARCH_CPU(cs);
68
@@ -XXX,XX +XXX,XX @@ static void mail_send(uint64_t val)
69
70
static void any_send(uint64_t val)
71
{
72
- int cpuid;
73
+ uint32_t cpuid;
74
hwaddr addr;
75
CPULoongArchState *env;
76
+ CPUState *cs;
77
+ LoongArchCPU *cpu;
78
+
79
+ cpuid = extract32(val, 16, 10);
80
+ if (cpuid >= LOONGARCH_MAX_CPUS) {
81
+ trace_loongarch_ipi_unsupported_cpuid("IOCSR_ANY_SEND", cpuid);
82
+ return;
83
+ }
84
85
- cpuid = (val >> 16) & 0x3ff;
86
addr = val & 0xffff;
87
- CPUState *cs = qemu_get_cpu(cpuid);
88
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
89
+ cs = qemu_get_cpu(cpuid);
90
+ cpu = LOONGARCH_CPU(cs);
91
env = &cpu->env;
92
send_ipi_data(env, val, addr);
93
}
94
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
95
index XXXXXXX..XXXXXXX 100644
96
--- a/hw/intc/trace-events
97
+++ b/hw/intc/trace-events
98
@@ -XXX,XX +XXX,XX @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
99
# loongarch_ipi.c
100
loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
101
loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
102
+loongarch_ipi_unsupported_cpuid(const char *s, uint32_t cpuid) "%s unsupported cpuid 0x%" PRIx32
103
104
# loongarch_pch_pic.c
105
loongarch_pch_pic_irq_handler(int irq, int level) "irq %d level %d"
106
--
107
2.39.1
108
109
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.