[PULL 00/21] target-arm queue
[PULL 00/72] target-arm queue
1
Hi; here's the latest batch of arm changes. The big thing
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
in here is the SMMUv3 changes to add stage-2 translation support.
2
handling series. (Lots more in my to-review queue, but I don't
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like pullreqs growing too close to a hundred patches at a time :-))
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4
4
thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit aa9bbd865502ed517624ab6fe7d4b5d89ca95e43:
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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9
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Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into staging (2023-05-29 14:31:52 -0700)
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230530
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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for you to fetch changes up to b03d0d4f531a8b867e0aac1fab0b876903015680:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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docs: sbsa: correct graphics card name (2023-05-30 13:32:46 +0100)
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MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
21
target-arm queue:
21
* fsl-imx6: Add SNVS support for i.MX6 boards
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
22
* smmuv3: Add support for stage 2 translations
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
23
* hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
24
* hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
25
* fpu: Minor NaN-related cleanups
25
* cleanups for recent Kconfig changes
26
* MAINTAINERS: email address updates
26
* target/arm: Explicitly select short-format FSR for M-profile
27
* tests/qtest: Run arm-specific tests only if the required machine is available
28
* hw/arm/sbsa-ref: add GIC node into DT
29
* docs: sbsa: correct graphics card name
30
* Update copyright dates to 2023
31
27
32
----------------------------------------------------------------
28
----------------------------------------------------------------
33
Clément Chigot (1):
29
Bernhard Beschow (5):
34
hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
35
35
36
Enze Li (1):
36
Leif Lindholm (1):
37
Update copyright dates to 2023
37
MAINTAINERS: update email address for Leif Lindholm
38
38
39
Fabiano Rosas (3):
39
Peter Maydell (54):
40
target/arm: Explain why we need to select ARM_V7M
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
41
arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
42
arm/Kconfig: Make TCG dependence explicit
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
tests/fp: Explicitly set inf-zero-nan rule
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
43
94
44
Marcin Juszkiewicz (2):
95
Richard Henderson (11):
45
hw/arm/sbsa-ref: add GIC node into DT
96
target/arm: Copy entire float_status in is_ebf
46
docs: sbsa: correct graphics card name
97
softfloat: Inline pickNaNMulAdd
98
softfloat: Use goto for default nan case in pick_nan_muladd
99
softfloat: Remove which from parts_pick_nan_muladd
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
47
107
48
Mostafa Saleh (10):
108
Vikram Garhwal (1):
49
hw/arm/smmuv3: Add missing fields for IDR0
109
MAINTAINERS: Add correct email address for Vikram Garhwal
50
hw/arm/smmuv3: Update translation config to hold stage-2
51
hw/arm/smmuv3: Refactor stage-1 PTW
52
hw/arm/smmuv3: Add page table walk for stage-2
53
hw/arm/smmuv3: Parse STE config for stage-2
54
hw/arm/smmuv3: Make TLB lookup work for stage-2
55
hw/arm/smmuv3: Add VMID to TLB tagging
56
hw/arm/smmuv3: Add CMDs related to stage-2
57
hw/arm/smmuv3: Add stage-2 support in iova notifier
58
hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
59
110
60
Peter Maydell (1):
111
MAINTAINERS | 4 +-
61
target/arm: Explicitly select short-format FSR for M-profile
112
include/fpu/softfloat-helpers.h | 38 +++-
62
113
include/fpu/softfloat-types.h | 89 +++++++-
63
Thomas Huth (1):
114
include/hw/net/imx_fec.h | 9 +-
64
tests/qtest: Run arm-specific tests only if the required machine is available
115
include/hw/net/lan9118_phy.h | 37 ++++
65
116
include/hw/net/mii.h | 6 +
66
Tommy Wu (1):
117
target/mips/fpu_helper.h | 20 ++
67
hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
118
target/sparc/helper.h | 4 +-
68
119
fpu/softfloat.c | 19 ++
69
Vitaly Cheptsov (1):
120
hw/net/imx_fec.c | 146 ++------------
70
fsl-imx6: Add SNVS support for i.MX6 boards
121
hw/net/lan9118.c | 137 ++-----------
71
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
72
docs/conf.py | 2 +-
123
linux-user/arm/nwfpe/fpa11.c | 5 +
73
docs/system/arm/sbsa.rst | 2 +-
124
target/alpha/cpu.c | 2 +
74
configs/devices/aarch64-softmmu/default.mak | 6 +
125
target/arm/cpu.c | 10 +
75
configs/devices/arm-softmmu/default.mak | 40 ++++
126
target/arm/tcg/vec_helper.c | 20 +-
76
hw/arm/smmu-internal.h | 37 +++
127
target/hexagon/cpu.c | 2 +
77
hw/arm/smmuv3-internal.h | 12 +-
128
target/hppa/fpu_helper.c | 12 ++
78
include/hw/arm/fsl-imx6.h | 2 +
129
target/i386/tcg/fpu_helper.c | 12 ++
79
include/hw/arm/smmu-common.h | 45 +++-
130
target/loongarch/tcg/fpu_helper.c | 14 +-
80
include/hw/arm/smmuv3.h | 4 +
131
target/m68k/cpu.c | 14 +-
81
include/qemu/help-texts.h | 2 +-
132
target/m68k/fpu_helper.c | 6 +-
82
hw/arm/fsl-imx6.c | 8 +
133
target/m68k/helper.c | 6 +-
83
hw/arm/sbsa-ref.c | 19 +-
134
target/microblaze/cpu.c | 2 +
84
hw/arm/smmu-common.c | 209 ++++++++++++++--
135
target/mips/msa.c | 10 +
85
hw/arm/smmuv3.c | 357 ++++++++++++++++++++++++----
136
target/openrisc/cpu.c | 2 +
86
hw/arm/xlnx-zynqmp.c | 2 +-
137
target/ppc/cpu_init.c | 19 ++
87
hw/dma/xilinx_axidma.c | 11 +-
138
target/ppc/fpu_helper.c | 3 +-
88
target/arm/tcg/tlb_helper.c | 13 +-
139
target/riscv/cpu.c | 2 +
89
hw/arm/Kconfig | 123 ++++++----
140
target/rx/cpu.c | 2 +
90
hw/arm/trace-events | 14 +-
141
target/s390x/cpu.c | 5 +
91
target/arm/Kconfig | 3 +
142
target/sh4/cpu.c | 2 +
92
tests/qtest/meson.build | 7 +-
143
target/sparc/cpu.c | 6 +
93
21 files changed, 773 insertions(+), 145 deletions(-)
144
target/sparc/fop_helper.c | 8 +-
94
145
target/sparc/translate.c | 4 +-
146
target/tricore/helper.c | 2 +
147
target/xtensa/cpu.c | 4 +
148
target/xtensa/fpu_helper.c | 3 +-
149
tests/fp/fp-bench.c | 7 +
150
tests/fp/fp-test-log2.c | 1 +
151
tests/fp/fp-test.c | 7 +
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
154
.mailmap | 5 +-
155
hw/net/Kconfig | 5 +
156
hw/net/meson.build | 1 +
157
hw/net/trace-events | 10 +-
158
47 files changed, 778 insertions(+), 730 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
160
create mode 100644 hw/net/lan9118_phy.c
diff view generated by jsdifflib
[PULL 08/21] hw/arm/smmuv3: Add VMID to TLB tagging
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Mostafa Saleh <smostafa@google.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Allow TLB to be tagged with VMID.
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
a common implementation by extracting a device model into its own files.
4
5
5
If stage-1 is only supported, VMID is set to -1 and ignored from STE
6
Some migration state has been moved into the new device model which breaks
6
and CMD_TLBI_NH* cmds.
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
7
13
8
Update smmu_iotlb_insert trace event to have vmid.
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
9
16
10
Signed-off-by: Mostafa Saleh <smostafa@google.com>
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
12
Tested-by: Eric Auger <eric.auger@redhat.com>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
14
Message-id: 20230516203327.2051088-8-smostafa@google.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
22
---
17
hw/arm/smmu-internal.h | 2 ++
23
include/hw/net/lan9118_phy.h | 37 ++++++++
18
include/hw/arm/smmu-common.h | 5 +++--
24
hw/net/lan9118.c | 137 +++++-----------------------
19
hw/arm/smmu-common.c | 36 ++++++++++++++++++++++--------------
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
20
hw/arm/smmuv3.c | 12 +++++++++---
26
hw/net/Kconfig | 4 +
21
hw/arm/trace-events | 6 +++---
27
hw/net/meson.build | 1 +
22
5 files changed, 39 insertions(+), 22 deletions(-)
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
23
31
24
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
25
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/smmu-internal.h
77
--- a/hw/net/lan9118.c
27
+++ b/hw/arm/smmu-internal.h
78
+++ b/hw/net/lan9118.c
28
@@ -XXX,XX +XXX,XX @@ static inline int pgd_concat_idx(int start_level, int granule_sz,
79
@@ -XXX,XX +XXX,XX @@
80
#include "net/net.h"
81
#include "net/eth.h"
82
#include "hw/irq.h"
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
29
}
141
}
30
142
31
#define SMMU_IOTLB_ASID(key) ((key).asid)
143
-static void phy_update_irq(lan9118_state *s)
32
+#define SMMU_IOTLB_VMID(key) ((key).vmid)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
33
145
{
34
typedef struct SMMUIOTLBPageInvInfo {
146
- if (s->phy_int & s->phy_int_mask) {
35
int asid;
147
+ lan9118_state *s = opaque;
36
+ int vmid;
148
+
37
uint64_t iova;
149
+ if (level) {
38
uint64_t mask;
150
s->int_sts |= PHY_INT;
39
} SMMUIOTLBPageInvInfo;
151
} else {
40
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
152
s->int_sts &= ~PHY_INT;
41
index XXXXXXX..XXXXXXX 100644
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
42
--- a/include/hw/arm/smmu-common.h
154
lan9118_update(s);
43
+++ b/include/hw/arm/smmu-common.h
44
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUPciBus {
45
typedef struct SMMUIOTLBKey {
46
uint64_t iova;
47
uint16_t asid;
48
+ uint16_t vmid;
49
uint8_t tg;
50
uint8_t level;
51
} SMMUIOTLBKey;
52
@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
53
SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
54
SMMUTransTableInfo *tt, hwaddr iova);
55
void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
56
-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
57
+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
58
uint8_t tg, uint8_t level);
59
void smmu_iotlb_inv_all(SMMUState *s);
60
void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
61
-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
62
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
63
uint8_t tg, uint64_t num_pages, uint8_t ttl);
64
65
/* Unmap the range of all the notifiers registered to any IOMMU mr */
66
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/smmu-common.c
69
+++ b/hw/arm/smmu-common.c
70
@@ -XXX,XX +XXX,XX @@ static guint smmu_iotlb_key_hash(gconstpointer v)
71
72
/* Jenkins hash */
73
a = b = c = JHASH_INITVAL + sizeof(*key);
74
- a += key->asid + key->level + key->tg;
75
+ a += key->asid + key->vmid + key->level + key->tg;
76
b += extract64(key->iova, 0, 32);
77
c += extract64(key->iova, 32, 32);
78
79
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
80
SMMUIOTLBKey *k1 = (SMMUIOTLBKey *)v1, *k2 = (SMMUIOTLBKey *)v2;
81
82
return (k1->asid == k2->asid) && (k1->iova == k2->iova) &&
83
- (k1->level == k2->level) && (k1->tg == k2->tg);
84
+ (k1->level == k2->level) && (k1->tg == k2->tg) &&
85
+ (k1->vmid == k2->vmid);
86
}
155
}
87
156
88
-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
157
-static void phy_update_link(lan9118_state *s)
89
+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
158
-{
90
uint8_t tg, uint8_t level)
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
169
-}
170
-
171
static void lan9118_set_link(NetClientState *nc)
91
{
172
{
92
- SMMUIOTLBKey key = {.asid = asid, .iova = iova, .tg = tg, .level = level};
173
- phy_update_link(qemu_get_nic_opaque(nc));
93
+ SMMUIOTLBKey key = {.asid = asid, .vmid = vmid, .iova = iova,
174
-}
94
+ .tg = tg, .level = level};
175
-
95
176
-static void phy_reset(lan9118_state *s)
96
return key;
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
97
}
186
}
98
@@ -XXX,XX +XXX,XX @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
187
99
uint64_t mask = subpage_size - 1;
188
static void lan9118_reset(DeviceState *d)
100
SMMUIOTLBKey key;
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
101
190
s->read_word_n = 0;
102
- key = smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level);
191
s->write_word_n = 0;
103
+ key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid,
192
104
+ iova & ~mask, tg, level);
193
- phy_reset(s);
105
entry = g_hash_table_lookup(bs->iotlb, &key);
194
-
106
if (entry) {
195
s->eeprom_writable = 0;
107
break;
196
lan9118_reload_eeprom(s);
108
@@ -XXX,XX +XXX,XX @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
197
}
109
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
110
if (entry) {
199
uint32_t status;
111
cfg->iotlb_hits++;
200
112
- trace_smmu_iotlb_lookup_hit(cfg->asid, iova,
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
113
+ trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova,
202
- if (s->phy_control & 0x4000) {
114
cfg->iotlb_hits, cfg->iotlb_misses,
203
+ if (s->mii.control & 0x4000) {
115
100 * cfg->iotlb_hits /
204
/* This assumes the receive routine doesn't touch the VLANClient. */
116
(cfg->iotlb_hits + cfg->iotlb_misses));
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
117
} else {
206
} else {
118
cfg->iotlb_misses++;
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
119
- trace_smmu_iotlb_lookup_miss(cfg->asid, iova,
120
+ trace_smmu_iotlb_lookup_miss(cfg->asid, cfg->s2cfg.vmid, iova,
121
cfg->iotlb_hits, cfg->iotlb_misses,
122
100 * cfg->iotlb_hits /
123
(cfg->iotlb_hits + cfg->iotlb_misses));
124
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
125
smmu_iotlb_inv_all(bs);
126
}
127
128
- *key = smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level);
129
- trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level);
130
+ *key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iova,
131
+ tg, new->level);
132
+ trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova,
133
+ tg, new->level);
134
g_hash_table_insert(bs->iotlb, key, new);
135
}
136
137
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
138
139
return SMMU_IOTLB_ASID(*iotlb_key) == asid;
140
}
141
-
142
-static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
143
+static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer value,
144
gpointer user_data)
145
{
146
SMMUTLBEntry *iter = (SMMUTLBEntry *)value;
147
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
148
if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) {
149
return false;
150
}
151
+ if (info->vmid >= 0 && info->vmid != SMMU_IOTLB_VMID(iotlb_key)) {
152
+ return false;
153
+ }
154
return ((info->iova & ~entry->addr_mask) == entry->iova) ||
155
((entry->iova & ~info->mask) == info->iova);
156
}
157
158
-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
159
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
160
uint8_t tg, uint64_t num_pages, uint8_t ttl)
161
{
162
/* if tg is not set we use 4KB range invalidation */
163
uint8_t granule = tg ? tg * 2 + 10 : 12;
164
165
if (ttl && (num_pages == 1) && (asid >= 0)) {
166
- SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
167
+ SMMUIOTLBKey key = smmu_get_iotlb_key(asid, vmid, iova, tg, ttl);
168
169
if (g_hash_table_remove(s->iotlb, &key)) {
170
return;
171
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
172
173
SMMUIOTLBPageInvInfo info = {
174
.asid = asid, .iova = iova,
175
+ .vmid = vmid,
176
.mask = (num_pages * 1 << granule) - 1};
177
178
g_hash_table_foreach_remove(s->iotlb,
179
- smmu_hash_remove_by_asid_iova,
180
+ smmu_hash_remove_by_asid_vmid_iova,
181
&info);
182
}
183
184
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/hw/arm/smmuv3.c
187
+++ b/hw/arm/smmuv3.c
188
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
189
{
190
dma_addr_t end, addr = CMD_ADDR(cmd);
191
uint8_t type = CMD_TYPE(cmd);
192
- uint16_t vmid = CMD_VMID(cmd);
193
+ int vmid = -1;
194
uint8_t scale = CMD_SCALE(cmd);
195
uint8_t num = CMD_NUM(cmd);
196
uint8_t ttl = CMD_TTL(cmd);
197
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
198
uint64_t num_pages;
199
uint8_t granule;
200
int asid = -1;
201
+ SMMUv3State *smmuv3 = ARM_SMMUV3(s);
202
+
203
+ /* Only consider VMID if stage-2 is supported. */
204
+ if (STAGE2_SUPPORTED(smmuv3)) {
205
+ vmid = CMD_VMID(cmd);
206
+ }
207
208
if (type == SMMU_CMD_TLBI_NH_VA) {
209
asid = CMD_ASID(cmd);
210
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
211
if (!tg) {
212
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
213
smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
214
- smmu_iotlb_inv_iova(s, asid, addr, tg, 1, ttl);
215
+ smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
216
return;
217
}
218
219
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
220
num_pages = (mask + 1) >> granule;
221
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
222
smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
223
- smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl);
224
+ smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
225
addr += mask + 1;
226
}
208
}
227
}
209
}
228
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
210
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
212
-{
213
- uint32_t val;
214
-
215
- switch (reg) {
216
- case 0: /* Basic Control */
217
- return s->phy_control;
218
- case 1: /* Basic Status */
219
- return s->phy_status;
220
- case 2: /* ID1 */
221
- return 0x0007;
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
243
-}
244
-
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
246
-{
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
304
+ return;
305
+ }
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
307
+
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
327
+ */
328
+
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
334
+#include "qemu/log.h"
335
+
336
+#define PHY_INT_ENERGYON (1 << 7)
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
338
+#define PHY_INT_FAULT (1 << 5)
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
229
index XXXXXXX..XXXXXXX 100644
487
index XXXXXXX..XXXXXXX 100644
230
--- a/hw/arm/trace-events
488
--- a/hw/net/Kconfig
231
+++ b/hw/arm/trace-events
489
+++ b/hw/net/Kconfig
232
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all"
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
233
smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
491
config SMC91C111
234
smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
492
bool
235
smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
493
236
-smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
494
+config LAN9118_PHY
237
-smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
495
+ bool
238
-smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d addr=0x%"PRIx64" tg=%d level=%d"
496
+
239
+smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
497
config LAN9118
240
+smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
498
bool
241
+smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d vmid=%d addr=0x%"PRIx64" tg=%d level=%d"
499
+ select LAN9118_PHY
242
500
select PTIMER
243
# smmuv3.c
501
244
smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
245
--
515
--
246
2.34.1
516
2.34.1
diff view generated by jsdifflib
New patch
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
imx_fec having more logging and tracing. Merge these improvements into
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
7
Some migration state how resides in the new device model which breaks migration
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/net/imx_fec.h | 9 ++-
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
26
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/net/imx_fec.h
30
+++ b/include/hw/net/imx_fec.h
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
32
#define TYPE_IMX_ENET "imx.enet"
33
34
#include "hw/sysbus.h"
35
+#include "hw/net/lan9118_phy.h"
36
+#include "hw/irq.h"
37
#include "net/net.h"
38
39
#define ENET_EIR 1
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
42
uint32_t tx_ring_num;
43
44
- uint32_t phy_status;
45
- uint32_t phy_control;
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
353
{
354
+ trace_lan9118_phy_write(val, reg);
355
+
356
switch (reg) {
357
case 0: /* Basic Control */
358
if (val & 0x8000) {
359
lan9118_phy_reset(s);
360
- break;
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
471
--
472
2.34.1
diff view generated by jsdifflib
[PULL 21/21] docs: sbsa: correct graphics card name
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
We moved from VGA to Bochs to have PCIe card.
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
4
5
5
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
12
---
9
docs/system/arm/sbsa.rst | 2 +-
13
hw/net/lan9118_phy.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
11
15
12
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/system/arm/sbsa.rst
18
--- a/hw/net/lan9118_phy.c
15
+++ b/docs/system/arm/sbsa.rst
19
+++ b/hw/net/lan9118_phy.c
16
@@ -XXX,XX +XXX,XX @@ The sbsa-ref board supports:
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
17
- System bus EHCI controller
21
val = s->advertise;
18
- CDROM and hard disc on AHCI bus
22
break;
19
- E1000E ethernet card on PCIe bus
23
case 5: /* Auto-neg Link Partner Ability */
20
- - VGA display adaptor on PCIe bus
24
- val = 0x0f71;
21
+ - Bochs display adapter on PCIe bus
25
+ val = 0x0fe1;
22
- A generic SBSA watchdog device
26
break;
23
27
case 6: /* Auto-neg Expansion */
28
val = 1;
24
--
29
--
25
2.34.1
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Prefer named constants over magic values for better readability.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/net/mii.h | 6 +++++
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
14
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/net/mii.h
18
+++ b/include/hw/net/mii.h
19
@@ -XXX,XX +XXX,XX @@
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
22
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
26
#define MII_ANAR_TXFD (1 << 8)
27
@@ -XXX,XX +XXX,XX @@
28
#define MII_ANAR_10FD (1 << 6)
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/net/lan9118_phy.c
49
+++ b/hw/net/lan9118_phy.c
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
117
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
166
--
167
2.34.1
diff view generated by jsdifflib
[PULL 17/21] arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Fabiano Rosas <farosas@suse.de>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
When we moved the arm default CONFIGs into Kconfig and removed them
3
The real device advertises this mode and the device model already advertises
4
from default.mak, we made it harder to identify which CONFIGs are
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
selected by default in case users want to disable them.
5
make the model more realistic.
6
6
7
Bring back the default entries into default.mak, but keep them
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
commented out. This way users can keep their workflows of editing
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
default.mak to remove build options without needing to search through
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Kconfig.
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
11
12
Reported-by: Thomas Huth <thuth@redhat.com>
13
Signed-off-by: Fabiano Rosas <farosas@suse.de>
14
Reviewed-by: Thomas Huth <thuth@redhat.com>
15
Message-id: 20230523180525.29994-3-farosas@suse.de
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
12
---
18
configs/devices/aarch64-softmmu/default.mak | 6 ++++
13
hw/net/lan9118_phy.c | 4 ++--
19
configs/devices/arm-softmmu/default.mak | 40 +++++++++++++++++++++
14
1 file changed, 2 insertions(+), 2 deletions(-)
20
2 files changed, 46 insertions(+)
21
15
22
diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
23
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
24
--- a/configs/devices/aarch64-softmmu/default.mak
18
--- a/hw/net/lan9118_phy.c
25
+++ b/configs/devices/aarch64-softmmu/default.mak
19
+++ b/hw/net/lan9118_phy.c
26
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
27
21
break;
28
# We support all the 32 bit boards so need all their config
22
case MII_ANAR:
29
include ../arm-softmmu/default.mak
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
30
+
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
31
+# These are selected by default when TCG is enabled, uncomment them to
25
- MII_ANAR_SELECT))
32
+# keep out of the build.
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
33
+# CONFIG_XLNX_ZYNQMP_ARM=n
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
34
+# CONFIG_XLNX_VERSAL=n
28
| MII_ANAR_TX;
35
+# CONFIG_SBSA_REF=n
29
break;
36
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
30
case 30: /* Interrupt mask */
37
index XXXXXXX..XXXXXXX 100644
38
--- a/configs/devices/arm-softmmu/default.mak
39
+++ b/configs/devices/arm-softmmu/default.mak
40
@@ -XXX,XX +XXX,XX @@
41
# CONFIG_TEST_DEVICES=n
42
43
CONFIG_ARM_VIRT=y
44
+
45
+# These are selected by default when TCG is enabled, uncomment them to
46
+# keep out of the build.
47
+# CONFIG_CUBIEBOARD=n
48
+# CONFIG_EXYNOS4=n
49
+# CONFIG_HIGHBANK=n
50
+# CONFIG_INTEGRATOR=n
51
+# CONFIG_FSL_IMX31=n
52
+# CONFIG_MUSICPAL=n
53
+# CONFIG_MUSCA=n
54
+# CONFIG_CHEETAH=n
55
+# CONFIG_SX1=n
56
+# CONFIG_NSERIES=n
57
+# CONFIG_STELLARIS=n
58
+# CONFIG_STM32VLDISCOVERY=n
59
+# CONFIG_REALVIEW=n
60
+# CONFIG_VERSATILE=n
61
+# CONFIG_VEXPRESS=n
62
+# CONFIG_ZYNQ=n
63
+# CONFIG_MAINSTONE=n
64
+# CONFIG_GUMSTIX=n
65
+# CONFIG_SPITZ=n
66
+# CONFIG_TOSA=n
67
+# CONFIG_Z2=n
68
+# CONFIG_NPCM7XX=n
69
+# CONFIG_COLLIE=n
70
+# CONFIG_ASPEED_SOC=n
71
+# CONFIG_NETDUINO2=n
72
+# CONFIG_NETDUINOPLUS2=n
73
+# CONFIG_OLIMEX_STM32_H405=n
74
+# CONFIG_MPS2=n
75
+# CONFIG_RASPI=n
76
+# CONFIG_DIGIC=n
77
+# CONFIG_SABRELITE=n
78
+# CONFIG_EMCRAFT_SF2=n
79
+# CONFIG_MICROBIT=n
80
+# CONFIG_FSL_IMX25=n
81
+# CONFIG_FSL_IMX7=n
82
+# CONFIG_FSL_IMX6UL=n
83
+# CONFIG_ALLWINNER_H3=n
84
--
31
--
85
2.34.1
32
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
1
6
7
For the cases where the infzero test in pickNaNMulAdd was
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
13
14
For Arm, this looks like it might be a behaviour change because we
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
37
---
38
fpu/softfloat-parts.c.inc | 13 +++++++------
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
41
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
43
index XXXXXXX..XXXXXXX 100644
44
--- a/fpu/softfloat-parts.c.inc
45
+++ b/fpu/softfloat-parts.c.inc
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
47
int ab_mask, int abc_mask)
48
{
49
int which;
50
+ bool infzero = (ab_mask == float_cmask_infzero);
51
52
if (unlikely(abc_mask & float_cmask_snan)) {
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
54
}
55
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
57
- ab_mask == float_cmask_infzero, s);
58
+ if (infzero) {
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
61
+ }
62
+
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
64
65
if (s->default_nan_mode || which == 3) {
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
165
--
166
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
architectures thus do different things:
4
* some return the default NaN
5
* some return the input NaN
6
* Arm returns the default NaN if the input NaN is quiet,
7
and the input NaN if it is signalling
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
33
---
34
include/fpu/softfloat-helpers.h | 11 ++++
35
include/fpu/softfloat-types.h | 23 +++++++++
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/fpu/softfloat-helpers.h
42
+++ b/include/fpu/softfloat-helpers.h
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
44
status->float_2nan_prop_rule = rule;
45
}
46
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
49
+{
50
+ status->float_infzeronan_rule = rule;
51
+}
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
54
{
55
status->flush_to_zero = val;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
57
return status->float_2nan_prop_rule;
58
}
59
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
61
+{
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
256
--
257
2.34.1
diff view generated by jsdifflib
[PULL 01/21] fsl-imx6: Add SNVS support for i.MX6 boards
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
From: Vitaly Cheptsov <cheptsov@ispras.ru>
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
2
5
3
SNVS is supported on both i.MX6 and i.MX6UL and is needed
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
to support shutdown on the board.
5
6
Cc: Peter Maydell <peter.maydell@linaro.org> (odd fixer:SABRELITE / i.MX6)
7
Cc: Jean-Christophe Dubois <jcd@tribudubois.net> (reviewer:SABRELITE / i.MX6)
8
Cc: qemu-arm@nongnu.org (open list:SABRELITE / i.MX6)
9
Cc: qemu-devel@nongnu.org (open list:All patches CC here)
10
Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru>
11
Message-id: 20230515095015.66860-1-cheptsov@ispras.ru
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
14
---
9
---
15
include/hw/arm/fsl-imx6.h | 2 ++
10
tests/fp/fp-bench.c | 5 +++++
16
hw/arm/fsl-imx6.c | 8 ++++++++
11
tests/fp/fp-test.c | 5 +++++
17
2 files changed, 10 insertions(+)
12
2 files changed, 10 insertions(+)
18
13
19
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/fsl-imx6.h
16
--- a/tests/fp/fp-bench.c
22
+++ b/include/hw/arm/fsl-imx6.h
17
+++ b/tests/fp/fp-bench.c
23
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
24
#include "hw/cpu/a9mpcore.h"
19
{
25
#include "hw/misc/imx6_ccm.h"
20
bench_func_t f;
26
#include "hw/misc/imx6_src.h"
21
27
+#include "hw/misc/imx7_snvs.h"
22
+ /*
28
#include "hw/watchdog/wdt_imx2.h"
23
+ * These implementation-defined choices for various things IEEE
29
#include "hw/char/imx_serial.h"
24
+ * doesn't specify match those used by the Arm architecture.
30
#include "hw/timer/imx_gpt.h"
25
+ */
31
@@ -XXX,XX +XXX,XX @@ struct FslIMX6State {
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
32
A9MPPrivState a9mpcore;
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
33
IMX6CCMState ccm;
28
34
IMX6SRCState src;
29
f = bench_funcs[operation][precision];
35
+ IMX7SNVSState snvs;
30
g_assert(f);
36
IMXSerialState uart[FSL_IMX6_NUM_UARTS];
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
IMXGPTState gpt;
38
IMXEPITState epit[FSL_IMX6_NUM_EPITS];
39
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
40
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/fsl-imx6.c
33
--- a/tests/fp/fp-test.c
42
+++ b/hw/arm/fsl-imx6.c
34
+++ b/tests/fp/fp-test.c
43
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
44
36
{
45
object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
37
unsigned int i;
46
47
+ object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
48
+
49
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
50
snprintf(name, NAME_SIZE, "uart%d", i + 1);
51
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
52
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
53
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
54
FSL_IMX6_ENET_MAC_1588_IRQ));
55
38
56
+ /*
39
+ /*
57
+ * SNVS
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
58
+ */
42
+ */
59
+ sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
60
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
61
+
45
62
/*
46
genCases_setLevel(test_level);
63
* Watchdog
47
verCases_maxErrorCount = n_max_errors;
64
*/
65
--
48
--
66
2.34.1
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 3 +++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
21
+ * and the input NaN if it is signalling
22
*/
23
static void arm_set_default_fp_behaviours(float_status *s)
24
{
25
set_float_detect_tininess(float_tininess_before_rounding, s);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
28
}
29
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
/*
37
* Temporarily fall back to ifdef ladder
38
*/
39
-#if defined(TARGET_ARM)
40
- /*
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
50
--
51
2.34.1
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[PULL 03/21] hw/arm/smmuv3: Update translation config to hold stage-2
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Mostafa Saleh <smostafa@google.com>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
In preparation for adding stage-2 support, add a S2 config
3
are NaNs. As a result different architectures have ended up with
4
struct(SMMUS2Cfg), composed of the following fields and embedded in
4
different rules for propagating NaNs.
5
the main SMMUTransCfg:
5
6
-tsz: Size of IPA input region (S2T0SZ)
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
-sl0: Start level of translation (S2SL0)
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
-affd: AF Fault Disable (S2AFFD)
8
We want to make the propagation rule instead be selectable at
9
-record_faults: Record fault events (S2R)
9
runtime, because:
10
-granule_sz: Granule page shift (based on S2TG)
10
* this will let us have multiple targets in one QEMU binary
11
-vmid: Virtual Machine ID (S2VMID)
11
* the Arm FEAT_AFP architectural feature includes letting
12
-vttb: Address of translation table base (S2TTB)
12
the guest select a NaN propagation rule at runtime
13
-eff_ps: Effective PA output range (based on S2PS)
13
14
14
In this commit we add an enum for the propagation rule, the field in
15
They will be used in the next patches in stage-2 address translation.
15
float_status, and the corresponding getters and setters. We change
16
16
pickNaNMulAdd to honour this, but because all targets still leave
17
The fields in SMMUS2Cfg, are reordered to make the shared and stage-1
17
this field at its default 0 value, the fallback logic will pick the
18
fields next to each other, this reordering didn't change the struct
18
rule type with the old ifdef ladder.
19
size (104 bytes before and after).
19
20
20
It's valid not to set a propagation rule if default_nan_mode is
21
Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas.
21
enabled, because in that case there's no need to pick a NaN; all the
22
oas is stage-1 output address size. However, it is used to check
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
input address in case stage-1 is unimplemented or bypassed according
23
24
to SMMUv3 manual IHI0070.E "3.4. Address sizes"
25
26
Shared fields: stage, disabled, bypassed, aborted, iotlb_*.
27
28
No functional change intended.
29
30
Reviewed-by: Eric Auger <eric.auger@redhat.com>
31
Signed-off-by: Mostafa Saleh <smostafa@google.com>
32
Tested-by: Eric Auger <eric.auger@redhat.com>
33
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
34
Message-id: 20230516203327.2051088-3-smostafa@google.com
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
36
---
27
---
37
include/hw/arm/smmu-common.h | 22 +++++++++++++++++++---
28
include/fpu/softfloat-helpers.h | 11 +++
38
1 file changed, 19 insertions(+), 3 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
39
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
40
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
41
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/arm/smmu-common.h
35
--- a/include/fpu/softfloat-helpers.h
43
+++ b/include/hw/arm/smmu-common.h
36
+++ b/include/fpu/softfloat-helpers.h
44
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTLBEntry {
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
45
uint8_t granule;
38
status->float_2nan_prop_rule = rule;
46
} SMMUTLBEntry;
39
}
47
40
48
+/* Stage-2 configuration. */
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
49
+typedef struct SMMUS2Cfg {
42
+ float_status *status)
50
+ uint8_t tsz; /* Size of IPA input region (S2T0SZ) */
43
+{
51
+ uint8_t sl0; /* Start level of translation (S2SL0) */
44
+ status->float_3nan_prop_rule = rule;
52
+ bool affd; /* AF Fault Disable (S2AFFD) */
45
+}
53
+ bool record_faults; /* Record fault events (S2R) */
46
+
54
+ uint8_t granule_sz; /* Granule page shift (based on S2TG) */
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
55
+ uint8_t eff_ps; /* Effective PA output range (based on S2PS) */
48
float_status *status)
56
+ uint16_t vmid; /* Virtual Machine ID (S2VMID) */
49
{
57
+ uint64_t vttb; /* Address of translation table base (S2TTB) */
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
58
+} SMMUS2Cfg;
51
return status->float_2nan_prop_rule;
52
}
53
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
55
+{
56
+ return status->float_3nan_prop_rule;
57
+}
58
+
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
60
{
61
return status->float_infzeronan_rule;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
59
+
71
+
60
/*
72
/*
61
* Generic structure populated by derived SMMU devices
73
* Software IEC/IEEE floating-point types.
62
* after decoding the configuration information and used as
63
* input to the page table walk
64
*/
74
*/
65
typedef struct SMMUTransCfg {
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
66
+ /* Shared fields between stage-1 and stage-2. */
76
float_2nan_prop_x87,
67
int stage; /* translation stage */
77
} Float2NaNPropRule;
68
- bool aa64; /* arch64 or aarch32 translation table */
78
69
bool disabled; /* smmu is disabled */
79
+/*
70
bool bypassed; /* translation is bypassed */
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
71
bool aborted; /* translation is aborted */
81
+ * architectures have different rules for which input NaN is
72
+ uint32_t iotlb_hits; /* counts IOTLB hits */
82
+ * propagated to the output when there is more than one NaN on the
73
+ uint32_t iotlb_misses; /* counts IOTLB misses*/
83
+ * input.
74
+ /* Used by stage-1 only. */
84
+ *
75
+ bool aa64; /* arch64 or aarch32 translation table */
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
76
bool record_faults; /* record fault events */
86
+ * propagation rule, because the softfloat code guarantees not to try
77
uint64_t ttb; /* TT base address */
87
+ * to pick a NaN to propagate in default NaN mode. When not in
78
uint8_t oas; /* output address width */
88
+ * default-NaN mode, it is an error for the target not to set the rule
79
uint8_t tbi; /* Top Byte Ignore */
89
+ * in float_status if it uses a muladd, and we will assert if we need
80
uint16_t asid;
90
+ * to handle an input NaN and no rule was selected.
81
SMMUTransTableInfo tt[2];
91
+ *
82
- uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
92
+ * The naming scheme for Float3NaNPropRule values is:
83
- uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
93
+ * float_3nan_prop_s_abc:
84
+ /* Used by stage-2 only. */
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
85
+ struct SMMUS2Cfg s2cfg;
95
+ * float_3nan_prop_abc:
86
} SMMUTransCfg;
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
87
97
+ *
88
typedef struct SMMUDevice {
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
158
}
159
}
160
161
+ if (rule == float_3nan_prop_none) {
162
#if defined(TARGET_ARM)
163
-
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
166
- */
167
- if (is_snan(c_cls)) {
168
- return 2;
169
- } else if (is_snan(a_cls)) {
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
337
}
338
339
/*----------------------------------------------------------------------------
89
--
340
--
90
2.34.1
341
2.34.1
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 5 +++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
}
34
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/fpu/softfloat-specialize.c.inc
38
+++ b/fpu/softfloat-specialize.c.inc
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
40
}
41
42
if (rule == float_3nan_prop_none) {
43
-#if defined(TARGET_ARM)
44
- /*
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
47
- */
48
- rule = float_3nan_prop_s_cab;
49
-#elif defined(TARGET_MIPS)
50
+#if defined(TARGET_MIPS)
51
if (snan_bit_is_one(status)) {
52
rule = float_3nan_prop_s_abc;
53
} else {
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 19/21] Update copyright dates to 2023
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
From: Enze Li <lienze@kylinos.cn>
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
I noticed that in the latest version, the copyright string is still
4
2022, even though 2023 is halfway through. This patch fixes that and
5
fixes the documentation along with it.
6
7
Signed-off-by: Enze Li <lienze@kylinos.cn>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20230525064345.1152801-1-lienze@kylinos.cn
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
11
---
7
---
12
docs/conf.py | 2 +-
8
target/sparc/cpu.c | 2 ++
13
include/qemu/help-texts.h | 2 +-
9
fpu/softfloat-specialize.c.inc | 2 --
14
2 files changed, 2 insertions(+), 2 deletions(-)
10
2 files changed, 2 insertions(+), 2 deletions(-)
15
11
16
diff --git a/docs/conf.py b/docs/conf.py
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/conf.py
14
--- a/target/sparc/cpu.c
19
+++ b/docs/conf.py
15
+++ b/target/sparc/cpu.c
20
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
21
17
* the CPU state struct so it won't get zeroed on reset.
22
# General information about the project.
18
*/
23
project = u'QEMU'
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
24
-copyright = u'2022, The QEMU Project Developers'
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
25
+copyright = u'2023, The QEMU Project Developers'
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
26
author = u'The QEMU Project Developers'
22
/* For inf * 0 + NaN, return the input NaN */
27
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
28
# The version info for the project you're documenting, acts as replacement for
24
29
diff --git a/include/qemu/help-texts.h b/include/qemu/help-texts.h
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
31
--- a/include/qemu/help-texts.h
27
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/include/qemu/help-texts.h
28
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
#define QEMU_HELP_TEXTS_H
30
} else {
35
31
rule = float_3nan_prop_s_cab;
36
/* Copyright string for -version arguments, About dialogs, etc */
32
}
37
-#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \
33
-#elif defined(TARGET_SPARC)
38
+#define QEMU_COPYRIGHT "Copyright (c) 2003-2023 " \
34
- rule = float_3nan_prop_s_cba;
39
"Fabrice Bellard and the QEMU Project developers"
35
#elif defined(TARGET_XTENSA)
40
36
if (status->use_first_nan) {
41
/* Bug reporting information for --help arguments, About dialogs, etc */
37
rule = float_3nan_prop_abc;
42
--
38
--
43
2.34.1
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
32
}
33
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
68
--
69
2.34.1
diff view generated by jsdifflib
New patch
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
8
target/xtensa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
11
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/fpu_helper.c
15
+++ b/target/xtensa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
22
}
23
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
}
31
32
if (rule == float_3nan_prop_none) {
33
-#if defined(TARGET_XTENSA)
34
- if (status->use_first_nan) {
35
- rule = float_3nan_prop_abc;
36
- } else {
37
- rule = float_3nan_prop_cba;
38
- }
39
-#else
40
rule = float_3nan_prop_abc;
41
-#endif
42
}
43
44
assert(rule != float_3nan_prop_none);
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
HPPA is the only target that was using the default branch of the
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
16
---
17
target/hppa/fpu_helper.c | 8 ++++++++
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
20
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/hppa/fpu_helper.c
24
+++ b/target/hppa/fpu_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
46
}
47
48
- if (rule == float_3nan_prop_none) {
49
- rule = float_3nan_prop_abc;
50
- }
51
-
52
assert(rule != float_3nan_prop_none);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
/* We have at least one SNaN input and should prefer it */
55
--
56
2.34.1
diff view generated by jsdifflib
New patch
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
15
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/fpu/softfloat-helpers.h
19
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
21
status->snan_bit_is_one = val;
22
}
23
24
-static inline void set_use_first_nan(bool val, float_status *status)
25
-{
26
- status->use_first_nan = val;
27
-}
28
-
29
static inline void set_no_signaling_nans(bool val, float_status *status)
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/helper.c
20
+++ b/target/m68k/helper.c
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
22
CPUM68KState *env = &cpu->env;
23
24
if (n < 8) {
25
- float_status s = {};
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
27
+ float_status s = env->fp_status;
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
29
}
30
switch (n) {
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
32
CPUM68KState *env = &cpu->env;
33
34
if (n < 8) {
35
- float_status s = {};
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 10/21] hw/arm/smmuv3: Add stage-2 support in iova notifier
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Mostafa Saleh <smostafa@google.com>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
In smmuv3_notify_iova, read the granule based on translation stage
8
To do this we need to pass the CPU env pointer in to the helper.
4
and use VMID if valid value is sent.
5
9
6
Signed-off-by: Mostafa Saleh <smostafa@google.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Tested-by: Eric Auger <eric.auger@redhat.com>
9
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Message-id: 20230516203327.2051088-10-smostafa@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
12
---
13
---
13
hw/arm/smmuv3.c | 39 ++++++++++++++++++++++++++-------------
14
target/sparc/helper.h | 4 ++--
14
hw/arm/trace-events | 2 +-
15
target/sparc/fop_helper.c | 8 ++++----
15
2 files changed, 27 insertions(+), 14 deletions(-)
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
16
18
17
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/smmuv3.c
21
--- a/target/sparc/helper.h
20
+++ b/hw/arm/smmuv3.c
22
+++ b/target/sparc/helper.h
21
@@ -XXX,XX +XXX,XX @@ epilogue:
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
22
* @mr: IOMMU mr region handle
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
23
* @n: notifier to be called
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
24
* @asid: address space ID or negative value if we don't care
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
25
+ * @vmid: virtual machine ID or negative value if we don't care
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
26
* @iova: iova
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
27
* @tg: translation granule (if communicated through range invalidation)
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
28
* @num_pages: number of @granule sized pages (if tg != 0), otherwise 1
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
29
*/
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
30
static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
32
31
IOMMUNotifier *n,
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
32
- int asid, dma_addr_t iova,
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
33
- uint8_t tg, uint64_t num_pages)
35
index XXXXXXX..XXXXXXX 100644
34
+ int asid, int vmid,
36
--- a/target/sparc/fop_helper.c
35
+ dma_addr_t iova, uint8_t tg,
37
+++ b/target/sparc/fop_helper.c
36
+ uint64_t num_pages)
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
39
return finish_fcmp(env, r, GETPC());
40
}
41
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
37
{
44
{
38
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
45
/*
39
IOMMUTLBEvent event;
46
* FLCMP never raises an exception nor modifies any FSR fields.
40
uint8_t granule;
47
* Perform the comparison with a dummy fp environment.
41
+ SMMUv3State *s = sdev->smmu;
48
*/
42
49
- float_status discard = { };
43
if (!tg) {
50
+ float_status discard = env->fp_status;
44
SMMUEventInfo event = {.inval_ste_allowed = true};
51
FloatRelation r;
45
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
52
46
return;
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
47
}
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
48
55
g_assert_not_reached();
49
- tt = select_tt(cfg, iova);
50
- if (!tt) {
51
+ if (vmid >= 0 && cfg->s2cfg.vmid != vmid) {
52
return;
53
}
54
- granule = tt->granule_sz;
55
+
56
+ if (STAGE1_SUPPORTED(s)) {
57
+ tt = select_tt(cfg, iova);
58
+ if (!tt) {
59
+ return;
60
+ }
61
+ granule = tt->granule_sz;
62
+ } else {
63
+ granule = cfg->s2cfg.granule_sz;
64
+ }
65
+
66
} else {
67
granule = tg * 2 + 10;
68
}
69
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
70
memory_region_notify_iommu_one(n, &event);
71
}
56
}
72
57
73
-/* invalidate an asid/iova range tuple in all mr's */
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
74
-static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
75
- uint8_t tg, uint64_t num_pages)
76
+/* invalidate an asid/vmid/iova range tuple in all mr's */
77
+static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid,
78
+ dma_addr_t iova, uint8_t tg,
79
+ uint64_t num_pages)
80
{
60
{
81
SMMUDevice *sdev;
61
- float_status discard = { };
82
62
+ float_status discard = env->fp_status;
83
@@ -XXX,XX +XXX,XX @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
63
FloatRelation r;
84
IOMMUMemoryRegion *mr = &sdev->iommu;
64
85
IOMMUNotifier *n;
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
86
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
87
- trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova,
67
index XXXXXXX..XXXXXXX 100644
88
- tg, num_pages);
68
--- a/target/sparc/translate.c
89
+ trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, vmid,
69
+++ b/target/sparc/translate.c
90
+ iova, tg, num_pages);
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
91
71
92
IOMMU_NOTIFIER_FOREACH(n, mr) {
72
src1 = gen_load_fpr_F(dc, a->rs1);
93
- smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages);
73
src2 = gen_load_fpr_F(dc, a->rs2);
94
+ smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
95
}
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
96
}
76
return advance_pc(dc);
97
}
77
}
98
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
78
99
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
100
if (!tg) {
80
101
trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
81
src1 = gen_load_fpr_D(dc, a->rs1);
102
- smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
82
src2 = gen_load_fpr_D(dc, a->rs2);
103
+ smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1);
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
104
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
105
return;
85
return advance_pc(dc);
106
}
86
}
107
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
108
109
num_pages = (mask + 1) >> granule;
110
trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
111
- smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
112
+ smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages);
113
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
114
addr += mask + 1;
115
}
116
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/arm/trace-events
119
+++ b/hw/arm/trace-events
120
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
121
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
122
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
123
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
124
-smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
125
+smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
126
87
127
--
88
--
128
2.34.1
89
2.34.1
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[PULL 18/21] arm/Kconfig: Make TCG dependence explicit
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Fabiano Rosas <farosas@suse.de>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Replace the 'default y if TCG' pattern with 'default y; depends on
3
Now that float_status has a bunch of fp parameters,
4
TCG'.
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
5
8
6
That makes explict that there is a dependence on TCG and enabling
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
these CONFIGs via .mak files without TCG present will fail earlier.
8
9
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
10
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
Reviewed-by: Thomas Huth <thuth@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Message-id: 20230523180525.29994-4-farosas@suse.de
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
14
---
16
hw/arm/Kconfig | 123 ++++++++++++++++++++++++++++++++-----------------
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
17
1 file changed, 82 insertions(+), 41 deletions(-)
16
1 file changed, 7 insertions(+), 13 deletions(-)
18
17
19
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
20
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/Kconfig
20
--- a/target/arm/tcg/vec_helper.c
22
+++ b/hw/arm/Kconfig
21
+++ b/target/arm/tcg/vec_helper.c
23
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
24
23
* no effect on AArch32 instructions.
25
config CHEETAH
24
*/
26
bool
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
27
- default y if TCG && ARM
26
- *statusp = (float_status){
28
+ default y
27
- .tininess_before_rounding = float_tininess_before_rounding,
29
+ depends on TCG && ARM
28
- .float_rounding_mode = float_round_to_odd_inf,
30
select OMAP
29
- .flush_to_zero = true,
31
select TSC210X
30
- .flush_inputs_to_zero = true,
32
31
- .default_nan_mode = true,
33
config CUBIEBOARD
32
- };
34
bool
33
+
35
- default y if TCG && ARM
34
+ *statusp = env->vfp.fp_status;
36
+ default y
35
+ set_default_nan_mode(true, statusp);
37
+ depends on TCG && ARM
36
38
select ALLWINNER_A10
37
if (ebf) {
39
38
- float_status *fpst = &env->vfp.fp_status;
40
config DIGIC
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
41
bool
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
42
- default y if TCG && ARM
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
43
+ default y
42
-
44
+ depends on TCG && ARM
43
/* EBF=1 needs to do a step with round-to-odd semantics */
45
select PTIMER
44
*oddstatusp = *statusp;
46
select PFLASH_CFI02
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
47
46
+ } else {
48
config EXYNOS4
47
+ set_flush_to_zero(true, statusp);
49
bool
48
+ set_flush_inputs_to_zero(true, statusp);
50
- default y if TCG && ARM
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
51
+ default y
50
}
52
+ depends on TCG && ARM
51
-
53
imply I2C_DEVICES
52
return ebf;
54
select A9MPCORE
53
}
55
select I2C
56
@@ -XXX,XX +XXX,XX @@ config EXYNOS4
57
58
config HIGHBANK
59
bool
60
- default y if TCG && ARM
61
+ default y
62
+ depends on TCG && ARM
63
select A9MPCORE
64
select A15MPCORE
65
select AHCI
66
@@ -XXX,XX +XXX,XX @@ config HIGHBANK
67
68
config INTEGRATOR
69
bool
70
- default y if TCG && ARM
71
+ default y
72
+ depends on TCG && ARM
73
select ARM_TIMER
74
select INTEGRATOR_DEBUG
75
select PL011 # UART
76
@@ -XXX,XX +XXX,XX @@ config INTEGRATOR
77
78
config MAINSTONE
79
bool
80
- default y if TCG && ARM
81
+ default y
82
+ depends on TCG && ARM
83
select PXA2XX
84
select PFLASH_CFI01
85
select SMC91C111
86
87
config MUSCA
88
bool
89
- default y if TCG && ARM
90
+ default y
91
+ depends on TCG && ARM
92
select ARMSSE
93
select PL011
94
select PL031
95
@@ -XXX,XX +XXX,XX @@ config MARVELL_88W8618
96
97
config MUSICPAL
98
bool
99
- default y if TCG && ARM
100
+ default y
101
+ depends on TCG && ARM
102
select OR_IRQ
103
select BITBANG_I2C
104
select MARVELL_88W8618
105
@@ -XXX,XX +XXX,XX @@ config MUSICPAL
106
107
config NETDUINO2
108
bool
109
- default y if TCG && ARM
110
+ default y
111
+ depends on TCG && ARM
112
select STM32F205_SOC
113
114
config NETDUINOPLUS2
115
bool
116
- default y if TCG && ARM
117
+ default y
118
+ depends on TCG && ARM
119
select STM32F405_SOC
120
121
config OLIMEX_STM32_H405
122
bool
123
- default y if TCG && ARM
124
+ default y
125
+ depends on TCG && ARM
126
select STM32F405_SOC
127
128
config NSERIES
129
bool
130
- default y if TCG && ARM
131
+ default y
132
+ depends on TCG && ARM
133
select OMAP
134
select TMP105 # temperature sensor
135
select BLIZZARD # LCD/TV controller
136
@@ -XXX,XX +XXX,XX @@ config PXA2XX
137
138
config GUMSTIX
139
bool
140
- default y if TCG && ARM
141
+ default y
142
+ depends on TCG && ARM
143
select PFLASH_CFI01
144
select SMC91C111
145
select PXA2XX
146
147
config TOSA
148
bool
149
- default y if TCG && ARM
150
+ default y
151
+ depends on TCG && ARM
152
select ZAURUS # scoop
153
select MICRODRIVE
154
select PXA2XX
155
@@ -XXX,XX +XXX,XX @@ config TOSA
156
157
config SPITZ
158
bool
159
- default y if TCG && ARM
160
+ default y
161
+ depends on TCG && ARM
162
select ADS7846 # touch-screen controller
163
select MAX111X # A/D converter
164
select WM8750 # audio codec
165
@@ -XXX,XX +XXX,XX @@ config SPITZ
166
167
config Z2
168
bool
169
- default y if TCG && ARM
170
+ default y
171
+ depends on TCG && ARM
172
select PFLASH_CFI01
173
select WM8750
174
select PL011 # UART
175
@@ -XXX,XX +XXX,XX @@ config Z2
176
177
config REALVIEW
178
bool
179
- default y if TCG && ARM
180
+ default y
181
+ depends on TCG && ARM
182
imply PCI_DEVICES
183
imply PCI_TESTDEV
184
imply I2C_DEVICES
185
@@ -XXX,XX +XXX,XX @@ config REALVIEW
186
187
config SBSA_REF
188
bool
189
- default y if TCG && AARCH64
190
+ default y
191
+ depends on TCG && AARCH64
192
imply PCI_DEVICES
193
select AHCI
194
select ARM_SMMUV3
195
@@ -XXX,XX +XXX,XX @@ config SBSA_REF
196
197
config SABRELITE
198
bool
199
- default y if TCG && ARM
200
+ default y
201
+ depends on TCG && ARM
202
select FSL_IMX6
203
select SSI_M25P80
204
205
config STELLARIS
206
bool
207
- default y if TCG && ARM
208
+ default y
209
+ depends on TCG && ARM
210
imply I2C_DEVICES
211
select ARM_V7M
212
select CMSDK_APB_WATCHDOG
213
@@ -XXX,XX +XXX,XX @@ config STELLARIS
214
215
config STM32VLDISCOVERY
216
bool
217
- default y if TCG && ARM
218
+ default y
219
+ depends on TCG && ARM
220
select STM32F100_SOC
221
222
config STRONGARM
223
@@ -XXX,XX +XXX,XX @@ config STRONGARM
224
225
config COLLIE
226
bool
227
- default y if TCG && ARM
228
+ default y
229
+ depends on TCG && ARM
230
select PFLASH_CFI01
231
select ZAURUS # scoop
232
select STRONGARM
233
234
config SX1
235
bool
236
- default y if TCG && ARM
237
+ default y
238
+ depends on TCG && ARM
239
select OMAP
240
241
config VERSATILE
242
bool
243
- default y if TCG && ARM
244
+ default y
245
+ depends on TCG && ARM
246
select ARM_TIMER # sp804
247
select PFLASH_CFI01
248
select LSI_SCSI_PCI
249
@@ -XXX,XX +XXX,XX @@ config VERSATILE
250
251
config VEXPRESS
252
bool
253
- default y if TCG && ARM
254
+ default y
255
+ depends on TCG && ARM
256
select A9MPCORE
257
select A15MPCORE
258
select ARM_MPTIMER
259
@@ -XXX,XX +XXX,XX @@ config VEXPRESS
260
261
config ZYNQ
262
bool
263
- default y if TCG && ARM
264
+ default y
265
+ depends on TCG && ARM
266
select A9MPCORE
267
select CADENCE # UART
268
select PFLASH_CFI02
269
@@ -XXX,XX +XXX,XX @@ config ZYNQ
270
config ARM_V7M
271
bool
272
# currently v7M must be included in a TCG build due to translate.c
273
- default y if TCG && ARM
274
+ default y
275
+ depends on TCG && ARM
276
select PTIMER
277
278
config ALLWINNER_A10
279
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
280
281
config ALLWINNER_H3
282
bool
283
- default y if TCG && ARM
284
+ default y
285
+ depends on TCG && ARM
286
select ALLWINNER_A10_PIT
287
select ALLWINNER_SUN8I_EMAC
288
select ALLWINNER_I2C
289
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
290
291
config RASPI
292
bool
293
- default y if TCG && ARM
294
+ default y
295
+ depends on TCG && ARM
296
select FRAMEBUFFER
297
select PL011 # UART
298
select SDHCI
299
@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC
300
301
config XLNX_ZYNQMP_ARM
302
bool
303
- default y if TCG && AARCH64
304
+ default y
305
+ depends on TCG && AARCH64
306
select AHCI
307
select ARM_GIC
308
select CADENCE
309
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
310
311
config XLNX_VERSAL
312
bool
313
- default y if TCG && AARCH64
314
+ default y
315
+ depends on TCG && AARCH64
316
select ARM_GIC
317
select PL011
318
select CADENCE
319
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
320
321
config NPCM7XX
322
bool
323
- default y if TCG && ARM
324
+ default y
325
+ depends on TCG && ARM
326
select A9MPCORE
327
select ADM1272
328
select ARM_GIC
329
@@ -XXX,XX +XXX,XX @@ config NPCM7XX
330
331
config FSL_IMX25
332
bool
333
- default y if TCG && ARM
334
+ default y
335
+ depends on TCG && ARM
336
imply I2C_DEVICES
337
select IMX
338
select IMX_FEC
339
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
340
341
config FSL_IMX31
342
bool
343
- default y if TCG && ARM
344
+ default y
345
+ depends on TCG && ARM
346
imply I2C_DEVICES
347
select SERIAL
348
select IMX
349
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
350
351
config ASPEED_SOC
352
bool
353
- default y if TCG && ARM
354
+ default y
355
+ depends on TCG && ARM
356
select DS1338
357
select FTGMAC100
358
select I2C
359
@@ -XXX,XX +XXX,XX @@ config ASPEED_SOC
360
361
config MPS2
362
bool
363
- default y if TCG && ARM
364
+ default y
365
+ depends on TCG && ARM
366
imply I2C_DEVICES
367
select ARMSSE
368
select LAN9118
369
@@ -XXX,XX +XXX,XX @@ config MPS2
370
371
config FSL_IMX7
372
bool
373
- default y if TCG && ARM
374
+ default y
375
+ depends on TCG && ARM
376
imply PCI_DEVICES
377
imply TEST_DEVICES
378
imply I2C_DEVICES
379
@@ -XXX,XX +XXX,XX @@ config ARM_SMMUV3
380
381
config FSL_IMX6UL
382
bool
383
- default y if TCG && ARM
384
+ default y
385
+ depends on TCG && ARM
386
imply I2C_DEVICES
387
select A15MPCORE
388
select IMX
389
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL
390
391
config MICROBIT
392
bool
393
- default y if TCG && ARM
394
+ default y
395
+ depends on TCG && ARM
396
select NRF51_SOC
397
398
config NRF51_SOC
399
@@ -XXX,XX +XXX,XX @@ config NRF51_SOC
400
401
config EMCRAFT_SF2
402
bool
403
- default y if TCG && ARM
404
+ default y
405
+ depends on TCG && ARM
406
select MSF2
407
select SSI_M25P80
408
54
409
--
55
--
410
2.34.1
56
2.34.1
411
57
412
58
diff view generated by jsdifflib
[PULL 05/21] hw/arm/smmuv3: Add page table walk for stage-2
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Mostafa Saleh <smostafa@google.com>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
In preparation for adding stage-2 support, add Stage-2 PTW code.
7
Add a field to float_status to specify the default NaN value; fall
4
Only Aarch64 format is supported as stage-1.
8
back to the old ifdef behaviour if these are not set.
5
9
6
Nesting stage-1 and stage-2 is not supported right now.
10
The default NaN value is specified by setting a uint8_t to a
11
pattern corresponding to the sign and upper fraction parts of
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
7
14
8
HTTU is not supported, SW is expected to maintain the Access flag.
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
This is described in the SMMUv3 manual(IHI 0070.E.a)
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
"5.2. Stream Table Entry" in "[181] S2AFFD".
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
11
This flag determines the behavior on access of a stage-2 page whose
18
---
12
descriptor has AF == 0:
19
include/fpu/softfloat-helpers.h | 11 +++++++
13
- 0b0: An Access flag fault occurs (stall not supported).
20
include/fpu/softfloat-types.h | 10 ++++++
14
- 0b1: An Access flag fault never occurs.
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
15
An Access fault takes priority over a Permission fault.
22
3 files changed, 54 insertions(+), 22 deletions(-)
16
23
17
There are 3 address size checks for stage-2 according to
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
18
(IHI 0070.E.a) in "3.4. Address sizes".
19
- As nesting is not supported, input address is passed directly to
20
stage-2, and is checked against IAS.
21
We use cfg->oas to hold the OAS when stage-1 is not used, this is set
22
in the next patch.
23
This check is done outside of smmu_ptw_64_s2 as it is not part of
24
stage-2(it throws stage-1 fault), and the stage-2 function shouldn't
25
change it's behavior when nesting is supported.
26
When nesting is supported and we figure out how to combine TLB for
27
stage-1 and stage-2 we can move this check into the stage-1 function
28
as described in ARM DDI0487I.a in pseudocode
29
aarch64/translation/vmsa_translation/AArch64.S1Translate
30
aarch64/translation/vmsa_translation/AArch64.S1DisabledOutput
31
32
- Input to stage-2 is checked against s2t0sz, and throws stage-2
33
transaltion fault if exceeds it.
34
35
- Output of stage-2 is checked against effective PA output range.
36
37
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Signed-off-by: Mostafa Saleh <smostafa@google.com>
39
Tested-by: Eric Auger <eric.auger@redhat.com>
40
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
41
Message-id: 20230516203327.2051088-5-smostafa@google.com
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
44
hw/arm/smmu-internal.h | 35 ++++++++++
45
hw/arm/smmu-common.c | 142 ++++++++++++++++++++++++++++++++++++++++-
46
2 files changed, 176 insertions(+), 1 deletion(-)
47
48
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
49
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/smmu-internal.h
26
--- a/include/fpu/softfloat-helpers.h
51
+++ b/hw/arm/smmu-internal.h
27
+++ b/include/fpu/softfloat-helpers.h
52
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
53
#define PTE_APTABLE(pte) \
29
status->float_infzeronan_rule = rule;
54
(extract64(pte, 61, 2))
55
56
+#define PTE_AF(pte) \
57
+ (extract64(pte, 10, 1))
58
/*
59
* TODO: At the moment all transactions are considered as privileged (EL1)
60
* as IOMMU translation callback does not pass user/priv attributes.
61
@@ -XXX,XX +XXX,XX @@
62
#define is_permission_fault(ap, perm) \
63
(((perm) & IOMMU_WO) && ((ap) & 0x2))
64
65
+#define is_permission_fault_s2(s2ap, perm) \
66
+ (!(((s2ap) & (perm)) == (perm)))
67
+
68
#define PTE_AP_TO_PERM(ap) \
69
(IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
70
71
@@ -XXX,XX +XXX,XX @@ uint64_t iova_level_offset(uint64_t iova, int inputsize,
72
MAKE_64BIT_MASK(0, gsz - 3);
73
}
30
}
74
31
75
+/* FEAT_LPA2 and FEAT_TTST are not implemented. */
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
76
+static inline int get_start_level(int sl0 , int granule_sz)
33
+ float_status *status)
77
+{
34
+{
78
+ /* ARM DDI0487I.a: Table D8-12. */
35
+ status->default_nan_pattern = dnan_pattern;
79
+ if (granule_sz == 12) {
80
+ return 2 - sl0;
81
+ }
82
+ /* ARM DDI0487I.a: Table D8-22 and Table D8-31. */
83
+ return 3 - sl0;
84
+}
36
+}
85
+
37
+
86
+/*
38
static inline void set_flush_to_zero(bool val, float_status *status)
87
+ * Index in a concatenated first level stage-2 page table.
39
{
88
+ * ARM DDI0487I.a: D8.2.2 Concatenated translation tables.
40
status->flush_to_zero = val;
89
+ */
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
90
+static inline int pgd_concat_idx(int start_level, int granule_sz,
42
return status->float_infzeronan_rule;
91
+ dma_addr_t ipa)
43
}
44
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
92
+{
46
+{
93
+ uint64_t ret;
47
+ return status->default_nan_pattern;
94
+ /*
95
+ * Get the number of bits handled by next levels, then any extra bits in
96
+ * the address should index the concatenated tables. This relation can be
97
+ * deduced from tables in ARM DDI0487I.a: D8.2.7-9
98
+ */
99
+ int shift = level_shift(start_level - 1, granule_sz);
100
+
101
+ ret = ipa >> shift;
102
+ return ret;
103
+}
48
+}
104
+
49
+
105
#define SMMU_IOTLB_ASID(key) ((key).asid)
50
static inline bool get_flush_to_zero(float_status *status)
106
51
{
107
typedef struct SMMUIOTLBPageInvInfo {
52
return status->flush_to_zero;
108
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
109
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/arm/smmu-common.c
55
--- a/include/fpu/softfloat-types.h
111
+++ b/hw/arm/smmu-common.c
56
+++ b/include/fpu/softfloat-types.h
112
@@ -XXX,XX +XXX,XX @@ error:
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
113
return -EINVAL;
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
114
}
59
bool flush_inputs_to_zero;
115
60
bool default_nan_mode;
116
+/**
117
+ * smmu_ptw_64_s2 - VMSAv8-64 Walk of the page tables for a given ipa
118
+ * for stage-2.
119
+ * @cfg: translation config
120
+ * @ipa: ipa to translate
121
+ * @perm: access type
122
+ * @tlbe: SMMUTLBEntry (out)
123
+ * @info: handle to an error info
124
+ *
125
+ * Return 0 on success, < 0 on error. In case of error, @info is filled
126
+ * and tlbe->perm is set to IOMMU_NONE.
127
+ * Upon success, @tlbe is filled with translated_addr and entry
128
+ * permission rights.
129
+ */
130
+static int smmu_ptw_64_s2(SMMUTransCfg *cfg,
131
+ dma_addr_t ipa, IOMMUAccessFlags perm,
132
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
133
+{
134
+ const int stage = 2;
135
+ int granule_sz = cfg->s2cfg.granule_sz;
136
+ /* ARM DDI0487I.a: Table D8-7. */
137
+ int inputsize = 64 - cfg->s2cfg.tsz;
138
+ int level = get_start_level(cfg->s2cfg.sl0, granule_sz);
139
+ int stride = VMSA_STRIDE(granule_sz);
140
+ int idx = pgd_concat_idx(level, granule_sz, ipa);
141
+ /*
61
+ /*
142
+ * Get the ttb from concatenated structure.
62
+ * The pattern to use for the default NaN. Here the high bit specifies
143
+ * The offset is the idx * size of each ttb(number of ptes * (sizeof(pte))
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
144
+ */
69
+ */
145
+ uint64_t baseaddr = extract64(cfg->s2cfg.vttb, 0, 48) + (1 << stride) *
70
+ uint8_t default_nan_pattern;
146
+ idx * sizeof(uint64_t);
71
/*
147
+ dma_addr_t indexmask = VMSA_IDXMSK(inputsize, stride, level);
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
148
+
136
+
149
+ baseaddr &= ~indexmask;
137
+ sign = dnan_pattern >> 7;
150
+
151
+ /*
138
+ /*
152
+ * On input, a stage 2 Translation fault occurs if the IPA is outside the
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
153
+ * range configured by the relevant S2T0SZ field of the STE.
140
+ * and replecate bit [0] down into [55:0]
154
+ */
141
+ */
155
+ if (ipa >= (1ULL << inputsize)) {
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
156
+ info->type = SMMU_PTW_ERR_TRANSLATION;
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
157
+ goto error;
144
158
+ }
145
*p = (FloatParts64) {
159
+
146
.cls = float_class_qnan,
160
+ while (level < VMSA_LEVELS) {
161
+ uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
162
+ uint64_t mask = subpage_size - 1;
163
+ uint32_t offset = iova_level_offset(ipa, inputsize, level, granule_sz);
164
+ uint64_t pte, gpa;
165
+ dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
166
+ uint8_t s2ap;
167
+
168
+ if (get_pte(baseaddr, offset, &pte, info)) {
169
+ goto error;
170
+ }
171
+ trace_smmu_ptw_level(stage, level, ipa, subpage_size,
172
+ baseaddr, offset, pte);
173
+ if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
174
+ trace_smmu_ptw_invalid_pte(stage, level, baseaddr,
175
+ pte_addr, offset, pte);
176
+ break;
177
+ }
178
+
179
+ if (is_table_pte(pte, level)) {
180
+ baseaddr = get_table_pte_address(pte, granule_sz);
181
+ level++;
182
+ continue;
183
+ } else if (is_page_pte(pte, level)) {
184
+ gpa = get_page_pte_address(pte, granule_sz);
185
+ trace_smmu_ptw_page_pte(stage, level, ipa,
186
+ baseaddr, pte_addr, pte, gpa);
187
+ } else {
188
+ uint64_t block_size;
189
+
190
+ gpa = get_block_pte_address(pte, level, granule_sz,
191
+ &block_size);
192
+ trace_smmu_ptw_block_pte(stage, level, baseaddr,
193
+ pte_addr, pte, ipa, gpa,
194
+ block_size >> 20);
195
+ }
196
+
197
+ /*
198
+ * If S2AFFD and PTE.AF are 0 => fault. (5.2. Stream Table Entry)
199
+ * An Access fault takes priority over a Permission fault.
200
+ */
201
+ if (!PTE_AF(pte) && !cfg->s2cfg.affd) {
202
+ info->type = SMMU_PTW_ERR_ACCESS;
203
+ goto error;
204
+ }
205
+
206
+ s2ap = PTE_AP(pte);
207
+ if (is_permission_fault_s2(s2ap, perm)) {
208
+ info->type = SMMU_PTW_ERR_PERMISSION;
209
+ goto error;
210
+ }
211
+
212
+ /*
213
+ * The address output from the translation causes a stage 2 Address
214
+ * Size fault if it exceeds the effective PA output range.
215
+ */
216
+ if (gpa >= (1ULL << cfg->s2cfg.eff_ps)) {
217
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
218
+ goto error;
219
+ }
220
+
221
+ tlbe->entry.translated_addr = gpa;
222
+ tlbe->entry.iova = ipa & ~mask;
223
+ tlbe->entry.addr_mask = mask;
224
+ tlbe->entry.perm = s2ap;
225
+ tlbe->level = level;
226
+ tlbe->granule = granule_sz;
227
+ return 0;
228
+ }
229
+ info->type = SMMU_PTW_ERR_TRANSLATION;
230
+
231
+error:
232
+ info->stage = 2;
233
+ tlbe->entry.perm = IOMMU_NONE;
234
+ return -EINVAL;
235
+}
236
+
237
/**
238
* smmu_ptw - Walk the page tables for an IOVA, according to @cfg
239
*
240
@@ -XXX,XX +XXX,XX @@ error:
241
int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
242
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
243
{
244
- return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
245
+ if (cfg->stage == 1) {
246
+ return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
247
+ } else if (cfg->stage == 2) {
248
+ /*
249
+ * If bypassing stage 1(or unimplemented), the input address is passed
250
+ * directly to stage 2 as IPA. If the input address of a transaction
251
+ * exceeds the size of the IAS, a stage 1 Address Size fault occurs.
252
+ * For AA64, IAS = OAS according to (IHI 0070.E.a) "3.4 Address sizes"
253
+ */
254
+ if (iova >= (1ULL << cfg->oas)) {
255
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
256
+ info->stage = 1;
257
+ tlbe->entry.perm = IOMMU_NONE;
258
+ return -EINVAL;
259
+ }
260
+
261
+ return smmu_ptw_64_s2(cfg, iova, perm, tlbe, info);
262
+ }
263
+
264
+ g_assert_not_reached();
265
}
266
267
/**
268
--
147
--
269
2.34.1
148
2.34.1
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 20/21] hw/arm/sbsa-ref: add GIC node into DT
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
Let add GIC information into DeviceTree as part of SBSA-REF versioning.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
9
---
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
4
13
5
Trusted Firmware will read it and provide to next firmware level.
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
6
7
Bumps platform version to 0.1 one so we can check is node is present.
8
9
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/sbsa-ref.c | 19 ++++++++++++++++++-
14
1 file changed, 18 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/sbsa-ref.c
16
--- a/linux-user/arm/nwfpe/fpa11.c
19
+++ b/hw/arm/sbsa-ref.c
17
+++ b/linux-user/arm/nwfpe/fpa11.c
20
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
21
#include "exec/hwaddr.h"
19
* this late date.
22
#include "kvm_arm.h"
20
*/
23
#include "hw/arm/boot.h"
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
24
+#include "hw/arm/fdt.h"
22
+ /*
25
#include "hw/arm/smmuv3.h"
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
26
#include "hw/block/flash.h"
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
27
#include "hw/boards.h"
25
+ */
28
@@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
29
return arm_cpu_mp_affinity(idx, clustersz);
30
}
27
}
31
28
32
+static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
29
void SetRoundingMode(const unsigned int opcode)
33
+{
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
34
+ char *nodename;
31
index XXXXXXX..XXXXXXX 100644
35
+
32
--- a/target/arm/cpu.c
36
+ nodename = g_strdup_printf("/intc");
33
+++ b/target/arm/cpu.c
37
+ qemu_fdt_add_subnode(sms->fdt, nodename);
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
38
+ qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
35
* the pseudocode function the arguments are in the order c, a, b.
39
+ 2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
40
+ 2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
37
* and the input NaN if it is signalling
41
+ 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
38
+ * * Default NaN has sign bit clear, msb frac bit set
42
+ 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
39
*/
43
+
40
static void arm_set_default_fp_behaviours(float_status *s)
44
+ g_free(nodename);
41
{
45
+}
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
46
/*
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
47
* Firmware on this machine only uses ACPI table to load OS, these limited
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
48
* device tree nodes are just to let firmware know the info which varies from
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
49
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
46
+ set_float_default_nan_pattern(0b01000000, s);
50
* fw compatibility.
51
*/
52
qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
53
- qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
54
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1);
55
56
if (ms->numa_state->have_numa_distance) {
57
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
58
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
59
60
g_free(nodename);
61
}
62
+
63
+ sbsa_fdt_add_gic_node(sms);
64
}
47
}
65
48
66
#define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
67
--
50
--
68
2.34.1
51
2.34.1
diff view generated by jsdifflib
New patch
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for loongarch.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/fpu_helper.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
int ieee_ex_to_loongarch(int xcpt)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/mips/fpu_helper.h
17
+++ b/target/mips/fpu_helper.h
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
22
+ /*
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
+ * frac bits except the msb are set.
26
+ */
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
28
+ &env->active_fpu.fp_status);
29
30
}
31
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/mips/msa.c
35
+++ b/target/mips/msa.c
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
37
/* Inf * 0 + NaN returns the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
39
&env->active_tc.msa_fp_status);
40
+ /* Default NaN: sign bit clear, frac msb set */
41
+ set_float_default_nan_pattern(0b01000000,
42
+ &env->active_tc.msa_fp_status);
43
}
44
--
45
2.34.1
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for ppc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
6
---
7
target/ppc/cpu_init.c | 4 ++++
8
1 file changed, 4 insertions(+)
9
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/ppc/cpu_init.c
13
+++ b/target/ppc/cpu_init.c
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
17
18
+ /* Default NaN: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
21
+
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
23
ppc_spr_t *spr = &env->spr_cb[i];
24
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sh4/cpu.c
15
+++ b/target/sh4/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
17
set_flush_to_zero(1, &env->fp_status);
18
#endif
19
set_default_nan_mode(1, &env->fp_status);
20
+ /* sign bit clear, set all frac bits other than msb */
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
22
}
23
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for rx.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
6
---
7
target/rx/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/rx/cpu.c
13
+++ b/target/rx/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for xtensa.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
6
---
7
target/xtensa/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/xtensa/cpu.c
13
+++ b/target/xtensa/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
15
/* For inf * 0 + NaN, return the input NaN */
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_no_signaling_nans(!dfpu, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
xtensa_use_first_nan(env, !dfpu);
21
}
22
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
8
---
9
target/hexagon/cpu.c | 2 ++
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
12
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/hexagon/cpu.c
16
+++ b/target/hexagon/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
18
19
set_default_nan_mode(1, &env->fp_status);
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
21
+ /* Default NaN value: sign bit set, all frac bits set */
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
23
}
24
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
27
index XXXXXXX..XXXXXXX 100644
28
--- a/fpu/softfloat-specialize.c.inc
29
+++ b/fpu/softfloat-specialize.c.inc
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
31
uint8_t dnan_pattern = status->default_nan_pattern;
32
33
if (dnan_pattern == 0) {
34
-#if defined(TARGET_HEXAGON)
35
- /* Sign bit set, all frac bits set. */
36
- dnan_pattern = 0b11111111;
37
-#else
38
/*
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
42
/* sign bit clear, set frac msb */
43
dnan_pattern = 0b01000000;
44
}
45
-#endif
46
}
47
assert(dnan_pattern != 0);
48
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for riscv.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu.c
13
+++ b/target/riscv/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
15
cs->exception_index = RISCV_EXCP_NONE;
16
env->load_res = -1;
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
env->vill = true;
21
22
#ifndef CONFIG_USER_ONLY
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for tricore.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
6
---
7
target/tricore/helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/tricore/helper.c
13
+++ b/target/tricore/helper.c
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
15
set_flush_to_zero(1, &env->fp_status);
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
uint32_t psw_read(CPUTriCoreState *env)
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 15/21] target/arm: Explicitly select short-format FSR for M-profile
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
For M-profile, there is no guest-facing A-profile format FSR, but we
1
Now that all our targets have bene converted to explicitly specify
2
still use the env->exception.fsr field to pass fault information from
2
their pattern for the default NaN value we can remove the remaining
3
the point where a fault is raised to the code in
3
fallback code in parts64_default_nan().
4
arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile
5
specific fault status registers. So it doesn't matter whether we
6
fill in env->exception.fsr in the short format or the LPAE format, as
7
long as both sides agree. As it happens arm_v7m_cpu_do_interrupt()
8
assumes short-form.
9
4
10
In compute_fsr_fsc() we weren't explicitly choosing short-form for
11
M-profile, but instead relied on it falling out in the wash because
12
arm_s1_regime_using_lpae_format() would be false. This was broken in
13
commit 452c67a4 when we added v8R support, because we said "PMSAv8 is
14
always LPAE format" (as it is for v8R), forgetting that we were
15
implicitly using this code path on M-profile. At that point we would
16
hit a g_assert_not_reached():
17
ERROR:../../target/arm/internals.h:549:arm_fi_to_lfsc: code should not be reached
18
19
#7 0x0000555555e055f7 in arm_fi_to_lfsc (fi=0x7fffecff9a90) at ../../target/arm/internals.h:549
20
#8 0x0000555555e05a27 in compute_fsr_fsc (env=0x555557356670, fi=0x7fffecff9a90, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff9a1c)
21
at ../../target/arm/tlb_helper.c:95
22
#9 0x0000555555e05b62 in arm_deliver_fault (cpu=0x555557354800, addr=268961344, access_type=MMU_INST_FETCH, mmu_idx=1, fi=0x7fffecff9a90)
23
at ../../target/arm/tlb_helper.c:132
24
#10 0x0000555555e06095 in arm_cpu_tlb_fill (cs=0x555557354800, address=268961344, size=1, access_type=MMU_INST_FETCH, mmu_idx=1, probe=false, retaddr=0)
25
at ../../target/arm/tlb_helper.c:260
26
27
The specific assertion changed when commit fcc7404eff24b4c added
28
"assert not M-profile" to arm_is_secure_below_el3(), because the
29
conditions being checked in compute_fsr_fsc() include
30
arm_el_is_aa64(), which will end up calling arm_is_secure_below_el3()
31
and asserting before we try to call arm_fi_to_lfsc():
32
33
#7 0x0000555555efaf43 in arm_is_secure_below_el3 (env=0x5555574665a0) at ../../target/arm/cpu.h:2396
34
#8 0x0000555555efb103 in arm_is_el2_enabled (env=0x5555574665a0) at ../../target/arm/cpu.h:2448
35
#9 0x0000555555efb204 in arm_el_is_aa64 (env=0x5555574665a0, el=1) at ../../target/arm/cpu.h:2509
36
#10 0x0000555555efbdfd in compute_fsr_fsc (env=0x5555574665a0, fi=0x7fffecff99e0, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff996c)
37
38
Avoid the assertion and the incorrect FSR format selection by
39
explicitly making M-profile use the short-format in this function.
40
41
Fixes: 452c67a42704 ("target/arm: Enable TTBCR_EAE for ARMv8-R AArch32")a
42
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1658
43
Cc: qemu-stable@nongnu.org
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
45
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
46
Message-id: 20230523131726.866635-1-peter.maydell@linaro.org
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
47
---
8
---
48
target/arm/tcg/tlb_helper.c | 13 +++++++++++--
9
fpu/softfloat-specialize.c.inc | 14 --------------
49
1 file changed, 11 insertions(+), 2 deletions(-)
10
1 file changed, 14 deletions(-)
50
11
51
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
52
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/tcg/tlb_helper.c
14
--- a/fpu/softfloat-specialize.c.inc
54
+++ b/target/arm/tcg/tlb_helper.c
15
+++ b/fpu/softfloat-specialize.c.inc
55
@@ -XXX,XX +XXX,XX @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
56
ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
17
uint64_t frac;
57
uint32_t fsr, fsc;
18
uint8_t dnan_pattern = status->default_nan_pattern;
58
19
59
- if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
20
- if (dnan_pattern == 0) {
60
- arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
21
- /*
61
+ /*
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
62
+ * For M-profile there is no guest-facing FSR. We compute a
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
63
+ * short-form value for env->exception.fsr which we will then
24
- * do not have floating-point.
64
+ * examine in arm_v7m_cpu_do_interrupt(). In theory we could
25
- */
65
+ * use the LPAE format instead as long as both bits of code agree
26
- if (snan_bit_is_one(status)) {
66
+ * (and arm_fi_to_lfsc() handled the M-profile specific
27
- /* sign bit clear, set all frac bits other than msb */
67
+ * ARMFault_QEMU_NSCExec and ARMFault_QEMU_SFault cases).
28
- dnan_pattern = 0b00111111;
68
+ */
29
- } else {
69
+ if (!arm_feature(env, ARM_FEATURE_M) &&
30
- /* sign bit clear, set frac msb */
70
+ (target_el == 2 || arm_el_is_aa64(env, target_el) ||
31
- dnan_pattern = 0b01000000;
71
+ arm_s1_regime_using_lpae_format(env, arm_mmu_idx))) {
32
- }
72
/*
33
- }
73
* LPAE format fault status register : bottom 6 bits are
34
assert(dnan_pattern != 0);
74
* status code in the same form as needed for syndrome
35
36
sign = dnan_pattern >> 7;
75
--
37
--
76
2.34.1
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
14
2 files changed, 40 insertions(+), 55 deletions(-)
15
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
--- a/fpu/softfloat-parts.c.inc
19
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
21
}
22
23
if (s->default_nan_mode) {
24
+ /*
25
+ * We guarantee not to require the target to tell us how to
26
+ * pick a NaN if we're always returning the default NaN.
27
+ * But if we're not in default-NaN mode then the target must
28
+ * specify.
29
+ */
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
67
}
68
69
if (which == 3) {
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
71
index XXXXXXX..XXXXXXX 100644
72
--- a/fpu/softfloat-specialize.c.inc
73
+++ b/fpu/softfloat-specialize.c.inc
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
75
}
76
}
77
78
-/*----------------------------------------------------------------------------
79
-| Select which NaN to propagate for a three-input operation.
80
-| For the moment we assume that no CPU needs the 'larger significand'
81
-| information.
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
83
-*----------------------------------------------------------------------------*/
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
86
-{
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
89
- int which;
90
-
91
- /*
92
- * We guarantee not to require the target to tell us how to
93
- * pick a NaN if we're always returning the default NaN.
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
96
- */
97
- assert(!status->default_nan_mode);
98
-
99
- if (infzero) {
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
114
- }
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
130
-}
131
-
132
/*----------------------------------------------------------------------------
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
134
| NaN; otherwise returns 0.
135
--
136
2.34.1
137
138
diff view generated by jsdifflib
[PULL 04/21] hw/arm/smmuv3: Refactor stage-1 PTW
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Mostafa Saleh <smostafa@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In preparation for adding stage-2 support, rename smmu_ptw_64 to
3
Remove "3" as a special case for which and simply
4
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
4
branch to return the desired value.
5
stage-2 page table walk.
6
5
7
Remove AA64 check from PTW as decode_cd already ensures that AA64 is
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
used, otherwise it faults with C_BAD_CD.
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
10
A stage member is added to SMMUPTWEventInfo to differentiate
11
between stage-1 and stage-2 ptw faults.
12
13
Add stage argument to trace_smmu_ptw_level be consistent with other
14
trace events.
15
16
Signed-off-by: Mostafa Saleh <smostafa@google.com>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Tested-by: Eric Auger <eric.auger@redhat.com>
19
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
20
Message-id: 20230516203327.2051088-4-smostafa@google.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
10
---
23
include/hw/arm/smmu-common.h | 16 +++++++++++++---
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
24
hw/arm/smmu-common.c | 27 ++++++++++-----------------
12
1 file changed, 10 insertions(+), 10 deletions(-)
25
hw/arm/smmuv3.c | 2 ++
26
hw/arm/trace-events | 2 +-
27
4 files changed, 26 insertions(+), 21 deletions(-)
28
13
29
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
30
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/arm/smmu-common.h
16
--- a/fpu/softfloat-parts.c.inc
32
+++ b/include/hw/arm/smmu-common.h
17
+++ b/fpu/softfloat-parts.c.inc
33
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
34
#include "hw/pci/pci.h"
19
* But if we're not in default-NaN mode then the target must
35
#include "qom/object.h"
20
* specify.
36
21
*/
37
-#define SMMU_PCI_BUS_MAX 256
22
- which = 3;
38
-#define SMMU_PCI_DEVFN_MAX 256
23
+ goto default_nan;
39
-#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
24
} else if (infzero) {
40
+#define SMMU_PCI_BUS_MAX 256
25
/*
41
+#define SMMU_PCI_DEVFN_MAX 256
26
* Inf * 0 + NaN -- some implementations return the
42
+#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
43
+
28
*/
44
+/* VMSAv8-64 Translation constants and functions */
29
switch (s->float_infzeronan_rule) {
45
+#define VMSA_LEVELS 4
30
case float_infzeronan_dnan_never:
46
+
31
- which = 2;
47
+#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1)
32
break;
48
+#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \
33
case float_infzeronan_dnan_always:
49
+ (VMSA_LEVELS - (lvl)))
34
- which = 3;
50
+#define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \
35
- break;
51
+ VMSA_BIT_LVL(isz, strd, lvl)) - 1)
36
+ goto default_nan;
52
37
case float_infzeronan_dnan_if_qnan:
53
/*
38
- which = is_qnan(c->cls) ? 3 : 2;
54
* Page table walk error types
39
+ if (is_qnan(c->cls)) {
55
@@ -XXX,XX +XXX,XX @@ typedef enum {
40
+ goto default_nan;
56
} SMMUPTWEventType;
41
+ }
57
42
break;
58
typedef struct SMMUPTWEventInfo {
43
default:
59
+ int stage;
44
g_assert_not_reached();
60
SMMUPTWEventType type;
45
}
61
dma_addr_t addr; /* fetched address that induced an abort, if any */
46
+ which = 2;
62
} SMMUPTWEventInfo;
47
} else {
63
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
64
index XXXXXXX..XXXXXXX 100644
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
65
--- a/hw/arm/smmu-common.c
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
66
+++ b/hw/arm/smmu-common.c
51
}
67
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
68
}
69
70
/**
71
- * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
72
+ * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA
73
* @cfg: translation config
74
* @iova: iova to translate
75
* @perm: access type
76
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
77
* Upon success, @tlbe is filled with translated_addr and entry
78
* permission rights.
79
*/
80
-static int smmu_ptw_64(SMMUTransCfg *cfg,
81
- dma_addr_t iova, IOMMUAccessFlags perm,
82
- SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
83
+static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
84
+ dma_addr_t iova, IOMMUAccessFlags perm,
85
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
86
{
87
dma_addr_t baseaddr, indexmask;
88
int stage = cfg->stage;
89
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
90
}
52
}
91
53
92
granule_sz = tt->granule_sz;
54
- if (which == 3) {
93
- stride = granule_sz - 3;
55
- parts_default_nan(a, s);
94
+ stride = VMSA_STRIDE(granule_sz);
56
- return a;
95
inputsize = 64 - tt->tsz;
96
level = 4 - (inputsize - 4) / stride;
97
- indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
98
+ indexmask = VMSA_IDXMSK(inputsize, stride, level);
99
baseaddr = extract64(tt->ttb, 0, 48);
100
baseaddr &= ~indexmask;
101
102
- while (level <= 3) {
103
+ while (level < VMSA_LEVELS) {
104
uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
105
uint64_t mask = subpage_size - 1;
106
uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);
107
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
108
if (get_pte(baseaddr, offset, &pte, info)) {
109
goto error;
110
}
111
- trace_smmu_ptw_level(level, iova, subpage_size,
112
+ trace_smmu_ptw_level(stage, level, iova, subpage_size,
113
baseaddr, offset, pte);
114
115
if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
116
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
117
info->type = SMMU_PTW_ERR_TRANSLATION;
118
119
error:
120
+ info->stage = 1;
121
tlbe->entry.perm = IOMMU_NONE;
122
return -EINVAL;
123
}
124
@@ -XXX,XX +XXX,XX @@ error:
125
int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
126
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
127
{
128
- if (!cfg->aa64) {
129
- /*
130
- * This code path is not entered as we check this while decoding
131
- * the configuration data in the derived SMMU model.
132
- */
133
- g_assert_not_reached();
134
- }
57
- }
135
-
58
-
136
- return smmu_ptw_64(cfg, iova, perm, tlbe, info);
59
switch (which) {
137
+ return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
60
case 0:
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
66
+
67
+ default_nan:
68
+ parts_default_nan(a, s);
69
+ return a;
138
}
70
}
139
71
140
/**
72
/*
141
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
142
index XXXXXXX..XXXXXXX 100644
143
--- a/hw/arm/smmuv3.c
144
+++ b/hw/arm/smmuv3.c
145
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
146
cached_entry = g_new0(SMMUTLBEntry, 1);
147
148
if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {
149
+ /* All faults from PTW has S2 field. */
150
+ event.u.f_walk_eabt.s2 = (ptw_info.stage == 2);
151
g_free(cached_entry);
152
switch (ptw_info.type) {
153
case SMMU_PTW_ERR_WALK_EABT:
154
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
155
index XXXXXXX..XXXXXXX 100644
156
--- a/hw/arm/trace-events
157
+++ b/hw/arm/trace-events
158
@@ -XXX,XX +XXX,XX @@ virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
159
160
# smmu-common.c
161
smmu_add_mr(const char *name) "%s"
162
-smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
163
+smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
164
smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64
165
smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
166
smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
167
--
73
--
168
2.34.1
74
2.34.1
75
76
diff view generated by jsdifflib
[PULL 12/21] hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Tommy Wu <tommy.wu@sifive.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When we receive a packet from the xilinx_axienet and then try to s2mem
3
Assign the pointer return value to 'a' directly,
4
through the xilinx_axidma, if the descriptor ring buffer is full in the
4
rather than going through an intermediary index.
5
xilinx axidma driver, we’ll assert the DMASR.HALTED in the
6
function : stream_process_s2mem and return 0. In the end, we’ll be stuck in
7
an infinite loop in axienet_eth_rx_notify.
8
5
9
This patch checks the DMASR.HALTED state when we try to push data
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted,
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
we will not keep pushing the data and then prevent the infinte loop.
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
12
13
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
14
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
15
Reviewed-by: Frank Chang <frank.chang@sifive.com>
16
Message-id: 20230519062137.1251741-1-tommy.wu@sifive.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
10
---
19
hw/dma/xilinx_axidma.c | 11 ++++++++---
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
20
1 file changed, 8 insertions(+), 3 deletions(-)
12
1 file changed, 10 insertions(+), 22 deletions(-)
21
13
22
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
23
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/dma/xilinx_axidma.c
16
--- a/fpu/softfloat-parts.c.inc
25
+++ b/hw/dma/xilinx_axidma.c
17
+++ b/fpu/softfloat-parts.c.inc
26
@@ -XXX,XX +XXX,XX @@ static inline int stream_idle(struct Stream *s)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
27
return !!(s->regs[R_DMASR] & DMASR_IDLE);
19
FloatPartsN *c, float_status *s,
28
}
20
int ab_mask, int abc_mask)
29
30
+static inline int stream_halted(struct Stream *s)
31
+{
32
+ return !!(s->regs[R_DMASR] & DMASR_HALTED);
33
+}
34
+
35
static void stream_reset(struct Stream *s)
36
{
21
{
37
s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
22
- int which;
38
@@ -XXX,XX +XXX,XX @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
23
bool infzero = (ab_mask == float_cmask_infzero);
39
uint64_t addr;
24
bool have_snan = (abc_mask & float_cmask_snan);
40
bool eop;
25
+ FloatPartsN *ret;
41
26
42
- if (!stream_running(s) || stream_idle(s)) {
27
if (unlikely(have_snan)) {
43
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
44
return;
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
default:
31
g_assert_not_reached();
32
}
33
- which = 2;
34
+ ret = c;
35
} else {
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
37
+ FloatPartsN *val[3] = { a, b, c };
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
56
}
45
}
57
}
46
58
47
@@ -XXX,XX +XXX,XX @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
59
- switch (which) {
48
unsigned int rxlen;
60
- case 0:
49
size_t pos = 0;
61
- break;
50
62
- case 1:
51
- if (!stream_running(s) || stream_idle(s)) {
63
- a = b;
52
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
64
- break;
53
return 0;
65
- case 2:
66
- a = c;
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
54
}
72
}
55
73
- if (is_snan(a->cls)) {
56
@@ -XXX,XX +XXX,XX @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
74
- parts_silence_nan(a, s);
57
XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
75
- }
58
struct Stream *s = &ds->dma->streams[1];
76
- return a;
59
77
+ return ret;
60
- if (!stream_running(s) || stream_idle(s)) {
78
61
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
79
default_nan:
62
ds->dma->notify = notify;
80
parts_default_nan(a, s);
63
ds->dma->notify_opaque = notify_opaque;
64
return false;
65
--
81
--
66
2.34.1
82
2.34.1
67
83
68
84
diff view generated by jsdifflib
[PULL 13/21] hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Clément Chigot <chigot@adacore.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS,
3
While all indices into val[] should be in [0-2], the mask
4
the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result
4
applied is two bits. To help static analysis see there is
5
in a positive number as ms->smp.cpus is a unsigned int.
5
no possibility of read beyond the end of the array, pad the
6
This will raise the following error afterwards, as Qemu will try to
6
array to 4 entries, with the final being (implicitly) NULL.
7
instantiate some additional RPUs.
8
| $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102
9
| **
10
| ERROR:../src/tcg/tcg.c:777:tcg_register_thread:
11
| assertion failed: (n < tcg_max_ctxs)
12
7
13
Signed-off-by: Clément Chigot <chigot@adacore.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
16
Message-id: 20230524143714.565792-1-chigot@adacore.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
12
---
19
hw/arm/xlnx-zynqmp.c | 2 +-
13
fpu/softfloat-parts.c.inc | 2 +-
20
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
21
15
22
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
23
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/xlnx-zynqmp.c
18
--- a/fpu/softfloat-parts.c.inc
25
+++ b/hw/arm/xlnx-zynqmp.c
19
+++ b/fpu/softfloat-parts.c.inc
26
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
27
const char *boot_cpu, Error **errp)
21
}
28
{
22
ret = c;
29
int i;
23
} else {
30
- int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
24
- FloatPartsN *val[3] = { a, b, c };
31
+ int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
32
XLNX_ZYNQMP_NUM_RPU_CPUS);
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
33
27
34
if (num_rpus <= 0) {
28
assert(rule != float_3nan_prop_none);
35
--
29
--
36
2.34.1
30
2.34.1
37
31
38
32
diff view generated by jsdifflib
[PULL 06/21] hw/arm/smmuv3: Parse STE config for stage-2
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Mostafa Saleh <smostafa@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
3
This function is part of the public interface and
4
Validity of field values are checked when possible.
4
is not "specialized" to any target in any way.
5
5
6
Only AA64 tables are supported and Small Translation Tables (STT) are
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
not supported.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
9
According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
10
with an S2 prefix (with the exception of S2VMID) are IGNORED when
11
stage-2 bypasses translation (Config[1] == 0).
12
13
Which means that VMID can be used(for TLB tagging) even if stage-2 is
14
bypassed, so we parse it unconditionally when S2P exists. Otherwise
15
it is set to -1.(only S1P)
16
17
As stall is not supported, if S2S is set the translation would abort.
18
For S2R, we reuse the same code used for stage-1 with flag
19
record_faults. However when nested translation is supported we would
20
need to separate stage-1 and stage-2 faults.
21
22
Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S.
23
24
Signed-off-by: Mostafa Saleh <smostafa@google.com>
25
Tested-by: Eric Auger <eric.auger@redhat.com>
26
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
27
Reviewed-by: Eric Auger <eric.auger@redhat.com>
28
Message-id: 20230516203327.2051088-6-smostafa@google.com
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
10
---
31
hw/arm/smmuv3-internal.h | 10 +-
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
32
include/hw/arm/smmu-common.h | 1 +
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
33
include/hw/arm/smmuv3.h | 3 +
13
2 files changed, 52 insertions(+), 52 deletions(-)
34
hw/arm/smmuv3.c | 181 +++++++++++++++++++++++++++++++++--
35
4 files changed, 185 insertions(+), 10 deletions(-)
36
14
37
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
38
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/smmuv3-internal.h
17
--- a/fpu/softfloat.c
40
+++ b/hw/arm/smmuv3-internal.h
18
+++ b/fpu/softfloat.c
41
@@ -XXX,XX +XXX,XX @@ typedef struct CD {
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
42
#define STE_S2TG(x) extract32((x)->word[5], 14, 2)
20
*zExpPtr = 1 - shiftCount;
43
#define STE_S2PS(x) extract32((x)->word[5], 16, 3)
21
}
44
#define STE_S2AA64(x) extract32((x)->word[5], 19, 1)
22
45
-#define STE_S2HD(x) extract32((x)->word[5], 24, 1)
23
+/*----------------------------------------------------------------------------
46
-#define STE_S2HA(x) extract32((x)->word[5], 25, 1)
24
+| Takes two extended double-precision floating-point values `a' and `b', one
47
-#define STE_S2S(x) extract32((x)->word[5], 26, 1)
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
48
+#define STE_S2ENDI(x) extract32((x)->word[5], 20, 1)
26
+| `b' is a signaling NaN, the invalid exception is raised.
49
+#define STE_S2AFFD(x) extract32((x)->word[5], 21, 1)
27
+*----------------------------------------------------------------------------*/
50
+#define STE_S2HD(x) extract32((x)->word[5], 23, 1)
51
+#define STE_S2HA(x) extract32((x)->word[5], 24, 1)
52
+#define STE_S2S(x) extract32((x)->word[5], 25, 1)
53
+#define STE_S2R(x) extract32((x)->word[5], 26, 1)
54
+
28
+
55
#define STE_CTXPTR(x) \
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
56
({ \
30
+{
57
unsigned long addr; \
31
+ bool aIsLargerSignificand;
58
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
32
+ FloatClass a_cls, b_cls;
59
index XXXXXXX..XXXXXXX 100644
60
--- a/include/hw/arm/smmu-common.h
61
+++ b/include/hw/arm/smmu-common.h
62
@@ -XXX,XX +XXX,XX @@
63
64
/* VMSAv8-64 Translation constants and functions */
65
#define VMSA_LEVELS 4
66
+#define VMSA_MAX_S2_CONCAT 16
67
68
#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1)
69
#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \
70
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/hw/arm/smmuv3.h
73
+++ b/include/hw/arm/smmuv3.h
74
@@ -XXX,XX +XXX,XX @@ struct SMMUv3Class {
75
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
76
OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
77
78
+#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P)
79
+#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P)
80
+
33
+
81
#endif
34
+ /* This is not complete, but is good enough for pickNaN. */
82
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
35
+ a_cls = (!floatx80_is_any_nan(a)
83
index XXXXXXX..XXXXXXX 100644
36
+ ? float_class_normal
84
--- a/hw/arm/smmuv3.c
37
+ : floatx80_is_signaling_nan(a, status)
85
+++ b/hw/arm/smmuv3.c
38
+ ? float_class_snan
86
@@ -XXX,XX +XXX,XX @@
39
+ : float_class_qnan);
87
#include "smmuv3-internal.h"
40
+ b_cls = (!floatx80_is_any_nan(b)
88
#include "smmu-internal.h"
41
+ ? float_class_normal
89
42
+ : floatx80_is_signaling_nan(b, status)
90
+#define PTW_RECORD_FAULT(cfg) (((cfg)->stage == 1) ? (cfg)->record_faults : \
43
+ ? float_class_snan
91
+ (cfg)->s2cfg.record_faults)
44
+ : float_class_qnan);
92
+
45
+
93
/**
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
94
* smmuv3_trigger_irq - pulse @irq if enabled and update
47
+ float_raise(float_flag_invalid, status);
95
* GERROR register in case of GERROR interrupt
96
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
97
return 0;
98
}
99
100
+/*
101
+ * Max valid value is 39 when SMMU_IDR3.STT == 0.
102
+ * In architectures after SMMUv3.0:
103
+ * - If STE.S2TG selects a 4KB or 16KB granule, the minimum valid value for this
104
+ * field is MAX(16, 64-IAS)
105
+ * - If STE.S2TG selects a 64KB granule, the minimum valid value for this field
106
+ * is (64-IAS).
107
+ * As we only support AA64, IAS = OAS.
108
+ */
109
+static bool s2t0sz_valid(SMMUTransCfg *cfg)
110
+{
111
+ if (cfg->s2cfg.tsz > 39) {
112
+ return false;
113
+ }
48
+ }
114
+
49
+
115
+ if (cfg->s2cfg.granule_sz == 16) {
50
+ if (status->default_nan_mode) {
116
+ return (cfg->s2cfg.tsz >= 64 - oas2bits(SMMU_IDR5_OAS));
51
+ return floatx80_default_nan(status);
117
+ }
52
+ }
118
+
53
+
119
+ return (cfg->s2cfg.tsz >= MAX(64 - oas2bits(SMMU_IDR5_OAS), 16));
54
+ if (a.low < b.low) {
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
61
+
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
63
+ if (is_snan(b_cls)) {
64
+ return floatx80_silence_nan(b, status);
65
+ }
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
72
+ }
120
+}
73
+}
121
+
74
+
122
+/*
75
/*----------------------------------------------------------------------------
123
+ * Return true if s2 page table config is valid.
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
124
+ * This checks with the configured start level, ias_bits and granularity we can
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
125
+ * have a valid page table as described in ARM ARM D8.2 Translation process.
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
126
+ * The idea here is to see for the highest possible number of IPA bits, how
79
index XXXXXXX..XXXXXXX 100644
127
+ * many concatenated tables we would need, if it is more than 16, then this is
80
--- a/fpu/softfloat-specialize.c.inc
128
+ * not possible.
81
+++ b/fpu/softfloat-specialize.c.inc
129
+ */
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
130
+static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gran)
83
return a;
131
+{
84
}
132
+ int level = get_start_level(sl0, gran);
85
133
+ uint64_t ipa_bits = 64 - t0sz;
86
-/*----------------------------------------------------------------------------
134
+ uint64_t max_ipa = (1ULL << ipa_bits) - 1;
87
-| Takes two extended double-precision floating-point values `a' and `b', one
135
+ int nr_concat = pgd_concat_idx(level, gran, max_ipa) + 1;
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
136
+
89
-| `b' is a signaling NaN, the invalid exception is raised.
137
+ return nr_concat <= VMSA_MAX_S2_CONCAT;
90
-*----------------------------------------------------------------------------*/
138
+}
91
-
139
+
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
140
+static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
93
-{
141
+{
94
- bool aIsLargerSignificand;
142
+ cfg->stage = 2;
95
- FloatClass a_cls, b_cls;
143
+
96
-
144
+ if (STE_S2AA64(ste) == 0x0) {
97
- /* This is not complete, but is good enough for pickNaN. */
145
+ qemu_log_mask(LOG_UNIMP,
98
- a_cls = (!floatx80_is_any_nan(a)
146
+ "SMMUv3 AArch32 tables not supported\n");
99
- ? float_class_normal
147
+ g_assert_not_reached();
100
- : floatx80_is_signaling_nan(a, status)
148
+ }
101
- ? float_class_snan
149
+
102
- : float_class_qnan);
150
+ switch (STE_S2TG(ste)) {
103
- b_cls = (!floatx80_is_any_nan(b)
151
+ case 0x0: /* 4KB */
104
- ? float_class_normal
152
+ cfg->s2cfg.granule_sz = 12;
105
- : floatx80_is_signaling_nan(b, status)
153
+ break;
106
- ? float_class_snan
154
+ case 0x1: /* 64KB */
107
- : float_class_qnan);
155
+ cfg->s2cfg.granule_sz = 16;
108
-
156
+ break;
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
157
+ case 0x2: /* 16KB */
110
- float_raise(float_flag_invalid, status);
158
+ cfg->s2cfg.granule_sz = 14;
111
- }
159
+ break;
112
-
160
+ default:
113
- if (status->default_nan_mode) {
161
+ qemu_log_mask(LOG_GUEST_ERROR,
114
- return floatx80_default_nan(status);
162
+ "SMMUv3 bad STE S2TG: %x\n", STE_S2TG(ste));
115
- }
163
+ goto bad_ste;
116
-
164
+ }
117
- if (a.low < b.low) {
165
+
118
- aIsLargerSignificand = 0;
166
+ cfg->s2cfg.vttb = STE_S2TTB(ste);
119
- } else if (b.low < a.low) {
167
+
120
- aIsLargerSignificand = 1;
168
+ cfg->s2cfg.sl0 = STE_S2SL0(ste);
121
- } else {
169
+ /* FEAT_TTST not supported. */
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
170
+ if (cfg->s2cfg.sl0 == 0x3) {
123
- }
171
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 S2SL0 = 0x3 has no meaning!\n");
124
-
172
+ goto bad_ste;
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
173
+ }
126
- if (is_snan(b_cls)) {
174
+
127
- return floatx80_silence_nan(b, status);
175
+ /* For AA64, The effective S2PS size is capped to the OAS. */
128
- }
176
+ cfg->s2cfg.eff_ps = oas2bits(MIN(STE_S2PS(ste), SMMU_IDR5_OAS));
129
- return b;
177
+ /*
130
- } else {
178
+ * It is ILLEGAL for the address in S2TTB to be outside the range
131
- if (is_snan(a_cls)) {
179
+ * described by the effective S2PS value.
132
- return floatx80_silence_nan(a, status);
180
+ */
133
- }
181
+ if (cfg->s2cfg.vttb & ~(MAKE_64BIT_MASK(0, cfg->s2cfg.eff_ps))) {
134
- return a;
182
+ qemu_log_mask(LOG_GUEST_ERROR,
135
- }
183
+ "SMMUv3 S2TTB too large 0x%lx, effective PS %d bits\n",
136
-}
184
+ cfg->s2cfg.vttb, cfg->s2cfg.eff_ps);
137
-
185
+ goto bad_ste;
138
/*----------------------------------------------------------------------------
186
+ }
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
187
+
140
| NaN; otherwise returns 0.
188
+ cfg->s2cfg.tsz = STE_S2T0SZ(ste);
189
+
190
+ if (!s2t0sz_valid(cfg)) {
191
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 bad STE S2T0SZ = %d\n",
192
+ cfg->s2cfg.tsz);
193
+ goto bad_ste;
194
+ }
195
+
196
+ if (!s2_pgtable_config_valid(cfg->s2cfg.sl0, cfg->s2cfg.tsz,
197
+ cfg->s2cfg.granule_sz)) {
198
+ qemu_log_mask(LOG_GUEST_ERROR,
199
+ "SMMUv3 STE stage 2 config not valid!\n");
200
+ goto bad_ste;
201
+ }
202
+
203
+ /* Only LE supported(IDR0.TTENDIAN). */
204
+ if (STE_S2ENDI(ste)) {
205
+ qemu_log_mask(LOG_GUEST_ERROR,
206
+ "SMMUv3 STE_S2ENDI only supports LE!\n");
207
+ goto bad_ste;
208
+ }
209
+
210
+ cfg->s2cfg.affd = STE_S2AFFD(ste);
211
+
212
+ cfg->s2cfg.record_faults = STE_S2R(ste);
213
+ /* As stall is not supported. */
214
+ if (STE_S2S(ste)) {
215
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 Stall not implemented!\n");
216
+ goto bad_ste;
217
+ }
218
+
219
+ /* This is still here as stage 2 has not been fully enabled yet. */
220
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
221
+ goto bad_ste;
222
+
223
+ return 0;
224
+
225
+bad_ste:
226
+ return -EINVAL;
227
+}
228
+
229
/* Returns < 0 in case of invalid STE, 0 otherwise */
230
static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
231
STE *ste, SMMUEventInfo *event)
232
{
233
uint32_t config;
234
+ int ret;
235
236
if (!STE_VALID(ste)) {
237
if (!event->inval_ste_allowed) {
238
@@ -XXX,XX +XXX,XX @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
239
return 0;
240
}
241
242
- if (STE_CFG_S2_ENABLED(config)) {
243
- qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
244
+ /*
245
+ * If a stage is enabled in SW while not advertised, throw bad ste
246
+ * according to user manual(IHI0070E) "5.2 Stream Table Entry".
247
+ */
248
+ if (!STAGE1_SUPPORTED(s) && STE_CFG_S1_ENABLED(config)) {
249
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S1 used but not supported.\n");
250
goto bad_ste;
251
}
252
+ if (!STAGE2_SUPPORTED(s) && STE_CFG_S2_ENABLED(config)) {
253
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S2 used but not supported.\n");
254
+ goto bad_ste;
255
+ }
256
+
257
+ if (STAGE2_SUPPORTED(s)) {
258
+ /* VMID is considered even if s2 is disabled. */
259
+ cfg->s2cfg.vmid = STE_S2VMID(ste);
260
+ } else {
261
+ /* Default to -1 */
262
+ cfg->s2cfg.vmid = -1;
263
+ }
264
+
265
+ if (STE_CFG_S2_ENABLED(config)) {
266
+ /*
267
+ * Stage-1 OAS defaults to OAS even if not enabled as it would be used
268
+ * in input address check for stage-2.
269
+ */
270
+ cfg->oas = oas2bits(SMMU_IDR5_OAS);
271
+ ret = decode_ste_s2_cfg(cfg, ste);
272
+ if (ret) {
273
+ goto bad_ste;
274
+ }
275
+ }
276
277
if (STE_S1CDMAX(ste) != 0) {
278
qemu_log_mask(LOG_UNIMP,
279
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
280
if (cached_entry) {
281
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
282
status = SMMU_TRANS_ERROR;
283
- if (cfg->record_faults) {
284
+ /*
285
+ * We know that the TLB only contains either stage-1 or stage-2 as
286
+ * nesting is not supported. So it is sufficient to check the
287
+ * translation stage to know the TLB stage for now.
288
+ */
289
+ event.u.f_walk_eabt.s2 = (cfg->stage == 2);
290
+ if (PTW_RECORD_FAULT(cfg)) {
291
event.type = SMMU_EVT_F_PERMISSION;
292
event.u.f_permission.addr = addr;
293
event.u.f_permission.rnw = flag & 0x1;
294
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
295
event.u.f_walk_eabt.addr2 = ptw_info.addr;
296
break;
297
case SMMU_PTW_ERR_TRANSLATION:
298
- if (cfg->record_faults) {
299
+ if (PTW_RECORD_FAULT(cfg)) {
300
event.type = SMMU_EVT_F_TRANSLATION;
301
event.u.f_translation.addr = addr;
302
event.u.f_translation.rnw = flag & 0x1;
303
}
304
break;
305
case SMMU_PTW_ERR_ADDR_SIZE:
306
- if (cfg->record_faults) {
307
+ if (PTW_RECORD_FAULT(cfg)) {
308
event.type = SMMU_EVT_F_ADDR_SIZE;
309
event.u.f_addr_size.addr = addr;
310
event.u.f_addr_size.rnw = flag & 0x1;
311
}
312
break;
313
case SMMU_PTW_ERR_ACCESS:
314
- if (cfg->record_faults) {
315
+ if (PTW_RECORD_FAULT(cfg)) {
316
event.type = SMMU_EVT_F_ACCESS;
317
event.u.f_access.addr = addr;
318
event.u.f_access.rnw = flag & 0x1;
319
}
320
break;
321
case SMMU_PTW_ERR_PERMISSION:
322
- if (cfg->record_faults) {
323
+ if (PTW_RECORD_FAULT(cfg)) {
324
event.type = SMMU_EVT_F_PERMISSION;
325
event.u.f_permission.addr = addr;
326
event.u.f_permission.rnw = flag & 0x1;
327
--
141
--
328
2.34.1
142
2.34.1
diff view generated by jsdifflib
[PULL 11/21] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Mostafa Saleh <smostafa@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
As everything is in place, we can use a new system property to
3
Unpacking and repacking the parts may be slightly more work
4
advertise which stage is supported and remove bad_ste from STE
4
than we did before, but we get to reuse more code. For a
5
stage2 config.
5
code path handling exceptional values, this is an improvement.
6
6
7
The property added arm-smmuv3.stage can have 3 values:
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
- "1": Stage-1 only is advertised.
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
- "2": Stage-2 only is advertised.
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
fpu/softfloat.c | 43 +++++--------------------------------------
13
1 file changed, 5 insertions(+), 38 deletions(-)
10
14
11
If not passed or an unsupported value is passed, it will default to
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
12
stage-1.
13
14
Advertise VMID16.
15
16
Don't try to decode CD, if stage-2 is configured.
17
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Signed-off-by: Mostafa Saleh <smostafa@google.com>
20
Tested-by: Eric Auger <eric.auger@redhat.com>
21
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
22
Message-id: 20230516203327.2051088-11-smostafa@google.com
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
include/hw/arm/smmuv3.h | 1 +
26
hw/arm/smmuv3.c | 32 ++++++++++++++++++++++----------
27
2 files changed, 23 insertions(+), 10 deletions(-)
28
29
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
30
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/arm/smmuv3.h
17
--- a/fpu/softfloat.c
32
+++ b/include/hw/arm/smmuv3.h
18
+++ b/fpu/softfloat.c
33
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
34
20
35
qemu_irq irq[4];
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
36
QemuMutex mutex;
37
+ char *stage;
38
};
39
40
typedef enum {
41
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/smmuv3.c
44
+++ b/hw/arm/smmuv3.c
45
@@ -XXX,XX +XXX,XX @@
46
#include "hw/irq.h"
47
#include "hw/sysbus.h"
48
#include "migration/vmstate.h"
49
+#include "hw/qdev-properties.h"
50
#include "hw/qdev-core.h"
51
#include "hw/pci/pci.h"
52
#include "cpu.h"
53
@@ -XXX,XX +XXX,XX @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)
54
55
static void smmuv3_init_regs(SMMUv3State *s)
56
{
22
{
57
- /**
23
- bool aIsLargerSignificand;
58
- * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
24
- FloatClass a_cls, b_cls;
59
- * multi-level stream table
25
+ FloatParts128 pa, pb, *pr;
60
- */
26
61
- s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */
27
- /* This is not complete, but is good enough for pickNaN. */
62
+ /* Based on sys property, the stages supported in smmu will be advertised.*/
28
- a_cls = (!floatx80_is_any_nan(a)
63
+ if (s->stage && !strcmp("2", s->stage)) {
29
- ? float_class_normal
64
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S2P, 1);
30
- : floatx80_is_signaling_nan(a, status)
65
+ } else {
31
- ? float_class_snan
66
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1);
32
- : float_class_qnan);
67
+ }
33
- b_cls = (!floatx80_is_any_nan(b)
68
+
34
- ? float_class_normal
69
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */
35
- : floatx80_is_signaling_nan(b, status)
70
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */
36
- ? float_class_snan
71
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */
37
- : float_class_qnan);
72
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */
38
-
73
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
74
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */
40
- float_raise(float_flag_invalid, status);
75
/* terminated transaction will always be aborted/error returned */
41
- }
76
@@ -XXX,XX +XXX,XX @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
42
-
77
goto bad_ste;
43
- if (status->default_nan_mode) {
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
78
}
47
}
79
48
80
- /* This is still here as stage 2 has not been fully enabled yet. */
49
- if (a.low < b.low) {
81
- qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
50
- aIsLargerSignificand = 0;
82
- goto bad_ste;
51
- } else if (b.low < a.low) {
52
- aIsLargerSignificand = 1;
53
- } else {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
55
- }
83
-
56
-
84
return 0;
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
85
58
- if (is_snan(b_cls)) {
86
bad_ste:
59
- return floatx80_silence_nan(b, status);
87
@@ -XXX,XX +XXX,XX @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
60
- }
88
return ret;
61
- return b;
89
}
62
- } else {
90
63
- if (is_snan(a_cls)) {
91
- if (cfg->aborted || cfg->bypassed) {
64
- return floatx80_silence_nan(a, status);
92
+ if (cfg->aborted || cfg->bypassed || (cfg->stage == 2)) {
65
- }
93
return 0;
66
- return a;
94
}
67
- }
95
68
+ pr = parts_pick_nan(&pa, &pb, status);
96
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
69
+ return floatx80_round_pack_canonical(pr, status);
97
}
98
};
99
100
+static Property smmuv3_properties[] = {
101
+ /*
102
+ * Stages of translation advertised.
103
+ * "1": Stage 1
104
+ * "2": Stage 2
105
+ * Defaults to stage 1
106
+ */
107
+ DEFINE_PROP_STRING("stage", SMMUv3State, stage),
108
+ DEFINE_PROP_END_OF_LIST()
109
+};
110
+
111
static void smmuv3_instance_init(Object *obj)
112
{
113
/* Nothing much to do here as of now */
114
@@ -XXX,XX +XXX,XX @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
115
&c->parent_phases);
116
c->parent_realize = dc->realize;
117
dc->realize = smmu_realize;
118
+ device_class_set_props(dc, smmuv3_properties);
119
}
70
}
120
71
121
static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,
72
/*----------------------------------------------------------------------------
122
--
73
--
123
2.34.1
74
2.34.1
diff view generated by jsdifflib
New patch
[PULL 67/72] softfloat: Inline pickNaN
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Inline pickNaN into its only caller. This makes one assert
4
redundant with the immediately preceding IF.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
13
2 files changed, 73 insertions(+), 105 deletions(-)
14
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/fpu/softfloat-parts.c.inc
18
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
float_status *s)
22
{
23
+ int cmp, which;
24
+
25
if (is_snan(a->cls) || is_snan(b->cls)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
if (s->default_nan_mode) {
30
parts_default_nan(a, s);
31
- } else {
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
118
index XXXXXXX..XXXXXXX 100644
119
--- a/fpu/softfloat-specialize.c.inc
120
+++ b/fpu/softfloat-specialize.c.inc
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
122
}
123
}
124
125
-/*----------------------------------------------------------------------------
126
-| Select which NaN to propagate for a two-input operation.
127
-| IEEE754 doesn't specify all the details of this, so the
128
-| algorithm is target-specific.
129
-| The routine is passed various bits of information about the
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
131
-| Note that signalling NaNs are always squashed to quiet NaNs
132
-| by the caller, by calling floatXX_silence_nan() before
133
-| returning them.
134
-|
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
136
-| of some kind, and is true if a has the larger significand,
137
-| or if both a and b have the same significand but a is
138
-| positive but b is negative. It is only needed for the x87
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
141
-
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
143
- bool aIsLargerSignificand, float_status *status)
144
-{
145
- /*
146
- * We guarantee not to require the target to tell us how to
147
- * pick a NaN if we're always returning the default NaN.
148
- * But if we're not in default-NaN mode then the target must
149
- * specify via set_float_2nan_prop_rule().
150
- */
151
- assert(!status->default_nan_mode);
152
-
153
- switch (status->float_2nan_prop_rule) {
154
- case float_2nan_prop_s_ab:
155
- if (is_snan(a_cls)) {
156
- return 0;
157
- } else if (is_snan(b_cls)) {
158
- return 1;
159
- } else if (is_qnan(a_cls)) {
160
- return 0;
161
- } else {
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
218
- }
219
-}
220
-
221
/*----------------------------------------------------------------------------
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
223
| NaN; otherwise returns 0.
224
--
225
2.34.1
226
227
diff view generated by jsdifflib
[PULL 14/21] tests/qtest: Run arm-specific tests only if the required machine is available
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Thomas Huth <thuth@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
pflash-cfi02-test.c always uses the "musicpal" machine for testing,
3
Remember if there was an SNaN, and use that to simplify
4
test-arm-mptimer.c always uses the "vexpress-a9" machine, and
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
microbit-test.c requires the "microbit" machine, so we should only
5
Then, fall through to the corresponding
6
run these tests if the machines have been enabled in the configuration.
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
7
8
8
Signed-off-by: Thomas Huth <thuth@redhat.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Fabiano Rosas <farosas@suse.de>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20230524080600.1618137-1-thuth@redhat.com
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
tests/qtest/meson.build | 7 ++++---
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
14
1 file changed, 4 insertions(+), 3 deletions(-)
15
1 file changed, 12 insertions(+), 20 deletions(-)
15
16
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/qtest/meson.build
19
--- a/fpu/softfloat-parts.c.inc
19
+++ b/tests/qtest/meson.build
20
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
21
(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
22
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
23
float_status *s)
23
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
24
{
24
- (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
25
+ bool have_snan = false;
25
+ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') and
26
int cmp, which;
26
+ config_all_devices.has_key('CONFIG_MUSICPAL') ? ['pflash-cfi02-test'] : []) + \
27
27
(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \
28
if (is_snan(a->cls) || is_snan(b->cls)) {
28
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
(config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'] : []) + \
30
+ have_snan = true;
30
(config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
31
}
31
+ (config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
32
32
+ (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
33
if (s->default_nan_mode) {
33
['arm-cpu-features',
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
34
- 'microbit-test',
35
35
- 'test-arm-mptimer',
36
switch (s->float_2nan_prop_rule) {
36
'boot-serial-test']
37
case float_2nan_prop_s_ab:
37
38
- if (is_snan(a->cls)) {
38
# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
39
- which = 0;
40
- } else if (is_snan(b->cls)) {
41
- which = 1;
42
- } else if (is_qnan(a->cls)) {
43
- which = 0;
44
- } else {
45
- which = 1;
46
+ if (have_snan) {
47
+ which = is_snan(a->cls) ? 0 : 1;
48
+ break;
49
}
50
- break;
51
- case float_2nan_prop_s_ba:
52
- if (is_snan(b->cls)) {
53
- which = 1;
54
- } else if (is_snan(a->cls)) {
55
- which = 0;
56
- } else if (is_qnan(b->cls)) {
57
- which = 1;
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
70
+ }
71
+ /* fall through */
72
case float_2nan_prop_ba:
73
which = is_nan(b->cls) ? 1 : 0;
74
break;
39
--
75
--
40
2.34.1
76
2.34.1
diff view generated by jsdifflib
[PULL 07/21] hw/arm/smmuv3: Make TLB lookup work for stage-2
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Mostafa Saleh <smostafa@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Right now, either stage-1 or stage-2 are supported, this simplifies
3
Move the fractional comparison to the end of the
4
how we can deal with TLBs.
4
float_2nan_prop_x87 case. This is not required for
5
This patch makes TLB lookup work if stage-2 is enabled instead of
5
any other 2nan propagation rule. Reorganize the
6
stage-1.
6
x87 case itself to break out of the switch when the
7
TLB lookup is done before a PTW, if a valid entry is found we won't
7
fractional comparison is not required.
8
do the PTW.
9
To be able to do TLB lookup, we need the correct tagging info, as
10
granularity and input size, so we get this based on the supported
11
translation stage. The TLB entries are added correctly from each
12
stage PTW.
13
8
14
When nested translation is supported, this would need to change, for
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
example if we go with a combined TLB implementation, we would need to
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
use the min of the granularities in TLB.
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
17
18
As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P
19
is not enabled.
20
21
Signed-off-by: Mostafa Saleh <smostafa@google.com>
22
Reviewed-by: Eric Auger <eric.auger@redhat.com>
23
Tested-by: Eric Auger <eric.auger@redhat.com>
24
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
25
Message-id: 20230516203327.2051088-7-smostafa@google.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
13
---
28
hw/arm/smmuv3.c | 44 +++++++++++++++++++++++++++++++++-----------
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
29
1 file changed, 33 insertions(+), 11 deletions(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
30
16
31
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
32
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/smmuv3.c
19
--- a/fpu/softfloat-parts.c.inc
34
+++ b/hw/arm/smmuv3.c
20
+++ b/fpu/softfloat-parts.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
36
STE ste;
22
return a;
37
CD cd;
38
39
+ /* ASID defaults to -1 (if s1 is not supported). */
40
+ cfg->asid = -1;
41
+
42
ret = smmu_find_ste(s, sid, &ste, event);
43
if (ret) {
44
return ret;
45
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
46
.addr_mask = ~(hwaddr)0,
47
.perm = IOMMU_NONE,
48
};
49
+ /*
50
+ * Combined attributes used for TLB lookup, as only one stage is supported,
51
+ * it will hold attributes based on the enabled stage.
52
+ */
53
+ SMMUTransTableInfo tt_combined;
54
55
qemu_mutex_lock(&s->mutex);
56
57
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
58
goto epilogue;
59
}
23
}
60
24
61
- tt = select_tt(cfg, addr);
25
- cmp = frac_cmp(a, b);
62
- if (!tt) {
26
- if (cmp == 0) {
63
- if (cfg->record_faults) {
27
- cmp = a->sign < b->sign;
64
- event.type = SMMU_EVT_F_TRANSLATION;
28
- }
65
- event.u.f_translation.addr = addr;
29
-
66
- event.u.f_translation.rnw = flag & 0x1;
30
switch (s->float_2nan_prop_rule) {
67
+ if (cfg->stage == 1) {
31
case float_2nan_prop_s_ab:
68
+ /* Select stage1 translation table. */
32
if (have_snan) {
69
+ tt = select_tt(cfg, addr);
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
70
+ if (!tt) {
34
* return the NaN with the positive sign bit (if any).
71
+ if (cfg->record_faults) {
35
*/
72
+ event.type = SMMU_EVT_F_TRANSLATION;
36
if (is_snan(a->cls)) {
73
+ event.u.f_translation.addr = addr;
37
- if (is_snan(b->cls)) {
74
+ event.u.f_translation.rnw = flag & 0x1;
38
- which = cmp > 0 ? 0 : 1;
75
+ }
39
- } else {
76
+ status = SMMU_TRANS_ERROR;
40
+ if (!is_snan(b->cls)) {
77
+ goto epilogue;
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
43
}
44
} else if (is_qnan(a->cls)) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
46
which = 0;
47
- } else {
48
- which = cmp > 0 ? 0 : 1;
49
+ break;
50
}
51
} else {
52
which = 1;
53
+ break;
78
}
54
}
79
- status = SMMU_TRANS_ERROR;
55
+ cmp = frac_cmp(a, b);
80
- goto epilogue;
56
+ if (cmp == 0) {
81
- }
57
+ cmp = a->sign < b->sign;
82
+ tt_combined.granule_sz = tt->granule_sz;
58
+ }
83
+ tt_combined.tsz = tt->tsz;
59
+ which = cmp > 0 ? 0 : 1;
84
60
break;
85
- page_mask = (1ULL << (tt->granule_sz)) - 1;
61
default:
86
+ } else {
62
g_assert_not_reached();
87
+ /* Stage2. */
88
+ tt_combined.granule_sz = cfg->s2cfg.granule_sz;
89
+ tt_combined.tsz = cfg->s2cfg.tsz;
90
+ }
91
+ /*
92
+ * TLB lookup looks for granule and input size for a translation stage,
93
+ * as only one stage is supported right now, choose the right values
94
+ * from the configuration.
95
+ */
96
+ page_mask = (1ULL << tt_combined.granule_sz) - 1;
97
aligned_addr = addr & ~page_mask;
98
99
- cached_entry = smmu_iotlb_lookup(bs, cfg, tt, aligned_addr);
100
+ cached_entry = smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr);
101
if (cached_entry) {
102
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
103
status = SMMU_TRANS_ERROR;
104
--
63
--
105
2.34.1
64
2.34.1
diff view generated by jsdifflib
[PULL 09/21] hw/arm/smmuv3: Add CMDs related to stage-2
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Mostafa Saleh <smostafa@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
3
Replace the "index" selecting between A and B with a result variable
4
same as CMD_TLBI_NH_VAA.
4
of the proper type. This improves clarity within the function.
5
5
6
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
For stage-1 only commands, add a check to throw CERROR_ILL if used
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
9
when stage-1 is not supported.
10
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Signed-off-by: Mostafa Saleh <smostafa@google.com>
13
Tested-by: Eric Auger <eric.auger@redhat.com>
14
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
15
Message-id: 20230516203327.2051088-9-smostafa@google.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
10
---
18
include/hw/arm/smmu-common.h | 1 +
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
19
hw/arm/smmu-common.c | 16 +++++++++++
12
1 file changed, 13 insertions(+), 15 deletions(-)
20
hw/arm/smmuv3.c | 55 ++++++++++++++++++++++++++++++------
21
hw/arm/trace-events | 4 ++-
22
4 files changed, 67 insertions(+), 9 deletions(-)
23
13
24
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/arm/smmu-common.h
16
--- a/fpu/softfloat-parts.c.inc
27
+++ b/include/hw/arm/smmu-common.h
17
+++ b/fpu/softfloat-parts.c.inc
28
@@ -XXX,XX +XXX,XX @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
29
uint8_t tg, uint8_t level);
19
float_status *s)
30
void smmu_iotlb_inv_all(SMMUState *s);
31
void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
32
+void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid);
33
void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
34
uint8_t tg, uint64_t num_pages, uint8_t ttl);
35
36
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/smmu-common.c
39
+++ b/hw/arm/smmu-common.c
40
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
41
42
return SMMU_IOTLB_ASID(*iotlb_key) == asid;
43
}
44
+
45
+static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value,
46
+ gpointer user_data)
47
+{
48
+ uint16_t vmid = *(uint16_t *)user_data;
49
+ SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
50
+
51
+ return SMMU_IOTLB_VMID(*iotlb_key) == vmid;
52
+}
53
+
54
static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer value,
55
gpointer user_data)
56
{
20
{
57
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
21
bool have_snan = false;
58
g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
22
- int cmp, which;
59
}
23
+ FloatPartsN *ret;
60
24
+ int cmp;
61
+inline void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid)
25
62
+{
26
if (is_snan(a->cls) || is_snan(b->cls)) {
63
+ trace_smmu_iotlb_inv_vmid(vmid);
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
64
+ g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid);
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
65
+}
29
switch (s->float_2nan_prop_rule) {
66
+
30
case float_2nan_prop_s_ab:
67
/* VMSAv8-64 Translation */
31
if (have_snan) {
68
32
- which = is_snan(a->cls) ? 0 : 1;
69
/**
33
+ ret = is_snan(a->cls) ? a : b;
70
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/smmuv3.c
73
+++ b/hw/arm/smmuv3.c
74
@@ -XXX,XX +XXX,XX @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
75
}
76
}
77
78
-static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
79
+static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
80
{
81
dma_addr_t end, addr = CMD_ADDR(cmd);
82
uint8_t type = CMD_TYPE(cmd);
83
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
84
}
85
86
if (!tg) {
87
- trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
88
+ trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
89
smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
90
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
91
return;
92
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
93
uint64_t mask = dma_aligned_pow2_mask(addr, end, 64);
94
95
num_pages = (mask + 1) >> granule;
96
- trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
97
+ trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
98
smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
99
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
100
addr += mask + 1;
101
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
102
{
103
uint16_t asid = CMD_ASID(&cmd);
104
105
+ if (!STAGE1_SUPPORTED(s)) {
106
+ cmd_error = SMMU_CERROR_ILL;
107
+ break;
108
+ }
109
+
110
trace_smmuv3_cmdq_tlbi_nh_asid(asid);
111
smmu_inv_notifiers_all(&s->smmu_state);
112
smmu_iotlb_inv_asid(bs, asid);
113
break;
34
break;
114
}
35
}
115
case SMMU_CMD_TLBI_NH_ALL:
36
/* fall through */
116
+ if (!STAGE1_SUPPORTED(s)) {
37
case float_2nan_prop_ab:
117
+ cmd_error = SMMU_CERROR_ILL;
38
- which = is_nan(a->cls) ? 0 : 1;
118
+ break;
39
+ ret = is_nan(a->cls) ? a : b;
119
+ }
40
break;
120
+ QEMU_FALLTHROUGH;
41
case float_2nan_prop_s_ba:
121
case SMMU_CMD_TLBI_NSNH_ALL:
42
if (have_snan) {
122
trace_smmuv3_cmdq_tlbi_nh();
43
- which = is_snan(b->cls) ? 1 : 0;
123
smmu_inv_notifiers_all(&s->smmu_state);
44
+ ret = is_snan(b->cls) ? b : a;
124
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
125
break;
126
case SMMU_CMD_TLBI_NH_VAA:
127
case SMMU_CMD_TLBI_NH_VA:
128
- smmuv3_s1_range_inval(bs, &cmd);
129
+ if (!STAGE1_SUPPORTED(s)) {
130
+ cmd_error = SMMU_CERROR_ILL;
131
+ break;
132
+ }
133
+ smmuv3_range_inval(bs, &cmd);
134
+ break;
135
+ case SMMU_CMD_TLBI_S12_VMALL:
136
+ {
137
+ uint16_t vmid = CMD_VMID(&cmd);
138
+
139
+ if (!STAGE2_SUPPORTED(s)) {
140
+ cmd_error = SMMU_CERROR_ILL;
141
+ break;
142
+ }
143
+
144
+ trace_smmuv3_cmdq_tlbi_s12_vmid(vmid);
145
+ smmu_inv_notifiers_all(&s->smmu_state);
146
+ smmu_iotlb_inv_vmid(bs, vmid);
147
+ break;
148
+ }
149
+ case SMMU_CMD_TLBI_S2_IPA:
150
+ if (!STAGE2_SUPPORTED(s)) {
151
+ cmd_error = SMMU_CERROR_ILL;
152
+ break;
153
+ }
154
+ /*
155
+ * As currently only either s1 or s2 are supported
156
+ * we can reuse same function for s2.
157
+ */
158
+ smmuv3_range_inval(bs, &cmd);
159
break;
160
case SMMU_CMD_TLBI_EL3_ALL:
161
case SMMU_CMD_TLBI_EL3_VA:
162
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
163
case SMMU_CMD_TLBI_EL2_ASID:
164
case SMMU_CMD_TLBI_EL2_VA:
165
case SMMU_CMD_TLBI_EL2_VAA:
166
- case SMMU_CMD_TLBI_S12_VMALL:
167
- case SMMU_CMD_TLBI_S2_IPA:
168
case SMMU_CMD_ATC_INV:
169
case SMMU_CMD_PRI_RESP:
170
case SMMU_CMD_RESUME:
171
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
172
break;
173
default:
174
cmd_error = SMMU_CERROR_ILL;
175
- qemu_log_mask(LOG_GUEST_ERROR,
176
- "Illegal command type: %d\n", CMD_TYPE(&cmd));
177
break;
45
break;
178
}
46
}
179
qemu_mutex_unlock(&s->mutex);
47
/* fall through */
180
if (cmd_error) {
48
case float_2nan_prop_ba:
181
+ if (cmd_error == SMMU_CERROR_ILL) {
49
- which = is_nan(b->cls) ? 1 : 0;
182
+ qemu_log_mask(LOG_GUEST_ERROR,
50
+ ret = is_nan(b->cls) ? b : a;
183
+ "Illegal command type: %d\n", CMD_TYPE(&cmd));
51
break;
184
+ }
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
185
break;
71
break;
186
}
72
}
187
/*
73
cmp = frac_cmp(a, b);
188
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
74
if (cmp == 0) {
189
index XXXXXXX..XXXXXXX 100644
75
cmp = a->sign < b->sign;
190
--- a/hw/arm/trace-events
76
}
191
+++ b/hw/arm/trace-events
77
- which = cmp > 0 ? 0 : 1;
192
@@ -XXX,XX +XXX,XX @@ smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, ui
78
+ ret = cmp > 0 ? a : b;
193
smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
79
break;
194
smmu_iotlb_inv_all(void) "IOTLB invalidate all"
80
default:
195
smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
81
g_assert_not_reached();
196
+smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=%d"
82
}
197
smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
83
198
smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
84
- if (which) {
199
smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
85
- a = b;
200
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
86
+ if (is_snan(ret->cls)) {
201
smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
87
+ parts_silence_nan(ret, s);
202
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
88
}
203
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
89
- if (is_snan(a->cls)) {
204
-smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
90
- parts_silence_nan(a, s);
205
+smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
91
- }
206
smmuv3_cmdq_tlbi_nh(void) ""
92
- return a;
207
smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
93
+ return ret;
208
+smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
94
}
209
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
95
210
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
211
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
212
--
97
--
213
2.34.1
98
2.34.1
99
100
diff view generated by jsdifflib
[PULL 16/21] target/arm: Explain why we need to select ARM_V7M
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Fabiano Rosas <farosas@suse.de>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
We currently need to select ARM_V7M unconditionally when TCG is
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
present in the build because some translate.c helpers and the whole of
4
update my email address, and update the mailmap to match.
5
m_helpers.c are not yet under CONFIG_ARM_V7M.
6
5
7
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20230523180525.29994-2-farosas@suse.de
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
target/arm/Kconfig | 3 +++
14
MAINTAINERS | 2 +-
14
1 file changed, 3 insertions(+)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
15
17
16
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
18
diff --git a/MAINTAINERS b/MAINTAINERS
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/Kconfig
20
--- a/MAINTAINERS
19
+++ b/target/arm/Kconfig
21
+++ b/MAINTAINERS
20
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
21
config ARM
23
SBSA-REF
22
bool
24
M: Radoslaw Biernacki <rad@semihalf.com>
23
select ARM_COMPATIBLE_SEMIHOSTING if TCG
25
M: Peter Maydell <peter.maydell@linaro.org>
24
+
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
25
+ # We need to select this until we move m_helper.c and the
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
26
+ # translate.c v7m helpers under ARM_V7M.
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
27
select ARM_V7M if TCG
29
L: qemu-arm@nongnu.org
28
30
S: Maintained
29
config AARCH64
31
diff --git a/.mailmap b/.mailmap
32
index XXXXXXX..XXXXXXX 100644
33
--- a/.mailmap
34
+++ b/.mailmap
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
30
--
47
--
31
2.34.1
48
2.34.1
32
49
33
50
diff view generated by jsdifflib
[PULL 02/21] hw/arm/smmuv3: Add missing fields for IDR0
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Mostafa Saleh <smostafa@google.com>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
In preparation for adding stage-2 support.
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
Add IDR0 fields related to stage-2.
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
5
6
VMID16: 16-bit VMID supported.
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
7
S2P: Stage-2 translation supported.
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
9
They are described in 6.3.1 SMMU_IDR0.
10
11
No functional change intended.
12
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
Signed-off-by: Mostafa Saleh <smostafa@google.com>
16
Tested-by: Eric Auger <eric.auger@redhat.com>
17
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
18
Message-id: 20230516203327.2051088-2-smostafa@google.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
10
---
21
hw/arm/smmuv3-internal.h | 2 ++
11
MAINTAINERS | 2 ++
22
1 file changed, 2 insertions(+)
12
1 file changed, 2 insertions(+)
23
13
24
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
14
diff --git a/MAINTAINERS b/MAINTAINERS
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/smmuv3-internal.h
16
--- a/MAINTAINERS
27
+++ b/hw/arm/smmuv3-internal.h
17
+++ b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ typedef enum SMMUTranslationStatus {
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
29
/* MMIO Registers */
19
30
20
Xilinx CAN
31
REG32(IDR0, 0x0)
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
32
+ FIELD(IDR0, S2P, 0 , 1)
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
33
FIELD(IDR0, S1P, 1 , 1)
23
S: Maintained
34
FIELD(IDR0, TTF, 2 , 2)
24
F: hw/net/can/xlnx-*
35
FIELD(IDR0, COHACC, 4 , 1)
25
F: include/hw/net/xlnx-*
36
FIELD(IDR0, ASID16, 12, 1)
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
37
+ FIELD(IDR0, VMID16, 18, 1)
27
CAN bus subsystem and hardware
38
FIELD(IDR0, TTENDIAN, 21, 2)
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
39
FIELD(IDR0, STALL_MODEL, 24, 2)
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
40
FIELD(IDR0, TERM_MODEL, 26, 1)
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
31
S: Maintained
32
W: https://canbus.pages.fel.cvut.cz/
33
F: net/can/*
41
--
34
--
42
2.34.1
35
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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