[v2] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support

[PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

Posted by Rajnesh Kanwal 2 years, 8 months ago

RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
 target/riscv/cpu_helper.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57d04385f1..b25ee179e9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1602,15 +1602,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
     target_ulong htval = 0;
     target_ulong mtval2 = 0;
 
-    if  (cause == RISCV_EXCP_SEMIHOST) {
-        do_common_semihosting(cs);
-        env->pc += 4;
-        return;
-    }
-
     if (!async) {
         /* set tval to badaddr for traps with address information */
         switch (cause) {
+        case RISCV_EXCP_SEMIHOST:
+            do_common_semihosting(cs);
+            env->pc += 4;
+            return;
         case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
         case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
         case RISCV_EXCP_LOAD_ADDR_MIS:
-- 
2.25.1

Re: [PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

Posted by Alistair Francis 2 years, 8 months ago

On Sat, May 27, 2023 at 2:24 AM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
> as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
> async flag check is performed before invoking semihosting logic.
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 57d04385f1..b25ee179e9 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1602,15 +1602,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>      target_ulong htval = 0;
>      target_ulong mtval2 = 0;
>
> -    if  (cause == RISCV_EXCP_SEMIHOST) {
> -        do_common_semihosting(cs);
> -        env->pc += 4;
> -        return;
> -    }
> -
>      if (!async) {
>          /* set tval to badaddr for traps with address information */
>          switch (cause) {
> +        case RISCV_EXCP_SEMIHOST:
> +            do_common_semihosting(cs);
> +            env->pc += 4;
> +            return;
>          case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
>          case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
>          case RISCV_EXCP_LOAD_ADDR_MIS:
> --
> 2.25.1
>
>

[PATCH v2 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.
[PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
[PATCH v2 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
[PATCH v2 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.
[PATCH v2 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
[PATCH v2 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.