the linker might rearrange sections, so lets reference memory by label
name instead of addr + off.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 1 -
tests/tcg/tricore/asm/test_ld_bu.S | 4 ++--
tests/tcg/tricore/asm/test_ld_h.S | 8 ++++----
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 3df2e0de82..b5087b5c97 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -25,7 +25,6 @@
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
-#define MEM_BASE_ADDR 0xd0000000
#define DREG_DEV_ADDR %a15
diff --git a/tests/tcg/tricore/asm/test_ld_bu.S b/tests/tcg/tricore/asm/test_ld_bu.S
index ff9dac128b..4a1f40c37b 100644
--- a/tests/tcg/tricore/asm/test_ld_bu.S
+++ b/tests/tcg/tricore/asm/test_ld_bu.S
@@ -9,7 +9,7 @@ _start:
# expect. addr reg val after load
# insn num expect. load value | pattern for loading
# | | | | |
- TEST_LD(ld.bu, 1, 0xff, MEM_BASE_ADDR + 4, [+AREG_ADDR]4) # pre_inc
- TEST_LD(ld.bu, 2, 0xad, MEM_BASE_ADDR + 4, [AREG_ADDR+]4) # post_inc
+ TEST_LD(ld.bu, 1, 0xff, test_data + 4, [+AREG_ADDR]4) # pre_inc
+ TEST_LD(ld.bu, 2, 0xad, test_data + 4, [AREG_ADDR+]4) # post_inc
TEST_PASSFAIL
diff --git a/tests/tcg/tricore/asm/test_ld_h.S b/tests/tcg/tricore/asm/test_ld_h.S
index d3c157a046..f5e4959198 100644
--- a/tests/tcg/tricore/asm/test_ld_h.S
+++ b/tests/tcg/tricore/asm/test_ld_h.S
@@ -7,9 +7,9 @@ test_data:
.global _start
_start:
# expect. addr reg val after load
-# insn num expect. load value | pattern for loading
-# | | | | |
- TEST_LD (ld.h, 1, 0xffffaffe, MEM_BASE_ADDR, [AREG_ADDR]2)
- TEST_LD_SRO(ld.h, 2, 0x000022ff, MEM_BASE_ADDR, [AREG_ADDR]4)
+# insn num expect. load value | pattern for loading
+# | | | | |
+ TEST_LD (ld.h, 1, 0xffffaffe, test_data, [AREG_ADDR]2)
+ TEST_LD_SRO(ld.h, 2, 0x000022ff, test_data, [AREG_ADDR]4)
TEST_PASSFAIL
--
2.40.1