This is a merge of a couple of singleton fixes, CONFIG_ATOMIC128
detection, and tcg backend code generation patch sets, just to
keep everything in one place.
Tested with the Arm FEAT_LSE2 patch set, which greatly increases
the number of 16-byte atomic operations.
Patches needing review:
01-tcg-Fix-register-move-type-in-tcg_out_ld_helper_r.patch
02-accel-tcg-Fix-check-for-page-writeability-in-load.patch
03-meson-Split-test-for-__int128_t-type-from-__int12.patch
05-tcg-i386-Support-128-bit-load-store.patch
07-tcg-aarch64-Reserve-TCG_REG_TMP1-TCG_REG_TMP2.patch
08-tcg-aarch64-Simplify-constraints-on-qemu_ld-st.patch
12-accel-tcg-Extract-load_atom_extract_al16_or_al8-t.patch
13-accel-tcg-Extract-store_atom_insert_al16-to-host-.patch
14-accel-tcg-Add-x86_64-load_atom_extract_al16_or_al.patch
15-accel-tcg-Add-aarch64-lse2-load_atom_extract_al16.patch
16-accel-tcg-Add-aarch64-store_atom_insert_al16.patch
r~
Richard Henderson (16):
tcg: Fix register move type in tcg_out_ld_helper_ret
accel/tcg: Fix check for page writeability in load_atomic16_or_exit
meson: Split test for __int128_t type from __int128_t arithmetic
qemu/atomic128: Add x86_64 atomic128-ldst.h
tcg/i386: Support 128-bit load/store
tcg/aarch64: Rename temporaries
tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2
tcg/aarch64: Simplify constraints on qemu_ld/st
tcg/aarch64: Support 128-bit load/store
tcg/ppc: Support 128-bit load/store
tcg/s390x: Support 128-bit load/store
accel/tcg: Extract load_atom_extract_al16_or_al8 to host header
accel/tcg: Extract store_atom_insert_al16 to host header
accel/tcg: Add x86_64 load_atom_extract_al16_or_al8
accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8
accel/tcg: Add aarch64 store_atom_insert_al16
meson.build | 15 +-
.../aarch64/host/load-extract-al16-al8.h | 40 +++
host/include/aarch64/host/store-insert-al16.h | 47 ++++
.../generic/host/load-extract-al16-al8.h | 45 ++++
host/include/generic/host/store-insert-al16.h | 50 ++++
host/include/x86_64/host/atomic128-ldst.h | 68 +++++
.../x86_64/host/load-extract-al16-al8.h | 50 ++++
include/qemu/int128.h | 4 +-
tcg/aarch64/tcg-target-con-set.h | 4 +-
tcg/aarch64/tcg-target-con-str.h | 1 -
tcg/aarch64/tcg-target.h | 11 +-
tcg/i386/tcg-target.h | 4 +-
tcg/ppc/tcg-target-con-set.h | 2 +
tcg/ppc/tcg-target-con-str.h | 1 +
tcg/ppc/tcg-target.h | 3 +-
tcg/s390x/tcg-target-con-set.h | 2 +
tcg/s390x/tcg-target.h | 2 +-
tcg/tcg.c | 4 +-
accel/tcg/ldst_atomicity.c.inc | 78 +-----
tcg/aarch64/tcg-target.c.inc | 243 ++++++++++++++----
tcg/i386/tcg-target.c.inc | 191 +++++++++++++-
tcg/ppc/tcg-target.c.inc | 108 +++++++-
tcg/s390x/tcg-target.c.inc | 103 +++++++-
23 files changed, 913 insertions(+), 163 deletions(-)
create mode 100644 host/include/aarch64/host/load-extract-al16-al8.h
create mode 100644 host/include/aarch64/host/store-insert-al16.h
create mode 100644 host/include/generic/host/load-extract-al16-al8.h
create mode 100644 host/include/generic/host/store-insert-al16.h
create mode 100644 host/include/x86_64/host/atomic128-ldst.h
create mode 100644 host/include/x86_64/host/load-extract-al16-al8.h
--
2.34.1