Fix lines with over 80 characters.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
disas/riscv.c | 201 +++++++++++++++++++++++++++++++++++---------------
1 file changed, 140 insertions(+), 61 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index a8eca47da2..e5d3cefd17 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1108,8 +1108,10 @@ static const char rv_vreg_name_sym[32][4] = {
/* pseudo-instruction constraints */
static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
-static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
-static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
+static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
+ rvc_end };
+static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
+ rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
@@ -1139,18 +1141,28 @@ static const rvc_constraint rvcc_bleu[] = { rvc_end };
static const rvc_constraint rvcc_bgt[] = { rvc_end };
static const rvc_constraint rvcc_bgtu[] = { rvc_end };
static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
-static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
-static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
-static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
-static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
-static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
-static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
-static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
+static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
+ rvc_end };
+static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
+ rvc_end };
+static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
+ rvc_end };
+static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
+ rvc_end };
+static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
+ rvc_csr_eq_0xc02, rvc_end };
+static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
+ rvc_csr_eq_0xc80, rvc_end };
+static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
+ rvc_end };
static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc82, rvc_end };
-static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
-static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
-static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
+static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
+ rvc_end };
+static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
+ rvc_end };
+static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
+ rvc_end };
static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
@@ -1552,17 +1564,23 @@ const rv_opcode_data opcode_data[] = {
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
- { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
- { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
+ { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
+ rv_op_fld, 0 },
+ { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
+ rv_op_lw },
{ "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
- { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
- { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
+ { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
+ rv_op_fsd, 0 },
+ { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
+ rv_op_sw },
{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
- { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
{ "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
rv_op_addi, rvcd_imm_nz },
{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
- { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
{ "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
@@ -1573,37 +1591,63 @@ const rv_opcode_data opcode_data[] = {
rv_op_srai, rv_op_srai, rvcd_imm_nz },
{ "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
rv_op_andi, rv_op_andi },
- { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
- { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
- { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
- { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
- { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
- { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
- { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
- { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
- { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
+ { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
+ rv_op_sub },
+ { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
+ rv_op_xor },
+ { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
+ rv_op_or },
+ { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
+ rv_op_and },
+ { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
+ rv_op_subw },
+ { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
+ rv_op_addw },
+ { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
+ rv_op_jal },
+ { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
+ rv_op_beq },
+ { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
+ rv_op_bne },
{ "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
rv_op_slli, rv_op_slli, rvcd_imm_nz },
- { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
- { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
- { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
- { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
- { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
- { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
- { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
- { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
- { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
- { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
- { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
- { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
- { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
- { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
- { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
- { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
+ { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
+ rv_op_fld, rv_op_fld },
+ { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
+ rv_op_lw, rv_op_lw },
+ { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
+ 0 },
+ { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
+ rv_op_jalr, rv_op_jalr },
+ { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
+ { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
+ rv_op_ebreak, rv_op_ebreak },
+ { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
+ rv_op_jalr, rv_op_jalr },
+ { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
+ rv_op_add },
+ { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
+ rv_op_fsd, rv_op_fsd },
+ { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
+ rv_op_sw, rv_op_sw },
+ { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
+ 0 },
+ { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
+ rv_op_ld },
+ { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
+ rv_op_sd },
+ { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
+ rv_op_addiw },
+ { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
+ rv_op_ld },
+ { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
+ rv_op_sd },
{ "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
{ "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
{ "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
- { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
+ { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
+ rv_op_sq },
{ "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
{ "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
@@ -2840,7 +2884,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 11:
- switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 24) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 2: op = rv_op_amoadd_w; break;
case 3: op = rv_op_amoadd_d; break;
case 4: op = rv_op_amoadd_q; break;
@@ -2889,7 +2934,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 12:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_add; break;
case 1: op = rv_op_sll; break;
case 2: op = rv_op_slt; break;
@@ -2960,7 +3006,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 13: op = rv_op_lui; break;
case 14:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addw; break;
case 1: op = rv_op_sllw; break;
case 5: op = rv_op_srlw; break;
@@ -3169,35 +3216,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 112:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_s; break;
case 1: op = rv_op_fclass_s; break;
}
break;
case 113:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_d; break;
case 1: op = rv_op_fclass_d; break;
}
break;
case 115:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_q; break;
case 1: op = rv_op_fclass_q; break;
}
break;
case 120:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_s_x; break;
}
break;
case 121:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_d_x; break;
}
break;
case 123:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_q_x; break;
}
break;
@@ -3218,9 +3271,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 11: op = rv_op_vxor_vv; break;
case 12: op = rv_op_vrgather_vv; break;
case 14: op = rv_op_vrgatherei16_vv; break;
- case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vvm;
+ }
+ break;
case 17: op = rv_op_vmadc_vvm; break;
- case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
+ case 18:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vsbc_vvm;
+ }
+ break;
case 19: op = rv_op_vmsbc_vvm; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
@@ -3367,7 +3428,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 2: op = rv_op_vmsof_m; break;
case 3: op = rv_op_vmsif_m; break;
case 16: op = rv_op_viota_m; break;
- case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
+ case 17:
+ if (((inst >> 20) & 0b11111) == 0) {
+ op = rv_op_vid_v;
+ }
+ break;
}
break;
case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
@@ -3417,7 +3482,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 12: op = rv_op_vrgather_vi; break;
case 14: op = rv_op_vslideup_vi; break;
case 15: op = rv_op_vslidedown_vi; break;
- case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vim;
+ }
+ break;
case 17: op = rv_op_vmadc_vim; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
@@ -3467,9 +3536,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 12: op = rv_op_vrgather_vx; break;
case 14: op = rv_op_vslideup_vx; break;
case 15: op = rv_op_vslidedown_vx; break;
- case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vxm;
+ }
+ break;
case 17: op = rv_op_vmadc_vxm; break;
- case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
+ case 18:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vsbc_vxm;
+ }
+ break;
case 19: op = rv_op_vmsbc_vxm; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
@@ -3640,7 +3717,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 28:
switch (((inst >> 12) & 0b111)) {
case 0:
- switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
+ switch (((inst >> 20) & 0b111111100000) |
+ ((inst >> 7) & 0b000000011111)) {
case 0:
switch (((inst >> 15) & 0b1111111111)) {
case 0: op = rv_op_ecall; break;
@@ -3690,7 +3768,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 30:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addd; break;
case 1: op = rv_op_slld; break;
case 5: op = rv_op_srld; break;
--
2.25.1On Tue, May 23, 2023 at 7:37 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Fix lines with over 80 characters.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 201 +++++++++++++++++++++++++++++++++++---------------
> 1 file changed, 140 insertions(+), 61 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index a8eca47da2..e5d3cefd17 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1108,8 +1108,10 @@ static const char rv_vreg_name_sym[32][4] = {
> /* pseudo-instruction constraints */
>
> static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
> -static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
> -static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
> +static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
> + rvc_end };
> +static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
> + rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
> static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
> @@ -1139,18 +1141,28 @@ static const rvc_constraint rvcc_bleu[] = { rvc_end };
> static const rvc_constraint rvcc_bgt[] = { rvc_end };
> static const rvc_constraint rvcc_bgtu[] = { rvc_end };
> static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
> -static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
> -static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
> -static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
> -static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
> -static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
> -static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
> -static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
> +static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
> + rvc_end };
> +static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
> + rvc_end };
> +static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
> + rvc_end };
> +static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
> + rvc_end };
> +static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
> + rvc_csr_eq_0xc02, rvc_end };
> +static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
> + rvc_csr_eq_0xc80, rvc_end };
> +static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
> + rvc_end };
> static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0xc82, rvc_end };
> -static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
> -static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
> -static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
> +static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
> + rvc_end };
> +static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
> + rvc_end };
> +static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
> + rvc_end };
> static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
> static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
> static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
> @@ -1552,17 +1564,23 @@ const rv_opcode_data opcode_data[] = {
> { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
> { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi, rv_op_addi, rvcd_imm_nz },
> - { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
> - { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
> + { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
> + rv_op_fld, 0 },
> + { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
> + rv_op_lw },
> { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
> - { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
> - { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
> + { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
> + rv_op_fsd, 0 },
> + { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
> + rv_op_sw },
> { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
> - { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
> + { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
> + rv_op_addi },
> { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
> rv_op_addi, rvcd_imm_nz },
> { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
> - { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
> + { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
> + rv_op_addi },
> { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi, rv_op_addi, rvcd_imm_nz },
> { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
> @@ -1573,37 +1591,63 @@ const rv_opcode_data opcode_data[] = {
> rv_op_srai, rv_op_srai, rvcd_imm_nz },
> { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
> rv_op_andi, rv_op_andi },
> - { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
> - { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
> - { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
> - { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
> - { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
> - { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
> - { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
> - { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
> - { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
> + { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
> + rv_op_sub },
> + { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
> + rv_op_xor },
> + { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
> + rv_op_or },
> + { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
> + rv_op_and },
> + { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
> + rv_op_subw },
> + { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
> + rv_op_addw },
> + { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
> + rv_op_jal },
> + { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
> + rv_op_beq },
> + { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
> + rv_op_bne },
> { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
> rv_op_slli, rv_op_slli, rvcd_imm_nz },
> - { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
> - { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
> - { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
> - { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
> - { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
> - { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
> - { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
> - { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
> - { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
> - { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
> - { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
> - { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
> - { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
> - { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
> - { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
> - { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
> + { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
> + rv_op_fld, rv_op_fld },
> + { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
> + rv_op_lw, rv_op_lw },
> + { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
> + 0 },
> + { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
> + rv_op_jalr, rv_op_jalr },
> + { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
> + rv_op_addi },
> + { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
> + rv_op_ebreak, rv_op_ebreak },
> + { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
> + rv_op_jalr, rv_op_jalr },
> + { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
> + rv_op_add },
> + { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
> + rv_op_fsd, rv_op_fsd },
> + { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
> + rv_op_sw, rv_op_sw },
> + { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
> + 0 },
> + { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
> + rv_op_ld },
> + { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
> + rv_op_sd },
> + { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
> + rv_op_addiw },
> + { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
> + rv_op_ld },
> + { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
> + rv_op_sd },
> { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
> { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
> { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
> - { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
> + { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
> + rv_op_sq },
> { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
> { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> @@ -2840,7 +2884,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> }
> break;
> case 11:
> - switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
> + switch (((inst >> 24) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> case 2: op = rv_op_amoadd_w; break;
> case 3: op = rv_op_amoadd_d; break;
> case 4: op = rv_op_amoadd_q; break;
> @@ -2889,7 +2934,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> }
> break;
> case 12:
> - switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
> + switch (((inst >> 22) & 0b1111111000) |
> + ((inst >> 12) & 0b0000000111)) {
> case 0: op = rv_op_add; break;
> case 1: op = rv_op_sll; break;
> case 2: op = rv_op_slt; break;
> @@ -2960,7 +3006,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> break;
> case 13: op = rv_op_lui; break;
> case 14:
> - switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
> + switch (((inst >> 22) & 0b1111111000) |
> + ((inst >> 12) & 0b0000000111)) {
> case 0: op = rv_op_addw; break;
> case 1: op = rv_op_sllw; break;
> case 5: op = rv_op_srlw; break;
> @@ -3169,35 +3216,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> }
> break;
> case 112:
> - switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> case 0: op = rv_op_fmv_x_s; break;
> case 1: op = rv_op_fclass_s; break;
> }
> break;
> case 113:
> - switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> case 0: op = rv_op_fmv_x_d; break;
> case 1: op = rv_op_fclass_d; break;
> }
> break;
> case 115:
> - switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> case 0: op = rv_op_fmv_x_q; break;
> case 1: op = rv_op_fclass_q; break;
> }
> break;
> case 120:
> - switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> case 0: op = rv_op_fmv_s_x; break;
> }
> break;
> case 121:
> - switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> case 0: op = rv_op_fmv_d_x; break;
> }
> break;
> case 123:
> - switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> case 0: op = rv_op_fmv_q_x; break;
> }
> break;
> @@ -3218,9 +3271,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 11: op = rv_op_vxor_vv; break;
> case 12: op = rv_op_vrgather_vv; break;
> case 14: op = rv_op_vrgatherei16_vv; break;
> - case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
> + case 16:
> + if (((inst >> 25) & 1) == 0) {
> + op = rv_op_vadc_vvm;
> + }
> + break;
> case 17: op = rv_op_vmadc_vvm; break;
> - case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
> + case 18:
> + if (((inst >> 25) & 1) == 0) {
> + op = rv_op_vsbc_vvm;
> + }
> + break;
> case 19: op = rv_op_vmsbc_vvm; break;
> case 23:
> if (((inst >> 20) & 0b111111) == 32)
> @@ -3367,7 +3428,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 2: op = rv_op_vmsof_m; break;
> case 3: op = rv_op_vmsif_m; break;
> case 16: op = rv_op_viota_m; break;
> - case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
> + case 17:
> + if (((inst >> 20) & 0b11111) == 0) {
> + op = rv_op_vid_v;
> + }
> + break;
> }
> break;
> case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
> @@ -3417,7 +3482,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 12: op = rv_op_vrgather_vi; break;
> case 14: op = rv_op_vslideup_vi; break;
> case 15: op = rv_op_vslidedown_vi; break;
> - case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
> + case 16:
> + if (((inst >> 25) & 1) == 0) {
> + op = rv_op_vadc_vim;
> + }
> + break;
> case 17: op = rv_op_vmadc_vim; break;
> case 23:
> if (((inst >> 20) & 0b111111) == 32)
> @@ -3467,9 +3536,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 12: op = rv_op_vrgather_vx; break;
> case 14: op = rv_op_vslideup_vx; break;
> case 15: op = rv_op_vslidedown_vx; break;
> - case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
> + case 16:
> + if (((inst >> 25) & 1) == 0) {
> + op = rv_op_vadc_vxm;
> + }
> + break;
> case 17: op = rv_op_vmadc_vxm; break;
> - case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
> + case 18:
> + if (((inst >> 25) & 1) == 0) {
> + op = rv_op_vsbc_vxm;
> + }
> + break;
> case 19: op = rv_op_vmsbc_vxm; break;
> case 23:
> if (((inst >> 20) & 0b111111) == 32)
> @@ -3640,7 +3717,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 28:
> switch (((inst >> 12) & 0b111)) {
> case 0:
> - switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
> + switch (((inst >> 20) & 0b111111100000) |
> + ((inst >> 7) & 0b000000011111)) {
> case 0:
> switch (((inst >> 15) & 0b1111111111)) {
> case 0: op = rv_op_ecall; break;
> @@ -3690,7 +3768,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> }
> break;
> case 30:
> - switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
> + switch (((inst >> 22) & 0b1111111000) |
> + ((inst >> 12) & 0b0000000111)) {
> case 0: op = rv_op_addd; break;
> case 1: op = rv_op_slld; break;
> case 5: op = rv_op_srld; break;
> --
> 2.25.1
>
>
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