Series comparison

-[PULL 0/5] loongarch-to-apply queue
+[PULL 0/6] loongarch-to-apply queue
-The following changes since commit 8844bb8d896595ee1d25d21c770e6e6f29803097:
+The following changes since commit aa3a285b5bc56a4208b3b57d4a55291e9c260107:
-  Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu into staging (2023-05-13 11:23:14 +0100)
+  Merge tag 'mem-2024-12-21' of https://github.com/davidhildenbrand/qemu into staging (2024-12-22 14:33:27 -0500)
 are available in the Git repository at:
-  https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230515
+  https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20241225
-for you to fetch changes up to 7ef0eb35a4e6961d7e40f03f16ed241c95ae93f9:
+for you to fetch changes up to cb91b7108cb0b3781de9a00994fe78b631d80012:
-  hw/intc: Add NULL pointer check on LoongArch ipi device (2023-05-15 19:09:33 +0800)
+  target/loongarch: Use auto method with LASX feature (2024-12-25 10:33:20 +0800)
 ----------------------------------------------------------------
-pull-loongarch-20230515
+pull-loongarch-20241225
 ----------------------------------------------------------------
-Alexander Bulekov (1):
+Bibo Mao (5):
-      loongarch: mark loongarch_ipi_iocsr re-entrnacy safe
+      target/loongarch: Use actual operand size with vbsrl check
       hw/loongarch/virt: Create fdt table on machine creation done notification
       hw/loongarch/virt: Improve fdt table creation for CPU object
       target/loongarch: Use auto method with LSX feature
       target/loongarch: Use auto method with LASX feature
-Song Gao (4):
+ghy (1):
-      tests/avocado: Add LoongArch machine start test
+      target/loongarch: Fix vldi inst
       hw/loongarch/virt: Modify ipi as percpu device
       hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine
       hw/intc: Add NULL pointer check on LoongArch ipi device
- MAINTAINERS                        |  1 +
+ hw/loongarch/virt.c                             | 142 ++++++++++++++----------
- hw/intc/loongarch_extioi.c         |  4 +-
+ target/loongarch/cpu.c                          |  86 ++++++++------
- hw/intc/loongarch_ipi.c            | 86 +++++++++++++++++++++-----------------
+ target/loongarch/cpu.h                          |   4 +
- hw/intc/trace-events               |  1 +
+ target/loongarch/kvm/kvm.c                      | 107 ++++++++++++++++++
- hw/loongarch/virt.c                | 25 ++++++-----
+ target/loongarch/tcg/insn_trans/trans_vec.c.inc |   4 +-
- include/hw/intc/loongarch_extioi.h | 10 +++--
+files changed, 249 insertions(+), 94 deletions(-)
  include/hw/intc/loongarch_ipi.h    | 10 ++---
  include/hw/loongarch/virt.h        |  3 +-
  tests/avocado/machine_loongarch.py | 58 +++++++++++++++++++++++++
 files changed, 136 insertions(+), 62 deletions(-)
  create mode 100644 tests/avocado/machine_loongarch.py

-New patch
+[PULL 1/6] target/loongarch: Fix vldi inst
+From: ghy <2247883756@qq.com>
+Refer to the link below for a description of the vldi instructions:
+https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88
+Fixed errors in vldi instruction implementation.
+Signed-off-by: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
+Tested-by: Xianglai Li <lixianglai@loongson.cn>
+Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
+Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+---
+ target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
++++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
+@@ -XXX,XX +XXX,XX @@ static uint64_t vldi_get_value(DisasContext *ctx, uint32_t imm)
+         break;
+     case 1:
+         /* data: {2{16'0, imm[7:0], 8'0}} */
+-        data = (t << 24) | (t << 8);
++        data = (t << 40) | (t << 8);
+         break;
+     case 2:
+         /* data: {2{8'0, imm[7:0], 16'0}} */
+--
+.43.5

-[PULL 2/5] tests/avocado: Add LoongArch machine start test
+[PULL 2/6] target/loongarch: Use actual operand size with vbsrl check
-Add a new test in tests/avocado to check LoongArch virt machine start.
+Hardcoded 32 bytes is used for vbsrl emulation check, there is
 problem when options lsx=on,lasx=off is used for vbsrl.v instruction
 in TCG mode. It injects LASX exception rather LSX exception.
-Reviewed-by: Thomas Huth <thuth@redhat.com>
+Here actual operand size is used.
-Signed-off-by: Song Gao <gaosong@loongson.cn>
-Reviewed-by: Cédric Le Goater <clg@redhat.com>
+Cc: qemu-stable@nongnu.org
-Message-Id: <20230513012744.1885728-1-gaosong@loongson.cn>
+Fixes: df97f338076 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve")
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- MAINTAINERS                        |  1 +
+ target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
- tests/avocado/machine_loongarch.py | 58 ++++++++++++++++++++++++++++++
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 59 insertions(+)
  create mode 100644 tests/avocado/machine_loongarch.py
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
-+++ b/MAINTAINERS
++++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
-@@ -XXX,XX +XXX,XX @@ M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+@@ -XXX,XX +XXX,XX @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
- S: Maintained
+ {
- F: target/loongarch/
+     int i, ofs;
- F: tests/tcg/loongarch64/
-+F: tests/avocado/machine_loongarch.py
+-    if (!check_vec(ctx, 32)) {
++    if (!check_vec(ctx, oprsz)) {
- M68K TCG CPUs
+         return true;
- M: Laurent Vivier <laurent@vivier.eu>
+     }
-diff --git a/tests/avocado/machine_loongarch.py b/tests/avocado/machine_loongarch.py
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/avocado/machine_loongarch.py
@@ -XXX,XX +XXX,XX @@
 +# SPDX-License-Identifier: GPL-2.0-or-later
 +#
 +# LoongArch virt test.
 +#
 +# Copyright (c) 2023 Loongson Technology Corporation Limited
 +#
 +
 +from avocado_qemu import QemuSystemTest
 +from avocado_qemu import exec_command_and_wait_for_pattern
 +from avocado_qemu import wait_for_console_pattern
 +
 +class LoongArchMachine(QemuSystemTest):
 +    KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
 +
 +    timeout = 120
 +
 +    def wait_for_console_pattern(self, success_message, vm=None):
 +        wait_for_console_pattern(self, success_message,
 +                                 failure_message='Kernel panic - not syncing',
 +                                 vm=vm)
 +
 +    def test_loongarch64_devices(self):
 +
 +        """
 +        :avocado: tags=arch:loongarch64
 +        :avocado: tags=machine:virt
 +        """
 +
 +        kernel_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
 +                      'releases/download/binary-files/vmlinuz.efi')
 +        kernel_hash = '951b485b16e3788b6db03a3e1793c067009e31a2'
 +        kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 +
 +        initrd_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
 +                      'releases/download/binary-files/ramdisk')
 +        initrd_hash = 'c67658d9b2a447ce7db2f73ba3d373c9b2b90ab2'
 +        initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
 +
 +        bios_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
 +                    'releases/download/binary-files/QEMU_EFI.fd')
 +        bios_hash = ('dfc1bfba4853cd763b9d392d0031827e8addbca8')
 +        bios_path = self.fetch_asset(bios_url, asset_hash=bios_hash)
 +
 +        self.vm.set_console()
 +        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
 +                               'root=/dev/ram rdinit=/sbin/init console=ttyS0,115200')
 +        self.vm.add_args('-nographic',
 +                         '-smp', '4',
 +                         '-m', '1024',
 +                         '-cpu', 'la464',
 +                         '-kernel', kernel_path,
 +                         '-initrd', initrd_path,
 +                         '-bios', bios_path,
 +                         '-append', kernel_command_line)
 +        self.vm.launch()
 +        self.wait_for_console_pattern('Run /sbin/init as init process')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
 +                                          'processor        : 3')
 --
-.39.1
+.43.5

-[PULL 3/5] hw/loongarch/virt: Modify ipi as percpu device
+[PULL 3/6] hw/loongarch/virt: Create fdt table on machine creation done notification
-ipi is used to communicate between cpus, this patch modified
+The same with ACPI table, fdt table is created on machine done
-loongarch ipi device as percpu device, so that there are
+notification. Some objects like CPU objects can be created with cold-plug
-MemoryRegions with ipi device, rather than 2*cpus
+method with command such as -smp x, -device la464-loongarch-cpu, so all
-MemoryRegions, which may be large than QDEV_MAX_MMIO if
+objects finish to create when machine is done.
 more cpus are added on loongarch virt machine.
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
+Reviewed-by: Bibo Mao <maobibo@loongson.cn>
 Message-Id: <20230512100421.1867848-2-gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c         | 44 ++++++++++++---------------------
+ hw/loongarch/virt.c | 103 ++++++++++++++++++++++++--------------------
- hw/loongarch/virt.c             | 12 ++++-----
+file changed, 57 insertions(+), 46 deletions(-)
  include/hw/intc/loongarch_ipi.h | 10 +++-----
  include/hw/loongarch/virt.h     |  1 -
 files changed, 26 insertions(+), 41 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
-+++ b/hw/intc/loongarch_ipi.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_ipi64_ops = {
- static void loongarch_ipi_init(Object *obj)
- {
--    int cpu;
--    LoongArchMachineState *lams;
-     LoongArchIPI *s = LOONGARCH_IPI(obj);
-     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
--    Object *machine = qdev_get_machine();
--    ObjectClass *mc = object_get_class(machine);
--    /* 'lams' should be initialized */
--    if (!strcmp(MACHINE_CLASS(mc)->name, "none")) {
--        return;
--    }
--    lams = LOONGARCH_MACHINE(machine);
--    for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
--        memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
--                            &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
--        /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
--        s->ipi_iocsr_mem[cpu].disable_reentrancy_guard = true;
-+    memory_region_init_io(&s->ipi_iocsr_mem, obj, &loongarch_ipi_ops,
-+                          &s->ipi_core, "loongarch_ipi_iocsr", 0x48);
--        sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
-+    /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
-+    s->ipi_iocsr_mem.disable_reentrancy_guard = true;
--        memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
--                              &lams->ipi_core[cpu], "loongarch_ipi64_iocsr", 0x118);
--        sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem[cpu]);
--        qdev_init_gpio_out(DEVICE(obj), &lams->ipi_core[cpu].irq, 1);
--    }
-+    sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
-+
-+    memory_region_init_io(&s->ipi64_iocsr_mem, obj, &loongarch_ipi64_ops,
-+                          &s->ipi_core, "loongarch_ipi64_iocsr", 0x118);
-+    sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
-+    qdev_init_gpio_out(DEVICE(obj), &s->ipi_core.irq, 1);
- }
- static const VMStateDescription vmstate_ipi_core = {
-     .name = "ipi-single",
--    .version_id = 0,
--    .minimum_version_id = 0,
-+    .version_id = 1,
-+    .minimum_version_id = 1,
-     .fields = (VMStateField[]) {
-         VMSTATE_UINT32(status, IPICore),
-         VMSTATE_UINT32(en, IPICore),
-         VMSTATE_UINT32(set, IPICore),
-         VMSTATE_UINT32(clear, IPICore),
--        VMSTATE_UINT32_ARRAY(buf, IPICore, MAX_IPI_MBX_NUM * 2),
-+        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
-         VMSTATE_END_OF_LIST()
-     }
- };
- static const VMStateDescription vmstate_loongarch_ipi = {
-     .name = TYPE_LOONGARCH_IPI,
--    .version_id = 0,
--    .minimum_version_id = 0,
-+    .version_id = 1,
-+    .minimum_version_id = 1,
-     .fields = (VMStateField[]) {
--        VMSTATE_STRUCT_ARRAY(ipi_core, LoongArchMachineState,
--                             MAX_IPI_CORE_NUM, 0,
--                             vmstate_ipi_core, IPICore),
-+        VMSTATE_STRUCT(ipi_core, LoongArchIPI, 0, vmstate_ipi_core, IPICore),
-         VMSTATE_END_OF_LIST()
-     }
- };
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/loongarch/virt.c
 +++ b/hw/loongarch/virt.c
-@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
+@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(LoongArchVirtMachineState *lvms)
      }
  }
 +static void virt_fdt_setup(LoongArchVirtMachineState *lvms)
 +{
 +    MachineState *machine = MACHINE(lvms);
 +    uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
 +    int i;
 +
 +    create_fdt(lvms);
 +    fdt_add_cpu_nodes(lvms);
 +    fdt_add_memory_nodes(machine);
 +    fdt_add_fw_cfg_node(lvms);
 +    fdt_add_flash_node(lvms);
 +
 +    /* Add cpu interrupt-controller */
 +    fdt_add_cpuic_node(lvms, &cpuintc_phandle);
 +    /* Add Extend I/O Interrupt Controller node */
 +    fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
 +    /* Add PCH PIC node */
 +    fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
 +    /* Add PCH MSI node */
 +    fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
 +    /* Add pcie node */
 +    fdt_add_pcie_node(lvms, &pch_pic_phandle, &pch_msi_phandle);
 +
 +    /*
 +     * Create uart fdt node in reverse order so that they appear
 +     * in the finished device tree lowest address first
 +     */
 +    for (i = VIRT_UART_COUNT; i-- > 0;) {
 +        hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
 +        int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
 +        fdt_add_uart_node(lvms, &pch_pic_phandle, base, irq, i == 0);
 +    }
 +
 +    fdt_add_rtc_node(lvms, &pch_pic_phandle);
 +    fdt_add_ged_reset(lvms);
 +    platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
 +                                   VIRT_PLATFORM_BUS_BASEADDRESS,
 +                                   VIRT_PLATFORM_BUS_SIZE,
 +                                   VIRT_PLATFORM_BUS_IRQ);
 +
 +    /*
 +     * Since lowmem region starts from 0 and Linux kernel legacy start address
 +     * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
 +     * access. FDT size limit with 1 MiB.
 +     * Put the FDT into the memory map as a ROM image: this will ensure
 +     * the FDT is copied again upon reset, even if addr points into RAM.
 +     */
 +    qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
 +    rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
 +                          &address_space_memory);
 +    qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
 +            rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
 +}
 +
  static void virt_done(Notifier *notifier, void *data)
  {
      LoongArchVirtMachineState *lvms = container_of(notifier,
                                        LoongArchVirtMachineState, machine_done);
      virt_build_smbios(lvms);
      loongarch_acpi_setup(lvms);
 +    virt_fdt_setup(lvms);
  }
  static void virt_powerdown_req(Notifier *notifier, void *opaque)
@@ -XXX,XX +XXX,XX @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
  }
  static void virt_devices_init(DeviceState *pch_pic,
 -                                   LoongArchVirtMachineState *lvms,
 -                                   uint32_t *pch_pic_phandle,
 -                                   uint32_t *pch_msi_phandle)
 +                                   LoongArchVirtMachineState *lvms)
  {
      MachineClass *mc = MACHINE_GET_CLASS(lvms);
      DeviceState *gpex_dev;
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
          gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
      }
 -    /* Add pcie node */
 -    fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
 -
      /*
       * Create uart fdt node in reverse order so that they appear
       * in the finished device tree lowest address first
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
          serial_mm_init(get_system_memory(), base, 0,
                         qdev_get_gpio_in(pch_pic, irq),
 , serial_hd(i), DEVICE_LITTLE_ENDIAN);
 -        fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
      }
      /* Network init */
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
      sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
                           qdev_get_gpio_in(pch_pic,
                           VIRT_RTC_IRQ - VIRT_GSI_BASE));
 -    fdt_add_rtc_node(lvms, pch_pic_phandle);
 -    fdt_add_ged_reset(lvms);
      /* acpi ged */
      lvms->acpi_ged = create_acpi_ged(pch_pic, lvms);
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
      CPULoongArchState *env;
      CPUState *cpu_state;
      int cpu, pin, i, start, num;
+-    uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
--    ipi = qdev_new(TYPE_LOONGARCH_IPI);
--    sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
+     /*
--
+      * Extended IRQ model.
-     extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
+@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
-     sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
+     memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
+                    sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
-@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
-         lacpu = LOONGARCH_CPU(cpu_state);
+-    /* Add cpu interrupt-controller */
-         env = &(lacpu->env);
+-    fdt_add_cpuic_node(lvms, &cpuintc_phandle);
+-
-+        ipi = qdev_new(TYPE_LOONGARCH_IPI);
+     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
-+        sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
+         cpu_state = qemu_get_cpu(cpu);
-+
+         cpudev = DEVICE(cpu_state);
-         /* connect ipi irq to cpu irq */
+@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
--        qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
+         }
-+        qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI));
+     }
-         /* IPI iocsr memory region */
-         memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
+-    /* Add Extend I/O Interrupt Controller node */
-                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+-    fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
--                                    cpu * 2));
+-
-+                                    0));
+     pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
-         memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
+     num = VIRT_PCH_PIC_IRQ_NUM;
-                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+     qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
--                                    cpu * 2 + 1));
+@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
-+                                    1));
+         qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
-         /* extioi iocsr memory region */
+     }
-         memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
-                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
+-    /* Add PCH PIC node */
-diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
+-    fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
-index XXXXXXX..XXXXXXX 100644
+-
---- a/include/hw/intc/loongarch_ipi.h
+     pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
-+++ b/include/hw/intc/loongarch_ipi.h
+     start   =  num;
-@@ -XXX,XX +XXX,XX @@
+     num = EXTIOI_IRQS - start;
- #define MAIL_SEND_OFFSET      0
+@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
- #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
+                               qdev_get_gpio_in(extioi, i + start));
+     }
--#define MAX_IPI_CORE_NUM      4
--#define MAX_IPI_MBX_NUM       4
+-    /* Add PCH MSI node */
--
+-    fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
- #define TYPE_LOONGARCH_IPI "loongarch_ipi"
+-
- OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
+-    virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle);
++    virt_devices_init(pch_pic, lvms);
-@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
+ }
-     uint32_t set;
-     uint32_t clear;
+ static void virt_firmware_init(LoongArchVirtMachineState *lvms)
-     /* 64bit buf divide into 2 32bit buf */
+@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
--    uint32_t buf[MAX_IPI_MBX_NUM * 2];
+         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
-+    uint32_t buf[2];
+     }
-     qemu_irq irq;
- } IPICore;
+-    create_fdt(lvms);
+-
- struct LoongArchIPI {
+     /* Create IOCSR space */
-     SysBusDevice parent_obj;
+     memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL,
--    MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM];
+                           machine, "iocsr", UINT64_MAX);
--    MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM];
+@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
-+    MemoryRegion ipi_iocsr_mem;
+         lacpu = LOONGARCH_CPU(cpu);
-+    MemoryRegion ipi64_iocsr_mem;
+         lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
-+    IPICore ipi_core;
+     }
- };
+-    fdt_add_cpu_nodes(lvms);
+-    fdt_add_memory_nodes(machine);
- #endif
+     fw_cfg_add_memory(machine);
-diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
-index XXXXXXX..XXXXXXX 100644
+     /* Node0 memory */
---- a/include/hw/loongarch/virt.h
+@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
-+++ b/include/hw/loongarch/virt.h
+                         memmap_table,
-@@ -XXX,XX +XXX,XX @@ struct LoongArchMachineState {
+                         sizeof(struct memmap_entry) * (memmap_entries));
-     /*< private >*/
+     }
-     MachineState parent_obj;
+-    fdt_add_fw_cfg_node(lvms);
+-    fdt_add_flash_node(lvms);
--    IPICore ipi_core[MAX_IPI_CORE_NUM];
-     MemoryRegion lowmem;
+     /* Initialize the IO interrupt subsystem */
-     MemoryRegion highmem;
+     virt_irq_init(lvms);
-     MemoryRegion isa_io;
+-    platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
 -                                   VIRT_PLATFORM_BUS_BASEADDRESS,
 -                                   VIRT_PLATFORM_BUS_SIZE,
 -                                   VIRT_PLATFORM_BUS_IRQ);
      lvms->machine_done.notify = virt_done;
      qemu_add_machine_init_done_notifier(&lvms->machine_done);
       /* connect powerdown request */
      lvms->powerdown_notifier.notify = virt_powerdown_req;
      qemu_register_powerdown_notifier(&lvms->powerdown_notifier);
 -    /*
 -     * Since lowmem region starts from 0 and Linux kernel legacy start address
 -     * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
 -     * access. FDT size limit with 1 MiB.
 -     * Put the FDT into the memory map as a ROM image: this will ensure
 -     * the FDT is copied again upon reset, even if addr points into RAM.
 -     */
 -    qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
 -    rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
 -                          &address_space_memory);
 -    qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
 -            rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
 -
      lvms->bootinfo.ram_size = ram_size;
      loongarch_load_kernel(machine, &lvms->bootinfo);
  }
 --
-.39.1
+.43.5

-[PULL 4/5] hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine
+[PULL 4/6] hw/loongarch/virt: Improve fdt table creation for CPU object
-Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi
+For CPU object, possible_cpu_arch_ids() function is used rather than
-only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that
+smp.cpus. With command -smp x, -device la464-loongarch-cpu, smp.cpus
-loongarch virt machine supports more cpus.
+is not accurate for all possible CPU objects, possible_cpu_arch_ids()
 is used here.
-Interrupts from external devices can only be routed cpu 0-3 because
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-of extioi limits, cpu internal interrupt such as timer/ipi can be
+Reviewed-by: Bibo Mao <maobibo@loongson.cn>
-triggered on all cpus.
+---
  hw/loongarch/virt.c | 39 +++++++++++++++++++++++++--------------
 file changed, 25 insertions(+), 14 deletions(-)
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20230512100421.1867848-3-gaosong@loongson.cn>
----
- hw/intc/loongarch_extioi.c         |  4 ++--
- hw/loongarch/virt.c                | 13 +++++++++----
- include/hw/intc/loongarch_extioi.h | 10 ++++++----
- include/hw/loongarch/virt.h        |  2 +-
-files changed, 18 insertions(+), 11 deletions(-)
-diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_extioi.c
-+++ b/hw/intc/loongarch_extioi.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_extioi = {
-     .minimum_version_id = 1,
-     .fields = (VMStateField[]) {
-         VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
--        VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, LOONGARCH_MAX_VCPUS,
-+        VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, EXTIOI_CPUS,
-                                EXTIOI_IRQS_GROUP_COUNT),
-         VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
-                              EXTIOI_IRQS_NODETYPE_COUNT / 2),
-@@ -XXX,XX +XXX,XX @@ static void loongarch_extioi_instance_init(Object *obj)
-     qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
--    for (cpu = 0; cpu < LOONGARCH_MAX_VCPUS; cpu++) {
-+    for (cpu = 0; cpu < EXTIOI_CPUS; cpu++) {
-         memory_region_init_io(&s->extioi_iocsr_mem[cpu], OBJECT(s), &extioi_ops,
-                               s, "extioi_iocsr", 0x900);
-         sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_iocsr_mem[cpu]);
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/loongarch/virt.c
 +++ b/hw/loongarch/virt.c
-@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(LoongArchVirtMachineState *lvms)
-         memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
+ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
-                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+ {
-));
+     int num;
--        /* extioi iocsr memory region */
+-    const MachineState *ms = MACHINE(lvms);
--        memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
+-    int smp_cpus = ms->smp.cpus;
-+        /*
++    MachineState *ms = MACHINE(lvms);
-+     * extioi iocsr memory region
++    MachineClass *mc = MACHINE_GET_CLASS(ms);
-+     * only one extioi is added on loongarch virt machine
++    const CPUArchIdList *possible_cpus;
-+     * external device interrupt can only be routed to cpu 0-3
++    LoongArchCPU *cpu;
-+     */
++    CPUState *cs;
-+    if (cpu < EXTIOI_CPUS)
++    char *nodename, *map_path;
-+            memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
-                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
+     qemu_fdt_add_subnode(ms->fdt, "/cpus");
-                                 cpu));
+     qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
      qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
      /* cpu nodes */
 -    for (num = smp_cpus - 1; num >= 0; num--) {
 -        char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
 -        LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
 -        CPUState *cs = CPU(cpu);
 +    possible_cpus = mc->possible_cpu_arch_ids(ms);
 +    for (num = 0; num < possible_cpus->len; num++) {
 +        cs = possible_cpus->cpus[num].cpu;
 +        if (cs == NULL) {
 +            continue;
 +        }
 +
 +        nodename = g_strdup_printf("/cpus/cpu@%d", num);
 +        cpu = LOONGARCH_CPU(cs);
          qemu_fdt_add_subnode(ms->fdt, nodename);
          qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
          qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
                                  cpu->dtb_compatible);
 -        if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
 +        if (possible_cpus->cpus[num].props.has_node_id) {
              qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
 -                ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
 +                possible_cpus->cpus[num].props.node_id);
          }
          qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
          qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
      /*cpu map */
      qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
 +    for (num = 0; num < possible_cpus->len; num++) {
 +        cs = possible_cpus->cpus[num].cpu;
 +        if (cs == NULL) {
 +            continue;
 +        }
 -    for (num = smp_cpus - 1; num >= 0; num--) {
 -        char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
 -        char *map_path;
 -
 +        nodename = g_strdup_printf("/cpus/cpu@%d", num);
          if (ms->smp.threads > 1) {
              map_path = g_strdup_printf(
                  "/cpus/cpu-map/socket%d/core%d/thread%d",
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
                  num % ms->smp.cores);
          }
          qemu_fdt_add_path(ms->fdt, map_path);
 -        qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
 +        qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", nodename);
          g_free(map_path);
 -        g_free(cpu_path);
 +        g_free(nodename);
      }
-@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
+ }
-      * connect ext irq to the cpu irq
       * cpu_pin[9:2] <= intc_pin[7:0]
       */
 -    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 +    for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) {
          cpudev = DEVICE(qemu_get_cpu(cpu));
          for (pin = 0; pin < LS3A_INTC_IP; pin++) {
              qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
      mc->default_ram_size = 1 * GiB;
      mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
      mc->default_ram_id = "loongarch.ram";
 -    mc->max_cpus = LOONGARCH_MAX_VCPUS;
 +    mc->max_cpus = LOONGARCH_MAX_CPUS;
      mc->is_default = 1;
      mc->default_kernel_irqchip_split = false;
      mc->block_default_type = IF_VIRTIO;
 diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/intc/loongarch_extioi.h
 +++ b/include/hw/intc/loongarch_extioi.h
@@ -XXX,XX +XXX,XX @@
  #define LS3A_INTC_IP               8
  #define EXTIOI_IRQS                (256)
  #define EXTIOI_IRQS_BITMAP_SIZE    (256 / 8)
 +/* irq from EXTIOI is routed to no more than 4 cpus */
 +#define EXTIOI_CPUS                (4)
  /* map to ipnum per 32 irqs */
  #define EXTIOI_IRQS_IPMAP_SIZE     (256 / 32)
  #define EXTIOI_IRQS_COREMAP_SIZE   256
@@ -XXX,XX +XXX,XX @@ struct LoongArchExtIOI {
      uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
      uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
      uint32_t isr[EXTIOI_IRQS / 32];
 -    uint32_t coreisr[LOONGARCH_MAX_VCPUS][EXTIOI_IRQS_GROUP_COUNT];
 +    uint32_t coreisr[EXTIOI_CPUS][EXTIOI_IRQS_GROUP_COUNT];
      uint32_t enable[EXTIOI_IRQS / 32];
      uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
      uint32_t coremap[EXTIOI_IRQS / 4];
      uint32_t sw_pending[EXTIOI_IRQS / 32];
 -    DECLARE_BITMAP(sw_isr[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP], EXTIOI_IRQS);
 +    DECLARE_BITMAP(sw_isr[EXTIOI_CPUS][LS3A_INTC_IP], EXTIOI_IRQS);
      uint8_t  sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
      uint8_t  sw_coremap[EXTIOI_IRQS];
 -    qemu_irq parent_irq[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP];
 +    qemu_irq parent_irq[EXTIOI_CPUS][LS3A_INTC_IP];
      qemu_irq irq[EXTIOI_IRQS];
 -    MemoryRegion extioi_iocsr_mem[LOONGARCH_MAX_VCPUS];
 +    MemoryRegion extioi_iocsr_mem[EXTIOI_CPUS];
      MemoryRegion extioi_system_mem;
  };
  #endif /* LOONGARCH_EXTIOI_H */
 diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/loongarch/virt.h
 +++ b/include/hw/loongarch/virt.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/intc/loongarch_ipi.h"
  #include "hw/block/flash.h"
 -#define LOONGARCH_MAX_VCPUS     4
 +#define LOONGARCH_MAX_CPUS      256
  #define VIRT_ISA_IO_BASE        0x18000000UL
  #define VIRT_ISA_IO_SIZE        0x0004000
 --
-.39.1
+.43.5

-[PULL 1/5] loongarch: mark loongarch_ipi_iocsr re-entrnacy safe
+[PULL 5/6] target/loongarch: Use auto method with LSX feature
-From: Alexander Bulekov <alxndr@bu.edu>
+Like LBT feature, add type OnOffAuto for LSX feature setting. Also
 add LSX feature detection with new VM ioctl command, fallback to old
 method if it is not supported.
-loongarch_ipi_iocsr MRs rely on re-entrant IO through the ipi_send
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-function. As such, mark these MRs re-entrancy-safe.
+Reviewed-by: Bibo Mao <maobibo@loongson.cn>
 ---
  target/loongarch/cpu.c     | 38 +++++++++++++++------------
  target/loongarch/cpu.h     |  2 ++
  target/loongarch/kvm/kvm.c | 54 ++++++++++++++++++++++++++++++++++++++
 files changed, 77 insertions(+), 17 deletions(-)
-Fixes: a2e1753b80 ("memory: prevent dma-reentracy issues")
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 Signed-off-by: Alexander Bulekov <alxndr@bu.edu>
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20230506112145.3563708-1-alxndr@bu.edu>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
  hw/intc/loongarch_ipi.c | 4 ++++
 file changed, 4 insertions(+)
 diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/target/loongarch/cpu.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
-     for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
+ {
-         memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
+     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-                             &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
+     CPULoongArchState *env = &cpu->env;
-+
++    uint32_t data = 0;
-+        /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
+     int i;
-+        s->ipi_iocsr_mem[cpu].disable_reentrancy_guard = true;
-+
+     for (i = 0; i < 21; i++) {
-         sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
+@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
+     cpu->dtb_compatible = "loongarch,Loongson-3A5000";
-         memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
+     env->cpucfg[0] = 0x14c010;  /* PRID */
 -    uint32_t data = 0;
      data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
      data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
      data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
  {
      LoongArchCPU *cpu = LOONGARCH_CPU(obj);
      CPULoongArchState *env = &cpu->env;
 -
 +    uint32_t data = 0;
      int i;
      for (i = 0; i < 21; i++) {
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
      cpu->dtb_compatible = "loongarch,Loongson-1C103";
      env->cpucfg[0] = 0x148042;  /* PRID */
 -    uint32_t data = 0;
      data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
      data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
      data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
  static bool loongarch_get_lsx(Object *obj, Error **errp)
  {
 -    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 -    bool ret;
 -
 -    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
 -        ret = true;
 -    } else {
 -        ret = false;
 -    }
 -    return ret;
 +    return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
  }
  static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
  {
      LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 +    uint32_t val;
 -    if (value) {
 -        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
 -    } else {
 -        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0);
 -        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
 +    cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
 +    if (kvm_enabled()) {
 +        /* kvm feature detection in function kvm_arch_init_vcpu */
 +        return;
      }
 +
 +    /* LSX feature detection in TCG mode */
 +    val = cpu->env.cpucfg[2];
 +    if (cpu->lsx == ON_OFF_AUTO_ON) {
 +        if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
 +            error_setg(errp, "Failed to enable LSX in TCG mode");
 +            return;
 +        }
 +    }
 +
 +    cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
  }
  static bool loongarch_get_lasx(Object *obj, Error **errp)
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
  {
      LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 +    cpu->lsx = ON_OFF_AUTO_AUTO;
      object_property_add_bool(obj, "lsx", loongarch_get_lsx,
                               loongarch_set_lsx);
      object_property_add_bool(obj, "lasx", loongarch_get_lasx,
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
      } else {
          cpu->lbt = ON_OFF_AUTO_OFF;
 +        cpu->pmu = ON_OFF_AUTO_OFF;
      }
  }
 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/cpu.h
 +++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
  #endif
  enum loongarch_features {
 +    LOONGARCH_FEATURE_LSX,
      LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
      LOONGARCH_FEATURE_PMU,
  };
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      uint32_t  phy_id;
      OnOffAuto lbt;
      OnOffAuto pmu;
 +    OnOffAuto lsx;
      /* 'compatible' string for this CPU for Linux device trees */
      const char *dtb_compatible;
 diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/kvm/kvm.c
 +++ b/target/loongarch/kvm/kvm.c
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
  {
      int ret;
      struct kvm_device_attr attr;
 +    uint64_t val;
      switch (feature) {
 +    case LOONGARCH_FEATURE_LSX:
 +        attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
 +        attr.attr = KVM_LOONGARCH_VM_FEAT_LSX;
 +        ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
 +        if (ret == 0) {
 +            return true;
 +        }
 +
 +        /* Fallback to old kernel detect interface */
 +        val = 0;
 +        attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
 +        /* Cpucfg2 */
 +        attr.attr  = 2;
 +        attr.addr = (uint64_t)&val;
 +        ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
 +        if (!ret) {
 +            ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
 +            if (ret) {
 +                return false;
 +            }
 +
 +            ret = FIELD_EX32((uint32_t)val, CPUCFG2, LSX);
 +            return (ret != 0);
 +        }
 +        return false;
 +
      case LOONGARCH_FEATURE_LBT:
          /*
           * Return all if all the LBT features are supported such as:
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
      return false;
  }
 +static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
 +{
 +    CPULoongArchState *env = cpu_env(cs);
 +    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
 +    bool kvm_supported;
 +
 +    kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LSX);
 +    env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 0);
 +    if (cpu->lsx == ON_OFF_AUTO_ON) {
 +        if (kvm_supported) {
 +            env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
 +        } else {
 +            error_setg(errp, "'lsx' feature not supported by KVM on this host");
 +            return -ENOTSUP;
 +        }
 +    } else if ((cpu->lsx == ON_OFF_AUTO_AUTO) && kvm_supported) {
 +        env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
 +    }
 +
 +    return 0;
 +}
 +
  static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
  {
      CPULoongArchState *env = cpu_env(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
          brk_insn = val;
      }
 +    ret = kvm_cpu_check_lsx(cs, &local_err);
 +    if (ret < 0) {
 +        error_report_err(local_err);
 +    }
 +
      ret = kvm_cpu_check_lbt(cs, &local_err);
      if (ret < 0) {
          error_report_err(local_err);
 --
-.39.1
+.43.5

-[PULL 5/5] hw/intc: Add NULL pointer check on LoongArch ipi device
+[PULL 6/6] target/loongarch: Use auto method with LASX feature
-When ipi mailbox is used, cpu_index is decoded from iocsr register.
+Like LSX feature, add type OnOffAuto for LASX feature setting.
 cpu maybe does not exist. This patch adds NULL pointer check on
 ipi device.
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bibo Mao <maobibo@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20230512100421.1867848-4-gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c | 40 +++++++++++++++++++++++++++++-----------
+ target/loongarch/cpu.c     | 50 +++++++++++++++++++++++------------
- hw/intc/trace-events    |  1 +
+ target/loongarch/cpu.h     |  2 ++
-files changed, 30 insertions(+), 11 deletions(-)
+ target/loongarch/kvm/kvm.c | 53 ++++++++++++++++++++++++++++++++++++++
 files changed, 89 insertions(+), 16 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/target/loongarch/cpu.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
+@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
+     uint32_t val;
- static void ipi_send(uint64_t val)
      cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
 +    if (cpu->lsx == ON_OFF_AUTO_OFF) {
 +        cpu->lasx = ON_OFF_AUTO_OFF;
 +        if (cpu->lasx == ON_OFF_AUTO_ON) {
 +            error_setg(errp, "Failed to disable LSX since LASX is enabled");
 +            return;
 +        }
 +    }
 +
      if (kvm_enabled()) {
          /* kvm feature detection in function kvm_arch_init_vcpu */
          return;
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
              error_setg(errp, "Failed to enable LSX in TCG mode");
              return;
          }
 +    } else {
 +        cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
 +        val = cpu->env.cpucfg[2];
      }
      cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
  static bool loongarch_get_lasx(Object *obj, Error **errp)
  {
--    int cpuid, data;
+-    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-+    uint32_t cpuid;
+-    bool ret;
-+    uint8_t vector;
+-
-     CPULoongArchState *env;
+-    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
-     CPUState *cs;
+-        ret = true;
-     LoongArchCPU *cpu;
+-    } else {
+-        ret = false;
--    cpuid = (val >> 16) & 0x3ff;
+-    }
-+    cpuid = extract32(val, 16, 10);
+-    return ret;
-+    if (cpuid >= LOONGARCH_MAX_CPUS) {
++    return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
-+        trace_loongarch_ipi_unsupported_cpuid("IOCSR_IPI_SEND", cpuid);
+ }
  static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
  {
      LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 +    uint32_t val;
 -    if (value) {
 -    if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
 -            cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
 -    }
 -        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1);
 -    } else {
 -        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
 +    cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
 +    if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
 +        error_setg(errp, "Failed to enable LASX since lSX is disabled");
 +        return;
 +    }
 +
-     /* IPI status vector */
++    if (kvm_enabled()) {
--    data = 1 << (val & 0x1f);
++        /* kvm feature detection in function kvm_arch_init_vcpu */
-+    vector = extract8(val, 0, 5);
++        return;
      }
 +
-     cs = qemu_get_cpu(cpuid);
++    /* LASX feature detection in TCG mode */
-     cpu = LOONGARCH_CPU(cs);
++    val = cpu->env.cpucfg[2];
-     env = &cpu->env;
++    if (cpu->lasx == ON_OFF_AUTO_ON) {
-     address_space_stl(&env->address_space_iocsr, 0x1008,
++        if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
--                      data, MEMTXATTRS_UNSPECIFIED, NULL);
++            error_setg(errp, "Failed to enable LASX in TCG mode");
--
++            return;
-+                      BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);
++        }
  }
  static void mail_send(uint64_t val)
  {
 -    int cpuid;
 +    uint32_t cpuid;
      hwaddr addr;
      CPULoongArchState *env;
      CPUState *cs;
      LoongArchCPU *cpu;
 -    cpuid = (val >> 16) & 0x3ff;
 +    cpuid = extract32(val, 16, 10);
 +    if (cpuid >= LOONGARCH_MAX_CPUS) {
 +        trace_loongarch_ipi_unsupported_cpuid("IOCSR_MAIL_SEND", cpuid);
 +        return;
 +    }
 +
-     addr = 0x1020 + (val & 0x1c);
++    cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
-     cs = qemu_get_cpu(cpuid);
+ }
-     cpu = LOONGARCH_CPU(cs);
-@@ -XXX,XX +XXX,XX @@ static void mail_send(uint64_t val)
+ static bool loongarch_get_lbt(Object *obj, Error **errp)
+@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
- static void any_send(uint64_t val)
+     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
      cpu->lsx = ON_OFF_AUTO_AUTO;
 +    cpu->lasx = ON_OFF_AUTO_AUTO;
      object_property_add_bool(obj, "lsx", loongarch_get_lsx,
                               loongarch_set_lsx);
      object_property_add_bool(obj, "lasx", loongarch_get_lasx,
 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/cpu.h
 +++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
  enum loongarch_features {
      LOONGARCH_FEATURE_LSX,
 +    LOONGARCH_FEATURE_LASX,
      LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
      LOONGARCH_FEATURE_PMU,
  };
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      OnOffAuto lbt;
      OnOffAuto pmu;
      OnOffAuto lsx;
 +    OnOffAuto lasx;
      /* 'compatible' string for this CPU for Linux device trees */
      const char *dtb_compatible;
 diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/kvm/kvm.c
 +++ b/target/loongarch/kvm/kvm.c
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
          }
          return false;
 +    case LOONGARCH_FEATURE_LASX:
 +        attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
 +        attr.attr = KVM_LOONGARCH_VM_FEAT_LASX;
 +        ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
 +        if (ret == 0) {
 +            return true;
 +        }
 +
 +        /* Fallback to old kernel detect interface */
 +        val = 0;
 +        attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
 +        /* Cpucfg2 */
 +        attr.attr  = 2;
 +        attr.addr = (uint64_t)&val;
 +        ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
 +        if (!ret) {
 +            ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
 +            if (ret) {
 +                return false;
 +            }
 +
 +            ret = FIELD_EX32((uint32_t)val, CPUCFG2, LASX);
 +            return (ret != 0);
 +        }
 +        return false;
 +
      case LOONGARCH_FEATURE_LBT:
          /*
           * Return all if all the LBT features are supported such as:
@@ -XXX,XX +XXX,XX @@ static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
      return 0;
  }
 +static int kvm_cpu_check_lasx(CPUState *cs, Error **errp)
 +{
 +    CPULoongArchState *env = cpu_env(cs);
 +    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
 +    bool kvm_supported;
 +
 +    kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LASX);
 +    env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 0);
 +    if (cpu->lasx == ON_OFF_AUTO_ON) {
 +        if (kvm_supported) {
 +            env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
 +        } else {
 +            error_setg(errp, "'lasx' feature not supported by KVM on host");
 +            return -ENOTSUP;
 +        }
 +    } else if ((cpu->lasx == ON_OFF_AUTO_AUTO) && kvm_supported) {
 +        env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
 +    }
 +
 +    return 0;
 +}
 +
  static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
  {
--    int cpuid;
+     CPULoongArchState *env = cpu_env(cs);
-+    uint32_t cpuid;
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
-     hwaddr addr;
+         error_report_err(local_err);
-     CPULoongArchState *env;
+     }
-+    CPUState *cs;
-+    LoongArchCPU *cpu;
++    ret = kvm_cpu_check_lasx(cs, &local_err);
 +    if (ret < 0) {
 +        error_report_err(local_err);
 +    }
 +
-+    cpuid = extract32(val, 16, 10);
+     ret = kvm_cpu_check_lbt(cs, &local_err);
-+    if (cpuid >= LOONGARCH_MAX_CPUS) {
+     if (ret < 0) {
-+        trace_loongarch_ipi_unsupported_cpuid("IOCSR_ANY_SEND", cpuid);
+         error_report_err(local_err);
 +        return;
 +    }
 -    cpuid = (val >> 16) & 0x3ff;
      addr = val & 0xffff;
 -    CPUState *cs = qemu_get_cpu(cpuid);
 -    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
 +    cs = qemu_get_cpu(cpuid);
 +    cpu = LOONGARCH_CPU(cs);
      env = &cpu->env;
      send_ipi_data(env, val, addr);
  }
 diff --git a/hw/intc/trace-events b/hw/intc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/trace-events
 +++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
  # loongarch_ipi.c
  loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
  loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
 +loongarch_ipi_unsupported_cpuid(const char *s, uint32_t cpuid) "%s unsupported cpuid 0x%" PRIx32
  # loongarch_pch_pic.c
  loongarch_pch_pic_irq_handler(int irq, int level) "irq %d level %d"
 --
-.39.1
+.43.5

The following changes since commit 8844bb8d896595ee1d25d21c770e6e6f29803097:

Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu into staging (2023-05-13 11:23:14 +0100)

are available in the Git repository at:

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230515

for you to fetch changes up to 7ef0eb35a4e6961d7e40f03f16ed241c95ae93f9:

hw/intc: Add NULL pointer check on LoongArch ipi device (2023-05-15 19:09:33 +0800)

----------------------------------------------------------------
pull-loongarch-20230515

----------------------------------------------------------------
Alexander Bulekov (1):
      loongarch: mark loongarch_ipi_iocsr re-entrnacy safe

Song Gao (4):
      tests/avocado: Add LoongArch machine start test
      hw/loongarch/virt: Modify ipi as percpu device
      hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine
      hw/intc: Add NULL pointer check on LoongArch ipi device

MAINTAINERS                        |  1 +
 hw/intc/loongarch_extioi.c         |  4 +-
 hw/intc/loongarch_ipi.c            | 86 +++++++++++++++++++++-----------------
 hw/intc/trace-events               |  1 +
 hw/loongarch/virt.c                | 25 ++++++-----
 include/hw/intc/loongarch_extioi.h | 10 +++--
 include/hw/intc/loongarch_ipi.h    | 10 ++---
 include/hw/loongarch/virt.h        |  3 +-
 tests/avocado/machine_loongarch.py | 58 +++++++++++++++++++++++++
 9 files changed, 136 insertions(+), 62 deletions(-)
 create mode 100644 tests/avocado/machine_loongarch.py

From: Alexander Bulekov <alxndr@bu.edu>

loongarch_ipi_iocsr MRs rely on re-entrant IO through the ipi_send
function. As such, mark these MRs re-entrancy-safe.

Fixes: a2e1753b80 ("memory: prevent dma-reentracy issues")
Signed-off-by: Alexander Bulekov <alxndr@bu.edu>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230506112145.3563708-1-alxndr@bu.edu>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_ipi.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
     for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
         memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
                             &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
+
+        /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
+        s->ipi_iocsr_mem[cpu].disable_reentrancy_guard = true;
+
         sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
 
         memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
-- 
2.39.1

Add a new test in tests/avocado to check LoongArch virt machine start.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-Id: <20230513012744.1885728-1-gaosong@loongson.cn>
---
 MAINTAINERS                        |  1 +
 tests/avocado/machine_loongarch.py | 58 ++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 tests/avocado/machine_loongarch.py

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 S: Maintained
 F: target/loongarch/
 F: tests/tcg/loongarch64/
+F: tests/avocado/machine_loongarch.py
 
 M68K TCG CPUs
 M: Laurent Vivier <laurent@vivier.eu>
diff --git a/tests/avocado/machine_loongarch.py b/tests/avocado/machine_loongarch.py
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/avocado/machine_loongarch.py
@@ -XXX,XX +XXX,XX @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# LoongArch virt test.
+#
+# Copyright (c) 2023 Loongson Technology Corporation Limited
+#
+
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import exec_command_and_wait_for_pattern
+from avocado_qemu import wait_for_console_pattern
+
+class LoongArchMachine(QemuSystemTest):
+    KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
+
+    timeout = 120
+
+    def wait_for_console_pattern(self, success_message, vm=None):
+        wait_for_console_pattern(self, success_message,
+                                 failure_message='Kernel panic - not syncing',
+                                 vm=vm)
+
+    def test_loongarch64_devices(self):
+
+        """
+        :avocado: tags=arch:loongarch64
+        :avocado: tags=machine:virt
+        """
+
+        kernel_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
+                      'releases/download/binary-files/vmlinuz.efi')
+        kernel_hash = '951b485b16e3788b6db03a3e1793c067009e31a2'
+        kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+        initrd_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
+                      'releases/download/binary-files/ramdisk')
+        initrd_hash = 'c67658d9b2a447ce7db2f73ba3d373c9b2b90ab2'
+        initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+
+        bios_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
+                    'releases/download/binary-files/QEMU_EFI.fd')
+        bios_hash = ('dfc1bfba4853cd763b9d392d0031827e8addbca8')
+        bios_path = self.fetch_asset(bios_url, asset_hash=bios_hash)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'root=/dev/ram rdinit=/sbin/init console=ttyS0,115200')
+        self.vm.add_args('-nographic',
+                         '-smp', '4',
+                         '-m', '1024',
+                         '-cpu', 'la464',
+                         '-kernel', kernel_path,
+                         '-initrd', initrd_path,
+                         '-bios', bios_path,
+                         '-append', kernel_command_line)
+        self.vm.launch()
+        self.wait_for_console_pattern('Run /sbin/init as init process')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                          'processor		: 3')
-- 
2.39.1

ipi is used to communicate between cpus, this patch modified
loongarch ipi device as percpu device, so that there are
2 MemoryRegions with ipi device, rather than 2*cpus
MemoryRegions, which may be large than QDEV_MAX_MMIO if
more cpus are added on loongarch virt machine.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230512100421.1867848-2-gaosong@loongson.cn>
---
 hw/intc/loongarch_ipi.c         | 44 ++++++++++++---------------------
 hw/loongarch/virt.c             | 12 ++++-----
 include/hw/intc/loongarch_ipi.h | 10 +++-----
 include/hw/loongarch/virt.h     |  1 -
 4 files changed, 26 insertions(+), 41 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_ipi64_ops = {
 
 static void loongarch_ipi_init(Object *obj)
 {
-    int cpu;
-    LoongArchMachineState *lams;
     LoongArchIPI *s = LOONGARCH_IPI(obj);
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-    Object *machine = qdev_get_machine();
-    ObjectClass *mc = object_get_class(machine);
-    /* 'lams' should be initialized */
-    if (!strcmp(MACHINE_CLASS(mc)->name, "none")) {
-        return;
-    }
-    lams = LOONGARCH_MACHINE(machine);
-    for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
-        memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
-                            &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
 
-        /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
-        s->ipi_iocsr_mem[cpu].disable_reentrancy_guard = true;
+    memory_region_init_io(&s->ipi_iocsr_mem, obj, &loongarch_ipi_ops,
+                          &s->ipi_core, "loongarch_ipi_iocsr", 0x48);
 
-        sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
+    /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
+    s->ipi_iocsr_mem.disable_reentrancy_guard = true;
 
-        memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
-                              &lams->ipi_core[cpu], "loongarch_ipi64_iocsr", 0x118);
-        sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem[cpu]);
-        qdev_init_gpio_out(DEVICE(obj), &lams->ipi_core[cpu].irq, 1);
-    }
+    sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
+
+    memory_region_init_io(&s->ipi64_iocsr_mem, obj, &loongarch_ipi64_ops,
+                          &s->ipi_core, "loongarch_ipi64_iocsr", 0x118);
+    sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
+    qdev_init_gpio_out(DEVICE(obj), &s->ipi_core.irq, 1);
 }
 
 static const VMStateDescription vmstate_ipi_core = {
     .name = "ipi-single",
-    .version_id = 0,
-    .minimum_version_id = 0,
+    .version_id = 1,
+    .minimum_version_id = 1,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(status, IPICore),
         VMSTATE_UINT32(en, IPICore),
         VMSTATE_UINT32(set, IPICore),
         VMSTATE_UINT32(clear, IPICore),
-        VMSTATE_UINT32_ARRAY(buf, IPICore, MAX_IPI_MBX_NUM * 2),
+        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
         VMSTATE_END_OF_LIST()
     }
 };
 
 static const VMStateDescription vmstate_loongarch_ipi = {
     .name = TYPE_LOONGARCH_IPI,
-    .version_id = 0,
-    .minimum_version_id = 0,
+    .version_id = 1,
+    .minimum_version_id = 1,
     .fields = (VMStateField[]) {
-        VMSTATE_STRUCT_ARRAY(ipi_core, LoongArchMachineState,
-                             MAX_IPI_CORE_NUM, 0,
-                             vmstate_ipi_core, IPICore),
+        VMSTATE_STRUCT(ipi_core, LoongArchIPI, 0, vmstate_ipi_core, IPICore),
         VMSTATE_END_OF_LIST()
     }
 };
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
     CPUState *cpu_state;
     int cpu, pin, i, start, num;
 
-    ipi = qdev_new(TYPE_LOONGARCH_IPI);
-    sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
-
     extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
 
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
         lacpu = LOONGARCH_CPU(cpu_state);
         env = &(lacpu->env);
 
+        ipi = qdev_new(TYPE_LOONGARCH_IPI);
+        sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
+
         /* connect ipi irq to cpu irq */
-        qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
+        qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI));
         /* IPI iocsr memory region */
         memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
-                                    cpu * 2));
+                                    0));
         memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
-                                    cpu * 2 + 1));
+                                    1));
         /* extioi iocsr memory region */
         memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_ipi.h
+++ b/include/hw/intc/loongarch_ipi.h
@@ -XXX,XX +XXX,XX @@
 #define MAIL_SEND_OFFSET      0
 #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
 
-#define MAX_IPI_CORE_NUM      4
-#define MAX_IPI_MBX_NUM       4
-
 #define TYPE_LOONGARCH_IPI "loongarch_ipi"
 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
 
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
     uint32_t set;
     uint32_t clear;
     /* 64bit buf divide into 2 32bit buf */
-    uint32_t buf[MAX_IPI_MBX_NUM * 2];
+    uint32_t buf[2];
     qemu_irq irq;
 } IPICore;
 
 struct LoongArchIPI {
     SysBusDevice parent_obj;
-    MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM];
-    MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM];
+    MemoryRegion ipi_iocsr_mem;
+    MemoryRegion ipi64_iocsr_mem;
+    IPICore ipi_core;
 };
 
 #endif
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -XXX,XX +XXX,XX @@ struct LoongArchMachineState {
     /*< private >*/
     MachineState parent_obj;
 
-    IPICore ipi_core[MAX_IPI_CORE_NUM];
     MemoryRegion lowmem;
     MemoryRegion highmem;
     MemoryRegion isa_io;
-- 
2.39.1

Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi
only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that
loongarch virt machine supports more cpus.

Interrupts from external devices can only be routed cpu 0-3 because
of extioi limits, cpu internal interrupt such as timer/ipi can be
triggered on all cpus.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230512100421.1867848-3-gaosong@loongson.cn>
---
 hw/intc/loongarch_extioi.c         |  4 ++--
 hw/loongarch/virt.c                | 13 +++++++++----
 include/hw/intc/loongarch_extioi.h | 10 ++++++----
 include/hw/loongarch/virt.h        |  2 +-
 4 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_extioi = {
     .minimum_version_id = 1,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
-        VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, LOONGARCH_MAX_VCPUS,
+        VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, EXTIOI_CPUS,
                                EXTIOI_IRQS_GROUP_COUNT),
         VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
                              EXTIOI_IRQS_NODETYPE_COUNT / 2),
@@ -XXX,XX +XXX,XX @@ static void loongarch_extioi_instance_init(Object *obj)
 
     qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
 
-    for (cpu = 0; cpu < LOONGARCH_MAX_VCPUS; cpu++) {
+    for (cpu = 0; cpu < EXTIOI_CPUS; cpu++) {
         memory_region_init_io(&s->extioi_iocsr_mem[cpu], OBJECT(s), &extioi_ops,
                               s, "extioi_iocsr", 0x900);
         sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_iocsr_mem[cpu]);
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
         memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
                                     1));
-        /* extioi iocsr memory region */
-        memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
+        /*
+	 * extioi iocsr memory region
+	 * only one extioi is added on loongarch virt machine
+	 * external device interrupt can only be routed to cpu 0-3
+	 */
+	if (cpu < EXTIOI_CPUS)
+            memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
                                 cpu));
     }
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
      * connect ext irq to the cpu irq
      * cpu_pin[9:2] <= intc_pin[7:0]
      */
-    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+    for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) {
         cpudev = DEVICE(qemu_get_cpu(cpu));
         for (pin = 0; pin < LS3A_INTC_IP; pin++) {
             qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
     mc->default_ram_size = 1 * GiB;
     mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
     mc->default_ram_id = "loongarch.ram";
-    mc->max_cpus = LOONGARCH_MAX_VCPUS;
+    mc->max_cpus = LOONGARCH_MAX_CPUS;
     mc->is_default = 1;
     mc->default_kernel_irqchip_split = false;
     mc->block_default_type = IF_VIRTIO;
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_extioi.h
+++ b/include/hw/intc/loongarch_extioi.h
@@ -XXX,XX +XXX,XX @@
 #define LS3A_INTC_IP               8
 #define EXTIOI_IRQS                (256)
 #define EXTIOI_IRQS_BITMAP_SIZE    (256 / 8)
+/* irq from EXTIOI is routed to no more than 4 cpus */
+#define EXTIOI_CPUS                (4)
 /* map to ipnum per 32 irqs */
 #define EXTIOI_IRQS_IPMAP_SIZE     (256 / 32)
 #define EXTIOI_IRQS_COREMAP_SIZE   256
@@ -XXX,XX +XXX,XX @@ struct LoongArchExtIOI {
     uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
     uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
     uint32_t isr[EXTIOI_IRQS / 32];
-    uint32_t coreisr[LOONGARCH_MAX_VCPUS][EXTIOI_IRQS_GROUP_COUNT];
+    uint32_t coreisr[EXTIOI_CPUS][EXTIOI_IRQS_GROUP_COUNT];
     uint32_t enable[EXTIOI_IRQS / 32];
     uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
     uint32_t coremap[EXTIOI_IRQS / 4];
     uint32_t sw_pending[EXTIOI_IRQS / 32];
-    DECLARE_BITMAP(sw_isr[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP], EXTIOI_IRQS);
+    DECLARE_BITMAP(sw_isr[EXTIOI_CPUS][LS3A_INTC_IP], EXTIOI_IRQS);
     uint8_t  sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
     uint8_t  sw_coremap[EXTIOI_IRQS];
-    qemu_irq parent_irq[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP];
+    qemu_irq parent_irq[EXTIOI_CPUS][LS3A_INTC_IP];
     qemu_irq irq[EXTIOI_IRQS];
-    MemoryRegion extioi_iocsr_mem[LOONGARCH_MAX_VCPUS];
+    MemoryRegion extioi_iocsr_mem[EXTIOI_CPUS];
     MemoryRegion extioi_system_mem;
 };
 #endif /* LOONGARCH_EXTIOI_H */
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/intc/loongarch_ipi.h"
 #include "hw/block/flash.h"
 
-#define LOONGARCH_MAX_VCPUS     4
+#define LOONGARCH_MAX_CPUS      256
 
 #define VIRT_ISA_IO_BASE        0x18000000UL
 #define VIRT_ISA_IO_SIZE        0x0004000
-- 
2.39.1

When ipi mailbox is used, cpu_index is decoded from iocsr register.
cpu maybe does not exist. This patch adds NULL pointer check on
ipi device.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230512100421.1867848-4-gaosong@loongson.cn>
---
 hw/intc/loongarch_ipi.c | 40 +++++++++++++++++++++++++++++-----------
 hw/intc/trace-events    |  1 +
 2 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
 
 static void ipi_send(uint64_t val)
 {
-    int cpuid, data;
+    uint32_t cpuid;
+    uint8_t vector;
     CPULoongArchState *env;
     CPUState *cs;
     LoongArchCPU *cpu;
 
-    cpuid = (val >> 16) & 0x3ff;
+    cpuid = extract32(val, 16, 10);
+    if (cpuid >= LOONGARCH_MAX_CPUS) {
+        trace_loongarch_ipi_unsupported_cpuid("IOCSR_IPI_SEND", cpuid);
+        return;
+    }
+
     /* IPI status vector */
-    data = 1 << (val & 0x1f);
+    vector = extract8(val, 0, 5);
+
     cs = qemu_get_cpu(cpuid);
     cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
     address_space_stl(&env->address_space_iocsr, 0x1008,
-                      data, MEMTXATTRS_UNSPECIFIED, NULL);
-
+                      BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static void mail_send(uint64_t val)
 {
-    int cpuid;
+    uint32_t cpuid;
     hwaddr addr;
     CPULoongArchState *env;
     CPUState *cs;
     LoongArchCPU *cpu;
 
-    cpuid = (val >> 16) & 0x3ff;
+    cpuid = extract32(val, 16, 10);
+    if (cpuid >= LOONGARCH_MAX_CPUS) {
+        trace_loongarch_ipi_unsupported_cpuid("IOCSR_MAIL_SEND", cpuid);
+        return;
+    }
+
     addr = 0x1020 + (val & 0x1c);
     cs = qemu_get_cpu(cpuid);
     cpu = LOONGARCH_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void mail_send(uint64_t val)
 
 static void any_send(uint64_t val)
 {
-    int cpuid;
+    uint32_t cpuid;
     hwaddr addr;
     CPULoongArchState *env;
+    CPUState *cs;
+    LoongArchCPU *cpu;
+
+    cpuid = extract32(val, 16, 10);
+    if (cpuid >= LOONGARCH_MAX_CPUS) {
+        trace_loongarch_ipi_unsupported_cpuid("IOCSR_ANY_SEND", cpuid);
+        return;
+    }
 
-    cpuid = (val >> 16) & 0x3ff;
     addr = val & 0xffff;
-    CPUState *cs = qemu_get_cpu(cpuid);
-    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    cs = qemu_get_cpu(cpuid);
+    cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
     send_ipi_data(env, val, addr);
 }
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
 # loongarch_ipi.c
 loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
 loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
+loongarch_ipi_unsupported_cpuid(const char *s, uint32_t cpuid) "%s unsupported cpuid 0x%" PRIx32
 
 # loongarch_pch_pic.c
 loongarch_pch_pic_irq_handler(int irq, int level) "irq %d level %d"
-- 
2.39.1

The following changes since commit aa3a285b5bc56a4208b3b57d4a55291e9c260107:

Merge tag 'mem-2024-12-21' of https://github.com/davidhildenbrand/qemu into staging (2024-12-22 14:33:27 -0500)

are available in the Git repository at:

https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20241225

for you to fetch changes up to cb91b7108cb0b3781de9a00994fe78b631d80012:

target/loongarch: Use auto method with LASX feature (2024-12-25 10:33:20 +0800)

----------------------------------------------------------------
pull-loongarch-20241225

----------------------------------------------------------------
Bibo Mao (5):
      target/loongarch: Use actual operand size with vbsrl check
      hw/loongarch/virt: Create fdt table on machine creation done notification
      hw/loongarch/virt: Improve fdt table creation for CPU object
      target/loongarch: Use auto method with LSX feature
      target/loongarch: Use auto method with LASX feature

ghy (1):
      target/loongarch: Fix vldi inst

hw/loongarch/virt.c                             | 142 ++++++++++++++----------
 target/loongarch/cpu.c                          |  86 ++++++++------
 target/loongarch/cpu.h                          |   4 +
 target/loongarch/kvm/kvm.c                      | 107 ++++++++++++++++++
 target/loongarch/tcg/insn_trans/trans_vec.c.inc |   4 +-
 5 files changed, 249 insertions(+), 94 deletions(-)

From: ghy <2247883756@qq.com>

Refer to the link below for a description of the vldi instructions:
https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88
Fixed errors in vldi instruction implementation.

Signed-off-by: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
Tested-by: Xianglai Li <lixianglai@loongson.cn>
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
@@ -XXX,XX +XXX,XX @@ static uint64_t vldi_get_value(DisasContext *ctx, uint32_t imm)
         break;
     case 1:
         /* data: {2{16'0, imm[7:0], 8'0}} */
-        data = (t << 24) | (t << 8);
+        data = (t << 40) | (t << 8);
         break;
     case 2:
         /* data: {2{8'0, imm[7:0], 16'0}} */
-- 
2.43.5

Hardcoded 32 bytes is used for vbsrl emulation check, there is
problem when options lsx=on,lasx=off is used for vbsrl.v instruction
in TCG mode. It injects LASX exception rather LSX exception.

Here actual operand size is used.

Cc: qemu-stable@nongnu.org
Fixes: df97f338076 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve")
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
 {
     int i, ofs;
 
-    if (!check_vec(ctx, 32)) {
+    if (!check_vec(ctx, oprsz)) {
         return true;
     }
 
-- 
2.43.5

The same with ACPI table, fdt table is created on machine done
notification. Some objects like CPU objects can be created with cold-plug
method with command such as -smp x, -device la464-loongarch-cpu, so all
objects finish to create when machine is done.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/loongarch/virt.c | 103 ++++++++++++++++++++++++--------------------
 1 file changed, 57 insertions(+), 46 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(LoongArchVirtMachineState *lvms)
     }
 }
 
+static void virt_fdt_setup(LoongArchVirtMachineState *lvms)
+{
+    MachineState *machine = MACHINE(lvms);
+    uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
+    int i;
+
+    create_fdt(lvms);
+    fdt_add_cpu_nodes(lvms);
+    fdt_add_memory_nodes(machine);
+    fdt_add_fw_cfg_node(lvms);
+    fdt_add_flash_node(lvms);
+
+    /* Add cpu interrupt-controller */
+    fdt_add_cpuic_node(lvms, &cpuintc_phandle);
+    /* Add Extend I/O Interrupt Controller node */
+    fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
+    /* Add PCH PIC node */
+    fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
+    /* Add PCH MSI node */
+    fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
+    /* Add pcie node */
+    fdt_add_pcie_node(lvms, &pch_pic_phandle, &pch_msi_phandle);
+
+    /*
+     * Create uart fdt node in reverse order so that they appear
+     * in the finished device tree lowest address first
+     */
+    for (i = VIRT_UART_COUNT; i-- > 0;) {
+        hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
+        int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
+        fdt_add_uart_node(lvms, &pch_pic_phandle, base, irq, i == 0);
+    }
+
+    fdt_add_rtc_node(lvms, &pch_pic_phandle);
+    fdt_add_ged_reset(lvms);
+    platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
+                                   VIRT_PLATFORM_BUS_BASEADDRESS,
+                                   VIRT_PLATFORM_BUS_SIZE,
+                                   VIRT_PLATFORM_BUS_IRQ);
+
+    /*
+     * Since lowmem region starts from 0 and Linux kernel legacy start address
+     * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
+     * access. FDT size limit with 1 MiB.
+     * Put the FDT into the memory map as a ROM image: this will ensure
+     * the FDT is copied again upon reset, even if addr points into RAM.
+     */
+    qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
+    rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
+                          &address_space_memory);
+    qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
+            rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
+}
+
 static void virt_done(Notifier *notifier, void *data)
 {
     LoongArchVirtMachineState *lvms = container_of(notifier,
                                       LoongArchVirtMachineState, machine_done);
     virt_build_smbios(lvms);
     loongarch_acpi_setup(lvms);
+    virt_fdt_setup(lvms);
 }
 
 static void virt_powerdown_req(Notifier *notifier, void *opaque)
@@ -XXX,XX +XXX,XX @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
 }
 
 static void virt_devices_init(DeviceState *pch_pic,
-                                   LoongArchVirtMachineState *lvms,
-                                   uint32_t *pch_pic_phandle,
-                                   uint32_t *pch_msi_phandle)
+                                   LoongArchVirtMachineState *lvms)
 {
     MachineClass *mc = MACHINE_GET_CLASS(lvms);
     DeviceState *gpex_dev;
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
         gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
     }
 
-    /* Add pcie node */
-    fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
-
     /*
      * Create uart fdt node in reverse order so that they appear
      * in the finished device tree lowest address first
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
         serial_mm_init(get_system_memory(), base, 0,
                        qdev_get_gpio_in(pch_pic, irq),
                        115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
-        fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
     }
 
     /* Network init */
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
     sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
                          qdev_get_gpio_in(pch_pic,
                          VIRT_RTC_IRQ - VIRT_GSI_BASE));
-    fdt_add_rtc_node(lvms, pch_pic_phandle);
-    fdt_add_ged_reset(lvms);
 
     /* acpi ged */
     lvms->acpi_ged = create_acpi_ged(pch_pic, lvms);
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
     CPULoongArchState *env;
     CPUState *cpu_state;
     int cpu, pin, i, start, num;
-    uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
 
     /*
      * Extended IRQ model.
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
     memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
                    sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
 
-    /* Add cpu interrupt-controller */
-    fdt_add_cpuic_node(lvms, &cpuintc_phandle);
-
     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
         cpu_state = qemu_get_cpu(cpu);
         cpudev = DEVICE(cpu_state);
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
         }
     }
 
-    /* Add Extend I/O Interrupt Controller node */
-    fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
-
     pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
     num = VIRT_PCH_PIC_IRQ_NUM;
     qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
         qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
     }
 
-    /* Add PCH PIC node */
-    fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
-
     pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
     start   =  num;
     num = EXTIOI_IRQS - start;
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
                               qdev_get_gpio_in(extioi, i + start));
     }
 
-    /* Add PCH MSI node */
-    fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
-
-    virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle);
+    virt_devices_init(pch_pic, lvms);
 }
 
 static void virt_firmware_init(LoongArchVirtMachineState *lvms)
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
     }
 
-    create_fdt(lvms);
-
     /* Create IOCSR space */
     memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL,
                           machine, "iocsr", UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
         lacpu = LOONGARCH_CPU(cpu);
         lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
     }
-    fdt_add_cpu_nodes(lvms);
-    fdt_add_memory_nodes(machine);
     fw_cfg_add_memory(machine);
 
     /* Node0 memory */
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
                         memmap_table,
                         sizeof(struct memmap_entry) * (memmap_entries));
     }
-    fdt_add_fw_cfg_node(lvms);
-    fdt_add_flash_node(lvms);
 
     /* Initialize the IO interrupt subsystem */
     virt_irq_init(lvms);
-    platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
-                                   VIRT_PLATFORM_BUS_BASEADDRESS,
-                                   VIRT_PLATFORM_BUS_SIZE,
-                                   VIRT_PLATFORM_BUS_IRQ);
     lvms->machine_done.notify = virt_done;
     qemu_add_machine_init_done_notifier(&lvms->machine_done);
      /* connect powerdown request */
     lvms->powerdown_notifier.notify = virt_powerdown_req;
     qemu_register_powerdown_notifier(&lvms->powerdown_notifier);
 
-    /*
-     * Since lowmem region starts from 0 and Linux kernel legacy start address
-     * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
-     * access. FDT size limit with 1 MiB.
-     * Put the FDT into the memory map as a ROM image: this will ensure
-     * the FDT is copied again upon reset, even if addr points into RAM.
-     */
-    qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
-    rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
-                          &address_space_memory);
-    qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
-            rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
-
     lvms->bootinfo.ram_size = ram_size;
     loongarch_load_kernel(machine, &lvms->bootinfo);
 }
-- 
2.43.5

For CPU object, possible_cpu_arch_ids() function is used rather than
smp.cpus. With command -smp x, -device la464-loongarch-cpu, smp.cpus
is not accurate for all possible CPU objects, possible_cpu_arch_ids()
is used here.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/loongarch/virt.c | 39 +++++++++++++++++++++++++--------------
 1 file changed, 25 insertions(+), 14 deletions(-)

Like LBT feature, add type OnOffAuto for LSX feature setting. Also
add LSX feature detection with new VM ioctl command, fallback to old
method if it is not supported.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c     | 38 +++++++++++++++------------
 target/loongarch/cpu.h     |  2 ++
 target/loongarch/kvm/kvm.c | 54 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 77 insertions(+), 17 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
     CPULoongArchState *env = &cpu->env;
+    uint32_t data = 0;
     int i;
 
     for (i = 0; i < 21; i++) {
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
     cpu->dtb_compatible = "loongarch,Loongson-3A5000";
     env->cpucfg[0] = 0x14c010;  /* PRID */
 
-    uint32_t data = 0;
     data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
     data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
     data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
     CPULoongArchState *env = &cpu->env;
-
+    uint32_t data = 0;
     int i;
 
     for (i = 0; i < 21; i++) {
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
     cpu->dtb_compatible = "loongarch,Loongson-1C103";
     env->cpucfg[0] = 0x148042;  /* PRID */
 
-    uint32_t data = 0;
     data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
     data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
     data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
 
 static bool loongarch_get_lsx(Object *obj, Error **errp)
 {
-    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-    bool ret;
-
-    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
-        ret = true;
-    } else {
-        ret = false;
-    }
-    return ret;
+    return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
 }
 
 static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    uint32_t val;
 
-    if (value) {
-        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
-    } else {
-        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0);
-        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
+    cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
+    if (kvm_enabled()) {
+        /* kvm feature detection in function kvm_arch_init_vcpu */
+        return;
     }
+
+    /* LSX feature detection in TCG mode */
+    val = cpu->env.cpucfg[2];
+    if (cpu->lsx == ON_OFF_AUTO_ON) {
+        if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
+            error_setg(errp, "Failed to enable LSX in TCG mode");
+            return;
+        }
+    }
+
+    cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
 }
 
 static bool loongarch_get_lasx(Object *obj, Error **errp)
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 
+    cpu->lsx = ON_OFF_AUTO_AUTO;
     object_property_add_bool(obj, "lsx", loongarch_get_lsx,
                              loongarch_set_lsx);
     object_property_add_bool(obj, "lasx", loongarch_get_lasx,
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
 
     } else {
         cpu->lbt = ON_OFF_AUTO_OFF;
+        cpu->pmu = ON_OFF_AUTO_OFF;
     }
 }
 
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
 #endif
 
 enum loongarch_features {
+    LOONGARCH_FEATURE_LSX,
     LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
     LOONGARCH_FEATURE_PMU,
 };
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t  phy_id;
     OnOffAuto lbt;
     OnOffAuto pmu;
+    OnOffAuto lsx;
 
     /* 'compatible' string for this CPU for Linux device trees */
     const char *dtb_compatible;
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
 {
     int ret;
     struct kvm_device_attr attr;
+    uint64_t val;
 
     switch (feature) {
+    case LOONGARCH_FEATURE_LSX:
+        attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
+        attr.attr = KVM_LOONGARCH_VM_FEAT_LSX;
+        ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
+        if (ret == 0) {
+            return true;
+        }
+
+        /* Fallback to old kernel detect interface */
+        val = 0;
+        attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
+        /* Cpucfg2 */
+        attr.attr  = 2;
+        attr.addr = (uint64_t)&val;
+        ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
+        if (!ret) {
+            ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
+            if (ret) {
+                return false;
+            }
+
+            ret = FIELD_EX32((uint32_t)val, CPUCFG2, LSX);
+            return (ret != 0);
+        }
+        return false;
+
     case LOONGARCH_FEATURE_LBT:
         /*
          * Return all if all the LBT features are supported such as:
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
     return false;
 }
 
+static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
+{
+    CPULoongArchState *env = cpu_env(cs);
+    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    bool kvm_supported;
+
+    kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LSX);
+    env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 0);
+    if (cpu->lsx == ON_OFF_AUTO_ON) {
+        if (kvm_supported) {
+            env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
+        } else {
+            error_setg(errp, "'lsx' feature not supported by KVM on this host");
+            return -ENOTSUP;
+        }
+    } else if ((cpu->lsx == ON_OFF_AUTO_AUTO) && kvm_supported) {
+        env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
+    }
+
+    return 0;
+}
+
 static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
 {
     CPULoongArchState *env = cpu_env(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         brk_insn = val;
     }
 
+    ret = kvm_cpu_check_lsx(cs, &local_err);
+    if (ret < 0) {
+        error_report_err(local_err);
+    }
+
     ret = kvm_cpu_check_lbt(cs, &local_err);
     if (ret < 0) {
         error_report_err(local_err);
-- 
2.43.5

Like LSX feature, add type OnOffAuto for LASX feature setting.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c     | 50 +++++++++++++++++++++++------------
 target/loongarch/cpu.h     |  2 ++
 target/loongarch/kvm/kvm.c | 53 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 89 insertions(+), 16 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
     uint32_t val;
 
     cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
+    if (cpu->lsx == ON_OFF_AUTO_OFF) {
+        cpu->lasx = ON_OFF_AUTO_OFF;
+        if (cpu->lasx == ON_OFF_AUTO_ON) {
+            error_setg(errp, "Failed to disable LSX since LASX is enabled");
+            return;
+        }
+    }
+
     if (kvm_enabled()) {
         /* kvm feature detection in function kvm_arch_init_vcpu */
         return;
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
             error_setg(errp, "Failed to enable LSX in TCG mode");
             return;
         }
+    } else {
+        cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
+        val = cpu->env.cpucfg[2];
     }
 
     cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
 
 static bool loongarch_get_lasx(Object *obj, Error **errp)
 {
-    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-    bool ret;
-
-    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
-        ret = true;
-    } else {
-        ret = false;
-    }
-    return ret;
+    return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
 }
 
 static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    uint32_t val;
 
-    if (value) {
-	if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
-            cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
-	}
-        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1);
-    } else {
-        cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
+    cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
+    if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
+        error_setg(errp, "Failed to enable LASX since lSX is disabled");
+        return;
+    }
+
+    if (kvm_enabled()) {
+        /* kvm feature detection in function kvm_arch_init_vcpu */
+        return;
     }
+
+    /* LASX feature detection in TCG mode */
+    val = cpu->env.cpucfg[2];
+    if (cpu->lasx == ON_OFF_AUTO_ON) {
+        if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
+            error_setg(errp, "Failed to enable LASX in TCG mode");
+            return;
+        }
+    }
+
+    cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
 }
 
 static bool loongarch_get_lbt(Object *obj, Error **errp)
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 
     cpu->lsx = ON_OFF_AUTO_AUTO;
+    cpu->lasx = ON_OFF_AUTO_AUTO;
     object_property_add_bool(obj, "lsx", loongarch_get_lsx,
                              loongarch_set_lsx);
     object_property_add_bool(obj, "lasx", loongarch_get_lasx,
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
 
 enum loongarch_features {
     LOONGARCH_FEATURE_LSX,
+    LOONGARCH_FEATURE_LASX,
     LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
     LOONGARCH_FEATURE_PMU,
 };
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     OnOffAuto lbt;
     OnOffAuto pmu;
     OnOffAuto lsx;
+    OnOffAuto lasx;
 
     /* 'compatible' string for this CPU for Linux device trees */
     const char *dtb_compatible;
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
         }
         return false;
 
+    case LOONGARCH_FEATURE_LASX:
+        attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
+        attr.attr = KVM_LOONGARCH_VM_FEAT_LASX;
+        ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
+        if (ret == 0) {
+            return true;
+        }
+
+        /* Fallback to old kernel detect interface */
+        val = 0;
+        attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
+        /* Cpucfg2 */
+        attr.attr  = 2;
+        attr.addr = (uint64_t)&val;
+        ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
+        if (!ret) {
+            ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
+            if (ret) {
+                return false;
+            }
+
+            ret = FIELD_EX32((uint32_t)val, CPUCFG2, LASX);
+            return (ret != 0);
+        }
+        return false;
+
     case LOONGARCH_FEATURE_LBT:
         /*
          * Return all if all the LBT features are supported such as:
@@ -XXX,XX +XXX,XX @@ static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
     return 0;
 }
 
+static int kvm_cpu_check_lasx(CPUState *cs, Error **errp)
+{
+    CPULoongArchState *env = cpu_env(cs);
+    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    bool kvm_supported;
+
+    kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LASX);
+    env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 0);
+    if (cpu->lasx == ON_OFF_AUTO_ON) {
+        if (kvm_supported) {
+            env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
+        } else {
+            error_setg(errp, "'lasx' feature not supported by KVM on host");
+            return -ENOTSUP;
+        }
+    } else if ((cpu->lasx == ON_OFF_AUTO_AUTO) && kvm_supported) {
+        env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
+    }
+
+    return 0;
+}
+
 static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
 {
     CPULoongArchState *env = cpu_env(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         error_report_err(local_err);
     }
 
+    ret = kvm_cpu_check_lasx(cs, &local_err);
+    if (ret < 0) {
+        error_report_err(local_err);
+    }
+
     ret = kvm_cpu_check_lbt(cs, &local_err);
     if (ret < 0) {
         error_report_err(local_err);
-- 
2.43.5