Hello,
Since v2:
- Add reviewed-by's from Richard
- Pull cpu definition out of ifdef in helper_mfspr
Since v1:
- Fixups suggested by Richard Henderson
This series adds support for the FPU related architecture changes defined in
architecture spec revision v1.4.
- https://openrisc.io/revisions/r1.4
In summary the architecture changes are:
- Change FPCSR SPR permissions to allow for reading and writing from user
space.
- Clarify that FPU underflow detection is done by detecting tininess before
rounding.
Previous to this series FPCSR reads and writes from user-mode in QEMU would
throw an illegal argument exception. The proper behavior should have been to
treat these operations as no-ops as the cpu implementations do. As mentioned
series changes FPCSR read/write to follow the spec.
The series has been tested with the FPU support added in glibc test suite and
all math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc: Set PC to cpu state on FPU exception
target/openrisc: Setup FPU for detecting tininess before rounding
target/openrisc/cpu.c | 4 ++
target/openrisc/fpu_helper.c | 13 ++++++-
target/openrisc/sys_helper.c | 45 ++++++++++++++++------
target/openrisc/translate.c | 72 ++++++++++++++++--------------------
4 files changed, 81 insertions(+), 53 deletions(-)
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2.39.1