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[PATCH 06/11] tcg/riscv: Support rotates from Zbb

Richard Henderson posted 11 patches 2 years, 9 months ago
[PATCH 06/11] tcg/riscv: Support rotates from Zbb
Posted by Richard Henderson 2 years, 9 months ago 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.h     |  4 ++--
 tcg/riscv/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 9f58d46208..317d385924 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -101,7 +101,7 @@ extern bool have_zbb;
 #define TCG_TARGET_HAS_div_i32          1
 #define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_div2_i32         0
-#define TCG_TARGET_HAS_rot_i32          0
+#define TCG_TARGET_HAS_rot_i32          have_zbb
 #define TCG_TARGET_HAS_deposit_i32      0
 #define TCG_TARGET_HAS_extract_i32      0
 #define TCG_TARGET_HAS_sextract_i32     0
@@ -136,7 +136,7 @@ extern bool have_zbb;
 #define TCG_TARGET_HAS_div_i64          1
 #define TCG_TARGET_HAS_rem_i64          1
 #define TCG_TARGET_HAS_div2_i64         0
-#define TCG_TARGET_HAS_rot_i64          0
+#define TCG_TARGET_HAS_rot_i64          have_zbb
 #define TCG_TARGET_HAS_deposit_i64      0
 #define TCG_TARGET_HAS_extract_i64      0
 #define TCG_TARGET_HAS_sextract_i64     0
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index f64eaa8515..58f969b4fe 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1458,6 +1458,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_rotl_i32:
+        if (c2) {
+            tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f);
+        } else {
+            tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2);
+        }
+        break;
+    case INDEX_op_rotl_i64:
+        if (c2) {
+            tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f);
+        } else {
+            tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_rotr_i32:
+        if (c2) {
+            tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f);
+        } else {
+            tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2);
+        }
+        break;
+    case INDEX_op_rotr_i64:
+        if (c2) {
+            tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f);
+        } else {
+            tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2);
+        }
+        break;
+
     case INDEX_op_add2_i32:
         tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
                         const_args[4], const_args[5], false, true);
@@ -1629,9 +1659,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shl_i32:
     case INDEX_op_shr_i32:
     case INDEX_op_sar_i32:
+    case INDEX_op_rotl_i32:
+    case INDEX_op_rotr_i32:
     case INDEX_op_shl_i64:
     case INDEX_op_shr_i64:
     case INDEX_op_sar_i64:
+    case INDEX_op_rotl_i64:
+    case INDEX_op_rotr_i64:
         return C_O1_I2(r, r, ri);
 
     case INDEX_op_brcond_i32:
-- 
2.34.1
Re: [PATCH 06/11] tcg/riscv: Support rotates from Zbb
Posted by Alistair Francis 2 years, 8 months ago 
On Wed, May 3, 2023 at 6:57 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  tcg/riscv/tcg-target.h     |  4 ++--
>  tcg/riscv/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
>  2 files changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 9f58d46208..317d385924 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -101,7 +101,7 @@ extern bool have_zbb;
>  #define TCG_TARGET_HAS_div_i32          1
>  #define TCG_TARGET_HAS_rem_i32          1
>  #define TCG_TARGET_HAS_div2_i32         0
> -#define TCG_TARGET_HAS_rot_i32          0
> +#define TCG_TARGET_HAS_rot_i32          have_zbb
>  #define TCG_TARGET_HAS_deposit_i32      0
>  #define TCG_TARGET_HAS_extract_i32      0
>  #define TCG_TARGET_HAS_sextract_i32     0
> @@ -136,7 +136,7 @@ extern bool have_zbb;
>  #define TCG_TARGET_HAS_div_i64          1
>  #define TCG_TARGET_HAS_rem_i64          1
>  #define TCG_TARGET_HAS_div2_i64         0
> -#define TCG_TARGET_HAS_rot_i64          0
> +#define TCG_TARGET_HAS_rot_i64          have_zbb
>  #define TCG_TARGET_HAS_deposit_i64      0
>  #define TCG_TARGET_HAS_extract_i64      0
>  #define TCG_TARGET_HAS_sextract_i64     0
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index f64eaa8515..58f969b4fe 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1458,6 +1458,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          }
>          break;
>
> +    case INDEX_op_rotl_i32:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2);
> +        }
> +        break;
> +    case INDEX_op_rotl_i64:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2);
> +        }
> +        break;
> +
> +    case INDEX_op_rotr_i32:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2);
> +        }
> +        break;
> +    case INDEX_op_rotr_i64:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2);
> +        }
> +        break;
> +
>      case INDEX_op_add2_i32:
>          tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
>                          const_args[4], const_args[5], false, true);
> @@ -1629,9 +1659,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
>      case INDEX_op_shl_i32:
>      case INDEX_op_shr_i32:
>      case INDEX_op_sar_i32:
> +    case INDEX_op_rotl_i32:
> +    case INDEX_op_rotr_i32:
>      case INDEX_op_shl_i64:
>      case INDEX_op_shr_i64:
>      case INDEX_op_sar_i64:
> +    case INDEX_op_rotl_i64:
> +    case INDEX_op_rotr_i64:
>          return C_O1_I2(r, r, ri);
>
>      case INDEX_op_brcond_i32:
> --
> 2.34.1
>
>
Re: [PATCH 06/11] tcg/riscv: Support rotates from Zbb
Posted by Daniel Henrique Barboza 2 years, 9 months ago 

On 5/3/23 05:56, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   tcg/riscv/tcg-target.h     |  4 ++--
>   tcg/riscv/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
>   2 files changed, 36 insertions(+), 2 deletions(-)
> 
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 9f58d46208..317d385924 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -101,7 +101,7 @@ extern bool have_zbb;
>   #define TCG_TARGET_HAS_div_i32          1
>   #define TCG_TARGET_HAS_rem_i32          1
>   #define TCG_TARGET_HAS_div2_i32         0
> -#define TCG_TARGET_HAS_rot_i32          0
> +#define TCG_TARGET_HAS_rot_i32          have_zbb
>   #define TCG_TARGET_HAS_deposit_i32      0
>   #define TCG_TARGET_HAS_extract_i32      0
>   #define TCG_TARGET_HAS_sextract_i32     0
> @@ -136,7 +136,7 @@ extern bool have_zbb;
>   #define TCG_TARGET_HAS_div_i64          1
>   #define TCG_TARGET_HAS_rem_i64          1
>   #define TCG_TARGET_HAS_div2_i64         0
> -#define TCG_TARGET_HAS_rot_i64          0
> +#define TCG_TARGET_HAS_rot_i64          have_zbb
>   #define TCG_TARGET_HAS_deposit_i64      0
>   #define TCG_TARGET_HAS_extract_i64      0
>   #define TCG_TARGET_HAS_sextract_i64     0
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index f64eaa8515..58f969b4fe 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1458,6 +1458,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>           }
>           break;
>   
> +    case INDEX_op_rotl_i32:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2);
> +        }
> +        break;
> +    case INDEX_op_rotl_i64:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2);
> +        }
> +        break;
> +
> +    case INDEX_op_rotr_i32:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2);
> +        }
> +        break;
> +    case INDEX_op_rotr_i64:
> +        if (c2) {
> +            tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f);
> +        } else {
> +            tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2);
> +        }
> +        break;
> +
>       case INDEX_op_add2_i32:
>           tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
>                           const_args[4], const_args[5], false, true);
> @@ -1629,9 +1659,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
>       case INDEX_op_shl_i32:
>       case INDEX_op_shr_i32:
>       case INDEX_op_sar_i32:
> +    case INDEX_op_rotl_i32:
> +    case INDEX_op_rotr_i32:
>       case INDEX_op_shl_i64:
>       case INDEX_op_shr_i64:
>       case INDEX_op_sar_i64:
> +    case INDEX_op_rotl_i64:
> +    case INDEX_op_rotr_i64:
>           return C_O1_I2(r, r, ri);
>   
>       case INDEX_op_brcond_i32:

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