[v2] riscv: implement Ssqosid extension and CBQRI controllers

[RFC PATCH v2 1/9] riscv: implement Ssqosid extension and sqoscfg CSR

Posted by Drew Fustini 2 years, 9 months ago

From: Kornel Dulęba <mindal@semihalf.com>

Implement the sqoscfg CSR defined by the Ssqosid ISA extension
(Supervisor-mode Quality of Service ID). The CSR contains two fields:

  - Resource Control ID (RCID) used determine resource allocation
  - Monitoring Counter ID (MCID) used to track resource usage

The CSR is defined for S-mode but accessing it when V=1 shall cause a
virtual instruction exception. Implement this behavior by calling the
hmode predicate.

Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf
Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
[dfustini: rebase on v8.0.50, reword commit message]
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
---
Changes since v1:
- rebase on current master (v8.0.50) instead of 8.0.0-rc4

 disas/riscv.c           |  1 +
 target/riscv/cpu.c      |  2 ++
 target/riscv/cpu.h      |  3 +++
 target/riscv/cpu_bits.h |  5 +++++
 target/riscv/csr.c      | 34 ++++++++++++++++++++++++++++++++++
 5 files changed, 45 insertions(+)

diff --git a/disas/riscv.c b/disas/riscv.c
index d6b0fbe5e877..94336f54637b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2100,6 +2100,7 @@ static const char *csr_name(int csrno)
     case 0x0143: return "stval";
     case 0x0144: return "sip";
     case 0x0180: return "satp";
+    case 0x0181: return "sqoscfg";
     case 0x0200: return "hstatus";
     case 0x0202: return "hedeleg";
     case 0x0203: return "hideleg";
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af27b..fb3f8c43a32d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
     ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
     ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
+    ISA_EXT_DATA_ENTRY(ssqosid, true, PRIV_VERSION_1_12_0, ext_ssqosid),
     ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
     ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
     ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
@@ -1397,6 +1398,7 @@ static Property riscv_cpu_extensions[] = {
 
     DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
 
+    DEFINE_PROP_BOOL("ssqosid", RISCVCPU, cfg.ext_ssqosid, true),
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
     DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a57..ffc1b5009d15 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -222,6 +222,8 @@ struct CPUArchState {
     target_ulong mcause;
     target_ulong mtval;  /* since: priv-1.10.0 */
 
+    target_ulong sqoscfg;
+
     /* Machine and Supervisor interrupt priorities */
     uint8_t miprio[64];
     uint8_t siprio[64];
@@ -454,6 +456,7 @@ struct RISCVCPUConfig {
     bool ext_icboz;
     bool ext_zicond;
     bool ext_zihintpause;
+    bool ext_ssqosid;
     bool ext_smstateen;
     bool ext_sstc;
     bool ext_svadu;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fca7ef0cef91..d11a3928735e 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -217,6 +217,7 @@
 /* Supervisor Protection and Translation */
 #define CSR_SPTBR           0x180
 #define CSR_SATP            0x180
+#define CSR_SQOSCFG         0x181
 
 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
 #define CSR_SISELECT        0x150
@@ -898,4 +899,8 @@ typedef enum RISCVException {
 #define MHPMEVENT_IDX_MASK                 0xFFFFF
 #define MHPMEVENT_SSCOF_RESVD              16
 
+/* SQOSCFG BITS (QOSID) */
+#define SQOSCFG_RCID                      0x00000FFF
+#define SQOSCFG_MCID                      0x0FFF0000
+
 #endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b63a..5769b3545704 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2700,6 +2700,37 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException check_sqoscfg(CPURISCVState *env, int csrno)
+{
+    RISCVCPU *cpu = env_archcpu(env);
+
+    if (!cpu->cfg.ext_ssqosid) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    /*
+     * Even though this is an S-mode CSR the spec says that we need to throw
+     * and virt instruction fault if a guest tries to access it.
+     */
+    return hmode(env, csrno);
+}
+
+static RISCVException read_sqoscfg(CPURISCVState *env, int csrno,
+                                target_ulong *val)
+{
+    *val = env->sqoscfg;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_sqoscfg(CPURISCVState *env, int csrno,
+                                 target_ulong val)
+{
+    env->sqoscfg = val & (SQOSCFG_RCID | SQOSCFG_MCID);
+    return RISCV_EXCP_NONE;
+}
+
+
+
 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
 {
     int irq, ret;
@@ -4182,6 +4213,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Supervisor Protection and Translation */
     [CSR_SATP]     = { "satp",     smode, read_satp,     write_satp     },
 
+    /* Supervisor-Level Quality of Service Identifier */
+    [CSR_SQOSCFG]  = { "sqoscfg",  check_sqoscfg, read_sqoscfg, write_sqoscfg },
+
     /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
     [CSR_SISELECT]   = { "siselect",   aia_smode, NULL, NULL, rmw_xiselect },
     [CSR_SIREG]      = { "sireg",      aia_smode, NULL, NULL, rmw_xireg },
-- 
2.34.1

Re: [RFC PATCH v2 1/9] riscv: implement Ssqosid extension and sqoscfg CSR

Posted by Weiwei Li 2 years, 9 months ago

On 2023/4/26 04:38, Drew Fustini wrote:
> From: Kornel Dulęba <mindal@semihalf.com>
>
> Implement the sqoscfg CSR defined by the Ssqosid ISA extension
> (Supervisor-mode Quality of Service ID). The CSR contains two fields:
>
>    - Resource Control ID (RCID) used determine resource allocation
>    - Monitoring Counter ID (MCID) used to track resource usage
>
> The CSR is defined for S-mode but accessing it when V=1 shall cause a
> virtual instruction exception. Implement this behavior by calling the
> hmode predicate.
>
> Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf
> Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
> [dfustini: rebase on v8.0.50, reword commit message]
> Signed-off-by: Drew Fustini <dfustini@baylibre.com>
> ---
> Changes since v1:
> - rebase on current master (v8.0.50) instead of 8.0.0-rc4
>
>   disas/riscv.c           |  1 +
>   target/riscv/cpu.c      |  2 ++
>   target/riscv/cpu.h      |  3 +++
>   target/riscv/cpu_bits.h |  5 +++++
>   target/riscv/csr.c      | 34 ++++++++++++++++++++++++++++++++++
>   5 files changed, 45 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index d6b0fbe5e877..94336f54637b 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2100,6 +2100,7 @@ static const char *csr_name(int csrno)
>       case 0x0143: return "stval";
>       case 0x0144: return "sip";
>       case 0x0180: return "satp";
> +    case 0x0181: return "sqoscfg";
>       case 0x0200: return "hstatus";
>       case 0x0202: return "hedeleg";
>       case 0x0203: return "hideleg";
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e97473af27b..fb3f8c43a32d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
>       ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
>       ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
> +    ISA_EXT_DATA_ENTRY(ssqosid, true, PRIV_VERSION_1_12_0, ext_ssqosid),
>       ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
>       ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
>       ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
> @@ -1397,6 +1398,7 @@ static Property riscv_cpu_extensions[] = {
>   
>       DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
>   
> +    DEFINE_PROP_BOOL("ssqosid", RISCVCPU, cfg.ext_ssqosid, true),
>       DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
>       DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>       DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a57..ffc1b5009d15 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -222,6 +222,8 @@ struct CPUArchState {
>       target_ulong mcause;
>       target_ulong mtval;  /* since: priv-1.10.0 */
>   
> +    target_ulong sqoscfg;
> +
>       /* Machine and Supervisor interrupt priorities */
>       uint8_t miprio[64];
>       uint8_t siprio[64];
> @@ -454,6 +456,7 @@ struct RISCVCPUConfig {
>       bool ext_icboz;
>       bool ext_zicond;
>       bool ext_zihintpause;
> +    bool ext_ssqosid;
>       bool ext_smstateen;
>       bool ext_sstc;
>       bool ext_svadu;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fca7ef0cef91..d11a3928735e 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -217,6 +217,7 @@
>   /* Supervisor Protection and Translation */
>   #define CSR_SPTBR           0x180
>   #define CSR_SATP            0x180
> +#define CSR_SQOSCFG         0x181
>   
>   /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
>   #define CSR_SISELECT        0x150
> @@ -898,4 +899,8 @@ typedef enum RISCVException {
>   #define MHPMEVENT_IDX_MASK                 0xFFFFF
>   #define MHPMEVENT_SSCOF_RESVD              16
>   
> +/* SQOSCFG BITS (QOSID) */
> +#define SQOSCFG_RCID                      0x00000FFF
> +#define SQOSCFG_MCID                      0x0FFF0000
> +
>   #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b63a..5769b3545704 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2700,6 +2700,37 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
>       return RISCV_EXCP_NONE;
>   }
>   
> +static RISCVException check_sqoscfg(CPURISCVState *env, int csrno)
> +{
> +    RISCVCPU *cpu = env_archcpu(env);
> +
> +    if (!cpu->cfg.ext_ssqosid) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
> +    /*
> +     * Even though this is an S-mode CSR the spec says that we need to throw
> +     * and virt instruction fault if a guest tries to access it.
> +     */
> +    return hmode(env, csrno);

If above comments is true, use hmode() here is not right, since it only 
check whether H extension is supported.

It need another check for guest mode access. And we should use smode() 
instead of hmode() here.

> +}
> +
> +static RISCVException read_sqoscfg(CPURISCVState *env, int csrno,
> +                                target_ulong *val)

'target_ulong' is better to align with 'CPURISCVState'.

Regards,

Weiwei Li

> +{
> +    *val = env->sqoscfg;
> +    return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_sqoscfg(CPURISCVState *env, int csrno,
> +                                 target_ulong val)
> +{
> +    env->sqoscfg = val & (SQOSCFG_RCID | SQOSCFG_MCID);
> +    return RISCV_EXCP_NONE;
> +}
> +
> +
> +
>   static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
>   {
>       int irq, ret;
> @@ -4182,6 +4213,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>       /* Supervisor Protection and Translation */
>       [CSR_SATP]     = { "satp",     smode, read_satp,     write_satp     },
>   
> +    /* Supervisor-Level Quality of Service Identifier */
> +    [CSR_SQOSCFG]  = { "sqoscfg",  check_sqoscfg, read_sqoscfg, write_sqoscfg },
> +
>       /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
>       [CSR_SISELECT]   = { "siselect",   aia_smode, NULL, NULL, rmw_xiselect },
>       [CSR_SIREG]      = { "sireg",      aia_smode, NULL, NULL, rmw_xireg },