On Thu, 20 Apr 2023 16:57:18 +0100
Alex Bennée <alex.bennee@linaro.org> wrote:
> From: Stefan Weil via <qemu-devel@nongnu.org>
>
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Message-Id: <20230409201828.1159568-1-sw@weilnetz.de>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Thomas already sent a pull request with this one in it.
https://lore.kernel.org/qemu-devel/20230420101216.786304-4-thuth@redhat.com/
> ---
> docs/system/devices/cxl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>
> CXL Root Ports (CXL RP)
> ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
> There are a number of CXL specific Designated Vendor Specific
> Extended Capabilities (DVSEC) in PCIe Configuration Space
> and associated component register access via PCI bars.