1
This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v2: added a missing #include qemu/error-report.h which only causes
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we were using uninitialized data for the guarded bit when
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build failure in some configs, not all.
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combining stage 1 and stage 2 attrs.
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3
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thanks
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The following changes since commit 853546f8128476eefb701d4a55b2781bb3a46faa:
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-- PMM
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5
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into staging (2024-03-22 10:59:57 +0000)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240325-1
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to fe3e38390126c2202292911c49d46fc7ee4a163a:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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tests/qtest/libqtest.c: Check for g_setenv() failure (2024-03-25 14:17:07 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* Fixes for seven minor coverity issues
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Peter Maydell (7):
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target/arm: PTE bit GP only applies to stage1
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tests/qtest/npcm7xx_emc_test: Don't leak cmd_line
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target/arm: Copy guarded bit in combine_cacheattrs
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tests/unit/socket-helpers: Don't close(-1)
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net/af-xdp.c: Don't leak sock_fds array in net_init_af_xdp()
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hw/misc/pca9554: Correct error check bounds in get/set pin functions
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hw/nvram/mac_nvram: Report failure to write data
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tests/unit/test-throttle: Avoid unintended integer division
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tests/qtest/libqtest.c: Check for g_setenv() failure
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target/arm/ptw.c | 11 ++++++-----
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hw/misc/pca9554.c | 4 ++--
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1 file changed, 6 insertions(+), 5 deletions(-)
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hw/nvram/mac_nvram.c | 6 +++++-
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net/af-xdp.c | 3 +--
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tests/qtest/libqtest.c | 6 +++++-
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tests/qtest/npcm7xx_emc-test.c | 4 ++--
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tests/unit/socket-helpers.c | 4 +++-
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tests/unit/test-throttle.c | 4 ++--
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7 files changed, 20 insertions(+), 11 deletions(-)
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
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1
3
Only perform the extract of GP during the stage1 walk.
4
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
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1
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The guarded bit comes from the stage1 walk.
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5
Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib