1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: | 1 | v2: added a missing #include qemu/error-report.h which only causes |
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2 | we were using uninitialized data for the guarded bit when | 2 | build failure in some configs, not all. |
3 | combining stage 1 and stage 2 attrs. | ||
4 | 3 | ||
5 | thanks | 4 | The following changes since commit 853546f8128476eefb701d4a55b2781bb3a46faa: |
6 | -- PMM | ||
7 | 5 | ||
8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: | 6 | Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into staging (2024-03-22 10:59:57 +0000) |
9 | |||
10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) | ||
11 | 7 | ||
12 | are available in the Git repository at: | 8 | are available in the Git repository at: |
13 | 9 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 | 10 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240325-1 |
15 | 11 | ||
16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: | 12 | for you to fetch changes up to fe3e38390126c2202292911c49d46fc7ee4a163a: |
17 | 13 | ||
18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) | 14 | tests/qtest/libqtest.c: Check for g_setenv() failure (2024-03-25 14:17:07 +0000) |
19 | 15 | ||
20 | ---------------------------------------------------------------- | 16 | ---------------------------------------------------------------- |
21 | target-arm: Fix bug where we weren't initializing | 17 | target-arm queue: |
22 | guarded bit state when combining S1/S2 attrs | 18 | * Fixes for seven minor coverity issues |
23 | 19 | ||
24 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
25 | Richard Henderson (2): | 21 | Peter Maydell (7): |
26 | target/arm: PTE bit GP only applies to stage1 | 22 | tests/qtest/npcm7xx_emc_test: Don't leak cmd_line |
27 | target/arm: Copy guarded bit in combine_cacheattrs | 23 | tests/unit/socket-helpers: Don't close(-1) |
24 | net/af-xdp.c: Don't leak sock_fds array in net_init_af_xdp() | ||
25 | hw/misc/pca9554: Correct error check bounds in get/set pin functions | ||
26 | hw/nvram/mac_nvram: Report failure to write data | ||
27 | tests/unit/test-throttle: Avoid unintended integer division | ||
28 | tests/qtest/libqtest.c: Check for g_setenv() failure | ||
28 | 29 | ||
29 | target/arm/ptw.c | 11 ++++++----- | 30 | hw/misc/pca9554.c | 4 ++-- |
30 | 1 file changed, 6 insertions(+), 5 deletions(-) | 31 | hw/nvram/mac_nvram.c | 6 +++++- |
32 | net/af-xdp.c | 3 +-- | ||
33 | tests/qtest/libqtest.c | 6 +++++- | ||
34 | tests/qtest/npcm7xx_emc-test.c | 4 ++-- | ||
35 | tests/unit/socket-helpers.c | 4 +++- | ||
36 | tests/unit/test-throttle.c | 4 ++-- | ||
37 | 7 files changed, 20 insertions(+), 11 deletions(-) | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Only perform the extract of GP during the stage1 walk. | ||
4 | |||
5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/ptw.c | 10 +++++----- | ||
12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/ptw.c | ||
17 | +++ b/target/arm/ptw.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
19 | result->f.attrs.secure = false; | ||
20 | } | ||
21 | |||
22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
25 | - } | ||
26 | - | ||
27 | if (regime_is_stage2(mmu_idx)) { | ||
28 | result->cacheattrs.is_s2_format = true; | ||
29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
31 | assert(attrindx <= 7); | ||
32 | result->cacheattrs.is_s2_format = false; | ||
33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
34 | + | ||
35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
38 | + } | ||
39 | } | ||
40 | |||
41 | /* | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The guarded bit comes from the stage1 walk. | ||
4 | |||
5 | Fixes: Coverity CID 1507929 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/ptw.c | 1 + | ||
12 | 1 file changed, 1 insertion(+) | ||
13 | |||
14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/ptw.c | ||
17 | +++ b/target/arm/ptw.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
19 | |||
20 | assert(!s1.is_s2_format); | ||
21 | ret.is_s2_format = false; | ||
22 | + ret.guarded = s1.guarded; | ||
23 | |||
24 | if (s1.attrs == 0xf0) { | ||
25 | tagged = true; | ||
26 | -- | ||
27 | 2.34.1 | diff view generated by jsdifflib |