| 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: | 1 | v2: fix format string error |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | ||
| 3 | combining stage 1 and stage 2 attrs. | ||
| 4 | 2 | ||
| 5 | thanks | 3 | thanks |
| 6 | -- PMM | 4 | -- PMM |
| 7 | 5 | ||
| 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: | 6 | The following changes since commit aa9bbd865502ed517624ab6fe7d4b5d89ca95e43: |
| 9 | 7 | ||
| 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) | 8 | Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into staging (2023-05-29 14:31:52 -0700) |
| 11 | 9 | ||
| 12 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 13 | 11 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230530-1 |
| 15 | 13 | ||
| 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: | 14 | for you to fetch changes up to ec683110def96b16be3931ec87baba65a3dc5ad0: |
| 17 | 15 | ||
| 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) | 16 | docs: sbsa: correct graphics card name (2023-05-30 15:50:17 +0100) |
| 19 | 17 | ||
| 20 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 21 | target-arm: Fix bug where we weren't initializing | 19 | target-arm queue: |
| 22 | guarded bit state when combining S1/S2 attrs | 20 | * fsl-imx6: Add SNVS support for i.MX6 boards |
| 21 | * smmuv3: Add support for stage 2 translations | ||
| 22 | * hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop | ||
| 23 | * hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number | ||
| 24 | * cleanups for recent Kconfig changes | ||
| 25 | * target/arm: Explicitly select short-format FSR for M-profile | ||
| 26 | * tests/qtest: Run arm-specific tests only if the required machine is available | ||
| 27 | * hw/arm/sbsa-ref: add GIC node into DT | ||
| 28 | * docs: sbsa: correct graphics card name | ||
| 29 | * Update copyright dates to 2023 | ||
| 23 | 30 | ||
| 24 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
| 25 | Richard Henderson (2): | 32 | Clément Chigot (1): |
| 26 | target/arm: PTE bit GP only applies to stage1 | 33 | hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number |
| 27 | target/arm: Copy guarded bit in combine_cacheattrs | ||
| 28 | 34 | ||
| 29 | target/arm/ptw.c | 11 ++++++----- | 35 | Enze Li (1): |
| 30 | 1 file changed, 6 insertions(+), 5 deletions(-) | 36 | Update copyright dates to 2023 |
| 37 | |||
| 38 | Fabiano Rosas (3): | ||
| 39 | target/arm: Explain why we need to select ARM_V7M | ||
| 40 | arm/Kconfig: Keep Kconfig default entries in default.mak as documentation | ||
| 41 | arm/Kconfig: Make TCG dependence explicit | ||
| 42 | |||
| 43 | Marcin Juszkiewicz (2): | ||
| 44 | hw/arm/sbsa-ref: add GIC node into DT | ||
| 45 | docs: sbsa: correct graphics card name | ||
| 46 | |||
| 47 | Mostafa Saleh (10): | ||
| 48 | hw/arm/smmuv3: Add missing fields for IDR0 | ||
| 49 | hw/arm/smmuv3: Update translation config to hold stage-2 | ||
| 50 | hw/arm/smmuv3: Refactor stage-1 PTW | ||
| 51 | hw/arm/smmuv3: Add page table walk for stage-2 | ||
| 52 | hw/arm/smmuv3: Parse STE config for stage-2 | ||
| 53 | hw/arm/smmuv3: Make TLB lookup work for stage-2 | ||
| 54 | hw/arm/smmuv3: Add VMID to TLB tagging | ||
| 55 | hw/arm/smmuv3: Add CMDs related to stage-2 | ||
| 56 | hw/arm/smmuv3: Add stage-2 support in iova notifier | ||
| 57 | hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 | ||
| 58 | |||
| 59 | Peter Maydell (1): | ||
| 60 | target/arm: Explicitly select short-format FSR for M-profile | ||
| 61 | |||
| 62 | Thomas Huth (1): | ||
| 63 | tests/qtest: Run arm-specific tests only if the required machine is available | ||
| 64 | |||
| 65 | Tommy Wu (1): | ||
| 66 | hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop. | ||
| 67 | |||
| 68 | Vitaly Cheptsov (1): | ||
| 69 | fsl-imx6: Add SNVS support for i.MX6 boards | ||
| 70 | |||
| 71 | docs/conf.py | 2 +- | ||
| 72 | docs/system/arm/sbsa.rst | 2 +- | ||
| 73 | configs/devices/aarch64-softmmu/default.mak | 6 + | ||
| 74 | configs/devices/arm-softmmu/default.mak | 40 ++++ | ||
| 75 | hw/arm/smmu-internal.h | 37 +++ | ||
| 76 | hw/arm/smmuv3-internal.h | 12 +- | ||
| 77 | include/hw/arm/fsl-imx6.h | 2 + | ||
| 78 | include/hw/arm/smmu-common.h | 45 +++- | ||
| 79 | include/hw/arm/smmuv3.h | 4 + | ||
| 80 | include/qemu/help-texts.h | 2 +- | ||
| 81 | hw/arm/fsl-imx6.c | 8 + | ||
| 82 | hw/arm/sbsa-ref.c | 19 +- | ||
| 83 | hw/arm/smmu-common.c | 209 ++++++++++++++-- | ||
| 84 | hw/arm/smmuv3.c | 358 ++++++++++++++++++++++++---- | ||
| 85 | hw/arm/xlnx-zynqmp.c | 2 +- | ||
| 86 | hw/dma/xilinx_axidma.c | 11 +- | ||
| 87 | target/arm/tcg/tlb_helper.c | 13 +- | ||
| 88 | hw/arm/Kconfig | 123 ++++++---- | ||
| 89 | hw/arm/trace-events | 14 +- | ||
| 90 | target/arm/Kconfig | 3 + | ||
| 91 | tests/qtest/meson.build | 7 +- | ||
| 92 | 21 files changed, 774 insertions(+), 145 deletions(-) | ||
| 93 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The guarded bit comes from the stage1 walk. | ||
| 4 | |||
| 5 | Fixes: Coverity CID 1507929 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 1 + | ||
| 12 | 1 file changed, 1 insertion(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
| 19 | |||
| 20 | assert(!s1.is_s2_format); | ||
| 21 | ret.is_s2_format = false; | ||
| 22 | + ret.guarded = s1.guarded; | ||
| 23 | |||
| 24 | if (s1.attrs == 0xf0) { | ||
| 25 | tagged = true; | ||
| 26 | -- | ||
| 27 | 2.34.1 | diff view generated by jsdifflib |