[PULL 0/2] target-arm queue
[PULL v2 00/34] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v2 changes: dropped the patch that enables the new 'notcg' CI test:
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we were using uninitialized data for the guarded bit when
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it doesn't pass on our aarch64 runner because the CI runner doesn't
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combining stage 1 and stage 2 attrs.
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have access to /dev/kvm.
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 7c18f2d663521f1b31b821a13358ce38075eaf7d:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-04-29 23:07:17 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230502-2
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to a4ae17e5ec512862bf73e40dfbb1e7db71f2c1e7:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields (2023-05-02 15:47:41 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* Support building Arm targets with CONFIG_TCG=no (ie KVM only)
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* hw/net: npcm7xx_emc: set MAC in register space
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* hw/arm/bcm2835_property: Implement "get command line" message
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* Deprecate the '-singlestep' command line option in favour of
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'-one-insn-per-tb' and '-accel one-insn-per-tb=on'
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* Deprecate 'singlestep' member of QMP StatusInfo struct
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* docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation
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* hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc()
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* raspi, aspeed: Write bootloader code correctly on big-endian hosts
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* hw/intc/allwinner-a10-pic: Fix bug on big-endian hosts
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* Fix bug in A32 ERET on big-endian hosts that caused guest crash
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* hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields
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* hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Claudio Fontana (1):
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target/arm: PTE bit GP only applies to stage1
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target/arm: move cpu_tcg to tcg/cpu32.c
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target/arm: Copy guarded bit in combine_cacheattrs
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target/arm/ptw.c | 11 ++++++-----
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Cédric Le Goater (2):
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1 file changed, 6 insertions(+), 5 deletions(-)
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hw/arm/boot: Make write_bootloader() public as arm_write_bootloader()
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hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader
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Daniel Bertalan (1):
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hw/arm/bcm2835_property: Implement "get command line" message
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Fabiano Rosas (11):
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target/arm: Move cortex sysregs into a separate file
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target/arm: Remove dead code from cpu_max_set_sve_max_vq
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target/arm: Extract TCG -cpu max code into a function
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target/arm: Do not expose all -cpu max features to qtests
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target/arm: Move 64-bit TCG CPUs into tcg/
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tests/qtest: Adjust and document query-cpu-model-expansion test for arm
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tests/qtest: Fix tests when no KVM or TCG are present
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tests/avocado: Pass parameters to migration test
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arm/Kconfig: Always select SEMIHOSTING when TCG is present
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arm/Kconfig: Do not build TCG-only boards on a KVM-only build
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tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG
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Patrick Venture (1):
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hw/net: npcm7xx_emc: set MAC in register space
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Peter Maydell (18):
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make one-insn-per-tb an accel option
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softmmu: Don't use 'singlestep' global in QMP and HMP commands
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accel/tcg: Use one_insn_per_tb global instead of old singlestep global
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linux-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'
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bsd-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'
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Document that -singlestep command line option is deprecated
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accel/tcg: Report one-insn-per-tb in 'info jit', not 'info status'
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hmp: Add 'one-insn-per-tb' command equivalent to 'singlestep'
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qapi/run-state.json: Fix missing newline at end of file
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qmp: Deprecate 'singlestep' member of StatusInfo
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docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation
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hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc()
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hw/arm/raspi: Use arm_write_bootloader() to write boot code
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hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()
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target/arm: Define and use new load_cpu_field_low32()
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target/arm: Add compile time asserts to load/store_cpu_field macros
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hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields
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hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields
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docs/about/deprecated.rst | 43 +-
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docs/user/main.rst | 14 +-
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configs/devices/aarch64-softmmu/default.mak | 4 -
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configs/devices/arm-softmmu/default.mak | 39 --
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qapi/run-state.json | 16 +-
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accel/tcg/internal.h | 2 +
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include/exec/cpu-common.h | 2 -
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include/hw/arm/boot.h | 49 ++
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include/hw/misc/bcm2835_property.h | 1 +
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include/monitor/hmp.h | 2 +-
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target/arm/cpregs.h | 6 +
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target/arm/internals.h | 10 +-
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target/arm/translate-a32.h | 24 +-
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accel/tcg/cpu-exec.c | 2 +-
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accel/tcg/monitor.c | 14 +
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accel/tcg/tcg-all.c | 23 +
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bsd-user/main.c | 14 +-
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hw/arm/aspeed.c | 38 +-
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hw/arm/bcm2835_peripherals.c | 2 +
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hw/arm/bcm2836.c | 2 +
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hw/arm/boot.c | 35 +-
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hw/arm/raspi.c | 66 +--
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hw/arm/virt.c | 6 +-
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hw/intc/allwinner-a10-pic.c | 7 +-
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hw/misc/bcm2835_property.c | 13 +-
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hw/net/allwinner-sun8i-emac.c | 22 +-
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hw/net/msf2-emac.c | 16 +-
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hw/net/npcm7xx_emc.c | 32 +-
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hw/sd/allwinner-sdhost.c | 31 +-
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linux-user/main.c | 18 +-
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softmmu/globals.c | 1 -
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softmmu/runstate-hmp-cmds.c | 25 +-
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softmmu/runstate.c | 10 +-
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softmmu/vl.c | 17 +-
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target/arm/cortex-regs.c | 69 +++
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target/arm/cpu64.c | 702 +--------------------------
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target/arm/{cpu_tcg.c => tcg/cpu32.c} | 72 +--
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target/arm/tcg/cpu64.c | 723 ++++++++++++++++++++++++++++
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target/arm/tcg/translate.c | 4 +-
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tests/qtest/arm-cpu-features.c | 20 +-
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tests/qtest/bios-tables-test.c | 11 +-
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tests/qtest/boot-serial-test.c | 5 +
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tests/qtest/migration-test.c | 9 +-
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tests/qtest/pxe-test.c | 8 +-
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tests/qtest/test-hmp.c | 1 +
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tests/qtest/vmgenid-test.c | 9 +-
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hmp-commands.hx | 25 +-
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hw/arm/Kconfig | 43 +-
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qemu-options.hx | 12 +-
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target/arm/Kconfig | 7 +
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target/arm/meson.build | 2 +-
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target/arm/tcg/meson.build | 2 +
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tcg/tci/README | 2 +-
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tests/avocado/migration.py | 83 +++-
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tests/qtest/meson.build | 3 +-
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55 files changed, 1438 insertions(+), 980 deletions(-)
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create mode 100644 target/arm/cortex-regs.c
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rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (93%)
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create mode 100644 target/arm/tcg/cpu64.c
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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