[PULL 0/2] target-arm queue
[PULL v2 00/38] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v1->v2: fix up format string issues in aspeed_i3c.c
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit b10d00d8811fa4eed4862963273d7353ce310c82:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20220118-pull-request' into staging (2022-01-19 18:46:28 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220120-1
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to b9d383ab797f54ae5fa8746117770709921dc529:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR (2022-01-20 16:04:58 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm:
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guarded bit state when combining S1/S2 attrs
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* hw/intc/arm_gicv3_its: Fix various minor bugs
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* hw/arm/aspeed: Add the i3c device to the AST2600 SoC
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* hw/arm: kudo: add lm75s behind bus 1 switch at 75
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* hw/arm/virt: Fix support for running guests on hosts
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with restricted IPA ranges
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* hw/intc/arm_gic: Allow reset of the running priority
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* hw/intc/arm_gic: Implement read of GICC_IIDR
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* hw/arm/virt: Support for virtio-mem-pci
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* hw/arm/virt: Support CPU cluster on ARM virt machine
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* docs/can: convert to restructuredText
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* hw/net: Move MV88W8618 network device out of hw/arm/ directory
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* hw/arm/virt: KVM: Enable PAuth when supported by the host
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Gavin Shan (2):
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target/arm: PTE bit GP only applies to stage1
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virtio-mem: Correct default THP size for ARM64
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/arm/virt: Support for virtio-mem-pci
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target/arm/ptw.c | 11 ++++++-----
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Lucas Ramage (1):
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1 file changed, 6 insertions(+), 5 deletions(-)
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docs/can: convert to restructuredText
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Marc Zyngier (7):
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hw/arm/virt: KVM: Enable PAuth when supported by the host
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hw/arm/virt: Add a control for the the highmem PCIe MMIO
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hw/arm/virt: Add a control for the the highmem redistributors
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hw/arm/virt: Honor highmem setting when computing the memory map
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hw/arm/virt: Use the PA range to compute the memory map
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hw/arm/virt: Disable highmem devices that don't fit in the PA range
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hw/arm/virt: Drop superfluous checks against highmem
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Patrick Venture (1):
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hw/arm: kudo add lm75s behind bus 1 switch at 75
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Peter Maydell (13):
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hw/intc/arm_gicv3_its: Fix event ID bounds checks
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hw/intc/arm_gicv3_its: Convert int ID check to num_intids convention
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hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() return value
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hw/intc/arm_gicv3_its: Don't use data if reading command failed
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hw/intc/arm_gicv3_its: Use enum for return value of process_* functions
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hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd()
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hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting
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hw/intc/arm_gicv3_its: Fix return codes in process_mapti()
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hw/intc/arm_gicv3_its: Fix return codes in process_mapc()
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hw/intc/arm_gicv3_its: Fix return codes in process_mapd()
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hw/intc/arm_gicv3_its: Factor out "find address of table entry" code
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hw/intc/arm_gicv3_its: Check indexes before use, not after
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hw/intc/arm_gicv3_its: Range-check ICID before indexing into collection table
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Petr Pavlu (2):
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hw/intc/arm_gic: Implement read of GICC_IIDR
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hw/intc/arm_gic: Allow reset of the running priority
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Philippe Mathieu-Daudé (4):
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hw: Move MARVELL_88W8618 Kconfig from audio/ to arm/
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hw/arm/musicpal: Fix coding style of code related to MV88W8618 device
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hw/net: Move MV88W8618 network device out of hw/arm/ directory
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hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR
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Troy Lee (2):
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hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model.
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hw/arm/aspeed: Add the i3c device to the AST2600 SoC
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Yanan Wang (6):
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hw/arm/virt: Support CPU cluster on ARM virt machine
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hw/arm/virt: Support cluster level in DT cpu-map
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hw/acpi/aml-build: Improve scalability of PPTT generation
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tests/acpi/bios-tables-test: Allow changes to virt/PPTT file
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hw/acpi/aml-build: Support cluster level in PPTT generation
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tests/acpi/bios-table-test: Update expected virt/PPTT file
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docs/system/arm/cpu-features.rst | 4 -
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docs/system/device-emulation.rst | 1 +
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docs/{can.txt => system/devices/can.rst} | 90 +++---
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include/hw/arm/aspeed_soc.h | 3 +
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include/hw/arm/virt.h | 5 +-
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include/hw/misc/aspeed_i3c.h | 48 +++
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include/hw/net/mv88w8618_eth.h | 12 +
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target/arm/cpu.h | 1 +
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hw/acpi/aml-build.c | 68 +++--
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hw/arm/aspeed_ast2600.c | 16 +
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hw/arm/musicpal.c | 381 +-----------------------
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hw/arm/npcm7xx_boards.c | 10 +-
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hw/arm/virt-acpi-build.c | 10 +-
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hw/arm/virt.c | 184 ++++++++++--
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hw/intc/arm_gic.c | 11 +
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hw/intc/arm_gicv3_its.c | 492 ++++++++++++++-----------------
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hw/intc/arm_gicv3_redist.c | 4 +-
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hw/misc/aspeed_i3c.c | 384 ++++++++++++++++++++++++
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hw/net/mv88w8618_eth.c | 403 +++++++++++++++++++++++++
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hw/virtio/virtio-mem.c | 36 ++-
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target/arm/cpu.c | 16 +-
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target/arm/cpu64.c | 31 +-
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target/arm/kvm64.c | 21 ++
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MAINTAINERS | 2 +
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hw/arm/Kconfig | 4 +
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hw/audio/Kconfig | 3 -
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hw/misc/meson.build | 1 +
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hw/misc/trace-events | 6 +
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hw/net/meson.build | 1 +
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qemu-options.hx | 10 +
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tests/data/acpi/virt/PPTT | Bin 76 -> 96 bytes
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31 files changed, 1476 insertions(+), 782 deletions(-)
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rename docs/{can.txt => system/devices/can.rst} (68%)
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create mode 100644 include/hw/misc/aspeed_i3c.h
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create mode 100644 include/hw/net/mv88w8618_eth.h
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create mode 100644 hw/misc/aspeed_i3c.c
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create mode 100644 hw/net/mv88w8618_eth.c
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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