[PULL 0/2] target-arm queue
[PULL v2 00/23] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v1->v2: fix format string nit in ITS patches (%lu used when PRIu64 needed)
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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thanks
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The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5:
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-1
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 925e3b205bb17af52ac06c7bdd9d84b27345a4e9:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 19:36:50 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* mark MPS2/MPS3 board-internal i2c buses as 'full' so that command
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line user-created devices are not plugged into them
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* Take an exception if PSTATE.IL is set
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* Support an emulated ITS in the virt board
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* Add support for kudo-bmc board
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* Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
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* cadence_uart: Fix clock handling issues that prevented
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u-boot from running
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Bin Meng (6):
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target/arm: PTE bit GP only applies to stage1
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hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/char: cadence_uart: Disable transmit when input clock is disabled
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hw/char: cadence_uart: Move clock/reset check to uart_can_receive()
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hw/char: cadence_uart: Convert to memop_with_attrs() ops
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hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}()
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hw/char: cadence_uart: Log a guest error when device is unclocked or in reset
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target/arm/ptw.c | 11 ++++++-----
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Chris Rauer (1):
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1 file changed, 6 insertions(+), 5 deletions(-)
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hw/arm: Add support for kudo-bmc board.
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Marc Zyngier (1):
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hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
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Peter Maydell (5):
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target/arm: Take an exception if PSTATE.IL is set
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qdev: Support marking individual buses as 'full'
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hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
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hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
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hw/arm/mps2.c: Mark internal-only I2C buses as 'full'
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Richard Henderson (1):
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target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn
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Shashi Mallela (9):
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hw/intc: GICv3 ITS initial framework
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hw/intc: GICv3 ITS register definitions added
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hw/intc: GICv3 ITS command queue framework
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hw/intc: GICv3 ITS Command processing
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hw/intc: GICv3 ITS Feature enablement
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hw/intc: GICv3 redistributor ITS processing
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tests/data/acpi/virt: Add IORT files for ITS
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hw/arm/virt: add ITS support in virt GIC
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tests/data/acpi/virt: Update IORT files for ITS
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docs/system/arm/nuvoton.rst | 1 +
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hw/intc/gicv3_internal.h | 188 ++++-
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include/hw/arm/virt.h | 2 +
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include/hw/intc/arm_gicv3_common.h | 13 +
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include/hw/intc/arm_gicv3_its_common.h | 32 +-
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include/hw/qdev-core.h | 24 +
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target/arm/cpu.h | 1 +
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target/arm/kvm_arm.h | 4 +-
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target/arm/syndrome.h | 5 +
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target/arm/translate.h | 2 +
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hw/arm/mps2-tz.c | 92 ++-
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hw/arm/mps2.c | 12 +-
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hw/arm/npcm7xx_boards.c | 34 +
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hw/arm/virt.c | 29 +-
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hw/char/cadence_uart.c | 61 +-
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hw/intc/arm_gicv3.c | 14 +
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hw/intc/arm_gicv3_common.c | 13 +
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hw/intc/arm_gicv3_cpuif.c | 7 +-
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hw/intc/arm_gicv3_dist.c | 5 +-
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hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++
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hw/intc/arm_gicv3_its_common.c | 7 +-
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hw/intc/arm_gicv3_its_kvm.c | 2 +-
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hw/intc/arm_gicv3_redist.c | 153 +++-
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hw/misc/zynq_slcr.c | 31 +-
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softmmu/qdev-monitor.c | 7 +-
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target/arm/helper-a64.c | 1 +
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target/arm/helper.c | 8 +
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target/arm/kvm.c | 7 +-
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target/arm/translate-a64.c | 255 +++---
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target/arm/translate.c | 21 +
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hw/intc/meson.build | 1 +
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tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
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tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
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tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes
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tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes
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35 files changed, 2144 insertions(+), 210 deletions(-)
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create mode 100644 hw/intc/arm_gicv3_its.c
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create mode 100644 tests/data/acpi/virt/IORT
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create mode 100644 tests/data/acpi/virt/IORT.memhp
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create mode 100644 tests/data/acpi/virt/IORT.numamem
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create mode 100644 tests/data/acpi/virt/IORT.pxb
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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