| 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: | 1 | v2: fix compile issue when building user-mode emulators with clang |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | ||
| 3 | combining stage 1 and stage 2 attrs. | ||
| 4 | 2 | ||
| 5 | thanks | ||
| 6 | -- PMM | 3 | -- PMM |
| 7 | 4 | ||
| 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: | 5 | The following changes since commit 4cc10cae64c51e17844dc4358481c393d7bf1ed4: |
| 9 | 6 | ||
| 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) | 7 | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-05-06 18:56:17 +0100) |
| 11 | 8 | ||
| 12 | are available in the Git repository at: | 9 | are available in the Git repository at: |
| 13 | 10 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210510-1 |
| 15 | 12 | ||
| 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: | 13 | for you to fetch changes up to c3080fbdaa381012666428fef2e5f7ce422ecfee: |
| 17 | 14 | ||
| 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) | 15 | hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 (2021-05-10 17:21:54 +0100) |
| 19 | 16 | ||
| 20 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
| 21 | target-arm: Fix bug where we weren't initializing | 18 | target-arm queue: |
| 22 | guarded bit state when combining S1/S2 attrs | 19 | * docs: fix link in sbsa description |
| 20 | * linux-user/aarch64: Enable hwcap for RND, BTI, and MTE | ||
| 21 | * target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() | ||
| 22 | * target/arm: Split neon and vfp translation to their own | ||
| 23 | compilation units | ||
| 24 | * target/arm: Make WFI a NOP for userspace emulators | ||
| 25 | * hw/sd/omap_mmc: Use device_cold_reset() instead of | ||
| 26 | device_legacy_reset() | ||
| 27 | * include: More fixes for 'extern "C"' block use | ||
| 28 | * hw/arm/imx25_pdk: Fix error message for invalid RAM size | ||
| 29 | * hw/arm/mps2-tz: Implement AN524 memory remapping via machine property | ||
| 30 | * hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 | ||
| 23 | 31 | ||
| 24 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
| 25 | Richard Henderson (2): | 33 | Alex Bennée (1): |
| 26 | target/arm: PTE bit GP only applies to stage1 | 34 | docs: fix link in sbsa description |
| 27 | target/arm: Copy guarded bit in combine_cacheattrs | ||
| 28 | 35 | ||
| 29 | target/arm/ptw.c | 11 ++++++----- | 36 | Guenter Roeck (1): |
| 30 | 1 file changed, 6 insertions(+), 5 deletions(-) | 37 | hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 |
| 38 | |||
| 39 | Peter Maydell (22): | ||
| 40 | target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() | ||
| 41 | target/arm: Move constant expanders to translate.h | ||
| 42 | target/arm: Share unallocated_encoding() and gen_exception_insn() | ||
| 43 | target/arm: Make functions used by m-nocp global | ||
| 44 | target/arm: Split m-nocp trans functions into their own file | ||
| 45 | target/arm: Move gen_aa32 functions to translate-a32.h | ||
| 46 | target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc | ||
| 47 | target/arm: Make functions used by translate-vfp global | ||
| 48 | target/arm: Make translate-vfp.c.inc its own compilation unit | ||
| 49 | target/arm: Move vfp_reg_ptr() to translate-neon.c.inc | ||
| 50 | target/arm: Delete unused typedef | ||
| 51 | target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h | ||
| 52 | target/arm: Make functions used by translate-neon global | ||
| 53 | target/arm: Make translate-neon.c.inc its own compilation unit | ||
| 54 | target/arm: Make WFI a NOP for userspace emulators | ||
| 55 | hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset() | ||
| 56 | osdep: Make os-win32.h and os-posix.h handle 'extern "C"' themselves | ||
| 57 | include/qemu/bswap.h: Handle being included outside extern "C" block | ||
| 58 | include/disas/dis-asm.h: Handle being included outside 'extern "C"' | ||
| 59 | hw/misc/mps2-scc: Add "QEMU interface" comment | ||
| 60 | hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping | ||
| 61 | hw/arm/mps2-tz: Implement AN524 memory remapping via machine property | ||
| 62 | |||
| 63 | Philippe Mathieu-Daudé (1): | ||
| 64 | hw/arm/imx25_pdk: Fix error message for invalid RAM size | ||
| 65 | |||
| 66 | Richard Henderson (1): | ||
| 67 | linux-user/aarch64: Enable hwcap for RND, BTI, and MTE | ||
| 68 | |||
| 69 | docs/system/arm/mps2.rst | 10 + | ||
| 70 | docs/system/arm/sbsa.rst | 2 +- | ||
| 71 | include/disas/dis-asm.h | 12 +- | ||
| 72 | include/hw/misc/mps2-scc.h | 21 ++ | ||
| 73 | include/qemu/bswap.h | 26 ++- | ||
| 74 | include/qemu/osdep.h | 8 +- | ||
| 75 | include/sysemu/os-posix.h | 8 + | ||
| 76 | include/sysemu/os-win32.h | 8 + | ||
| 77 | target/arm/translate-a32.h | 144 +++++++++++++ | ||
| 78 | target/arm/translate-a64.h | 2 - | ||
| 79 | target/arm/translate.h | 29 +++ | ||
| 80 | hw/arm/imx25_pdk.c | 5 +- | ||
| 81 | hw/arm/mps2-tz.c | 108 +++++++++- | ||
| 82 | hw/arm/xilinx_zynq.c | 2 +- | ||
| 83 | hw/misc/mps2-scc.c | 13 +- | ||
| 84 | hw/sd/omap_mmc.c | 2 +- | ||
| 85 | linux-user/elfload.c | 13 ++ | ||
| 86 | target/arm/helper.c | 2 +- | ||
| 87 | target/arm/op_helper.c | 14 ++ | ||
| 88 | target/arm/translate-a64.c | 15 -- | ||
| 89 | target/arm/translate-m-nocp.c | 221 ++++++++++++++++++++ | ||
| 90 | .../arm/{translate-neon.c.inc => translate-neon.c} | 19 +- | ||
| 91 | .../arm/{translate-vfp.c.inc => translate-vfp.c} | 230 +++------------------ | ||
| 92 | target/arm/translate.c | 200 ++++-------------- | ||
| 93 | disas/arm-a64.cc | 2 - | ||
| 94 | disas/nanomips.cpp | 2 - | ||
| 95 | target/arm/meson.build | 15 +- | ||
| 96 | 27 files changed, 720 insertions(+), 413 deletions(-) | ||
| 97 | create mode 100644 target/arm/translate-a32.h | ||
| 98 | create mode 100644 target/arm/translate-m-nocp.c | ||
| 99 | rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%) | ||
| 100 | rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (94%) | ||
| 101 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The guarded bit comes from the stage1 walk. | ||
| 4 | |||
| 5 | Fixes: Coverity CID 1507929 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 1 + | ||
| 12 | 1 file changed, 1 insertion(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
| 19 | |||
| 20 | assert(!s1.is_s2_format); | ||
| 21 | ret.is_s2_format = false; | ||
| 22 | + ret.guarded = s1.guarded; | ||
| 23 | |||
| 24 | if (s1.attrs == 0xf0) { | ||
| 25 | tagged = true; | ||
| 26 | -- | ||
| 27 | 2.34.1 | diff view generated by jsdifflib |