[PULL 0/2] target-arm queue
[PULL v2 00/39] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v2: fix format-string issue in a test case.
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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2
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 6f34661b6c97a37a5efc27d31c037ddeda4547e2:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging (2021-03-11 18:55:27 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210314
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 6500ac13ff8e5c64ca69f5ef5d456028cfda6139:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/display/pxa2xx: Inline template header (2021-03-14 13:14:56 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* versal: Support XRAMs and XRAM controller
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* smmu: Various minor bug fixes
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* SVE emulation: fix bugs handling odd vector lengths
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* allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
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* tests/acceptance: fix orangepi-pc acceptance tests
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* hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
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* hw/arm/virt: KVM: The IPA lower bound is 32
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* npcm7xx: support MFT module
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* pl110, pxa2xx_lcd: tidy up template headers
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Andrew Jones (2):
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target/arm: PTE bit GP only applies to stage1
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accel: kvm: Fix kvm_type invocation
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/arm/virt: KVM: The IPA lower bound is 32
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target/arm/ptw.c | 11 ++++++-----
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Edgar E. Iglesias (2):
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1 file changed, 6 insertions(+), 5 deletions(-)
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hw/misc: versal: Add a model of the XRAM controller
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hw/arm: versal: Add support for the XRAMs
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Eric Auger (7):
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intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate
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dma: Introduce dma_aligned_pow2_mask()
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virtio-iommu: Handle non power of 2 range invalidations
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hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set
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hw/arm/smmuv3: Enforce invalidation on a power of two range
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hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling
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hw/arm/smmuv3: Uniformize sid traces
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Hao Wu (5):
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hw/misc: Add GPIOs for duty in NPCM7xx PWM
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hw/misc: Add NPCM7XX MFT Module
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hw/arm: Add MFT device to NPCM7xx Soc
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hw/arm: Connect PWM fans in NPCM7XX boards
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tests/qtest: Test PWM fan RPM using MFT in PWM test
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Niek Linnenbank (5):
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hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
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tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for orangepi-pc machine
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tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
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tests/acceptance: update sunxi kernel from armbian to 5.10.16
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tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
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Peter Maydell (9):
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hw/display/pl110: Remove dead code for non-32-bpp surfaces
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hw/display/pl110: Pull included-once parts of template header into pl110.c
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hw/display/pl110: Remove use of BITS from pl110_template.h
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hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
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hw/display/pxa2xx_lcd: Remove dest_width state field
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hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
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hw/display/pxa2xx: Apply brace-related coding style fixes to template header
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hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
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hw/display/pxa2xx: Inline template header
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Philippe Mathieu-Daudé (1):
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hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
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Richard Henderson (8):
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target/arm: Fix sve_uzp_p vs odd vector lengths
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target/arm: Fix sve_zip_p vs odd vector lengths
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target/arm: Fix sve_punpk_p vs odd vector lengths
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target/arm: Update find_last_active for PREDDESC
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target/arm: Update BRKA, BRKB, BRKN for PREDDESC
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target/arm: Update CNTP for PREDDESC
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target/arm: Update WHILE for PREDDESC
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target/arm: Update sve reduction vs simd_desc
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docs/system/arm/nuvoton.rst | 2 +-
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docs/system/arm/xlnx-versal-virt.rst | 1 +
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hw/arm/smmu-internal.h | 5 +
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hw/display/pl110_template.h | 120 +-------
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hw/display/pxa2xx_template.h | 447 ---------------------------
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include/hw/arm/npcm7xx.h | 13 +-
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include/hw/arm/xlnx-versal.h | 13 +
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include/hw/boards.h | 1 +
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include/hw/misc/npcm7xx_mft.h | 70 +++++
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include/hw/misc/npcm7xx_pwm.h | 4 +-
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include/hw/misc/xlnx-versal-xramc.h | 97 ++++++
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include/sysemu/dma.h | 12 +
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target/arm/kvm_arm.h | 6 +-
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accel/kvm/kvm-all.c | 2 +
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hw/arm/npcm7xx.c | 45 ++-
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hw/arm/npcm7xx_boards.c | 99 ++++++
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hw/arm/smmu-common.c | 32 +-
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hw/arm/smmuv3.c | 58 ++--
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hw/arm/virt.c | 23 +-
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hw/arm/xlnx-versal.c | 36 +++
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hw/display/pl110.c | 123 +++++---
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hw/display/pxa2xx_lcd.c | 520 ++++++++++++++++++++++++++-----
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hw/i386/intel_iommu.c | 32 +-
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hw/misc/npcm7xx_mft.c | 540 +++++++++++++++++++++++++++++++++
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hw/misc/npcm7xx_pwm.c | 4 +
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hw/misc/xlnx-versal-xramc.c | 253 +++++++++++++++
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hw/net/allwinner-sun8i-emac.c | 62 ++--
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hw/timer/sse-timer.c | 1 +
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hw/virtio/virtio-iommu.c | 19 +-
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softmmu/dma-helpers.c | 26 ++
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target/arm/kvm.c | 4 +-
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target/arm/sve_helper.c | 107 ++++---
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target/arm/translate-sve.c | 26 +-
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tests/qtest/npcm7xx_pwm-test.c | 205 ++++++++++++-
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hw/arm/trace-events | 24 +-
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hw/misc/meson.build | 2 +
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hw/misc/trace-events | 8 +
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tests/acceptance/boot_linux_console.py | 120 +++-----
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tests/acceptance/replay_kernel.py | 10 +-
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39 files changed, 2235 insertions(+), 937 deletions(-)
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delete mode 100644 hw/display/pxa2xx_template.h
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create mode 100644 include/hw/misc/npcm7xx_mft.h
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create mode 100644 include/hw/misc/xlnx-versal-xramc.h
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create mode 100644 hw/misc/npcm7xx_mft.c
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create mode 100644 hw/misc/xlnx-versal-xramc.c
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

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