[PULL 0/2] target-arm queue
[PULL v2 00/54] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v1->v2: fix format-string errors on 32-bit hosts in xilinx csu dma model.
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 0436c55edf6b357ff56e2a5bf688df8636f83456:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-03-08 13:51:41 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210310
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 81b3ddaf8772ec6f88d372e52f9b433cfa46bc46:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() (2021-03-10 13:54:51 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* Add new mps3-an547 board
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* target/arm: Restrict v7A TCG cpus to TCG accel
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* Implement a Xilinx CSU DMA model
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* hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Peter Maydell (48):
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target/arm: PTE bit GP only applies to stage1
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clock: Add ClockEvent parameter to callbacks
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target/arm: Copy guarded bit in combine_cacheattrs
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clock: Add ClockPreUpdate callback event type
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clock: Add clock_ns_to_ticks() function
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hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()
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hw/arm/armsse: Introduce SSE subsystem version property
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hw/misc/iotkit-sysctl: Remove is_sse200 flag
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hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values
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hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values
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hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
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hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
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hw/timer/sse-counter: Model the SSE Subsystem System Counter
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hw/timer/sse-timer: Model the SSE Subsystem System Timer
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hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
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hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
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hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
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hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register
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hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers
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hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values
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hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc
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hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
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hw/arm/armsse: Use an array for apb_ppc fields in the state structure
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hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
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hw/arm/armsse: Add framework for data-driven device placement
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hw/arm/armsse: Move dual-timer device into data-driven framework
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hw/arm/armsse: Move watchdogs into data-driven framework
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hw/arm/armsse: Move s32ktimer into data-driven framework
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hw/arm/armsse: Move sysinfo register block into data-driven framework
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hw/arm/armsse: Move sysctl register block into data-driven framework
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hw/arm/armsse: Move PPUs into data-driven framework
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hw/arm/armsse: Add missing SSE-200 SYS_PPU
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hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo
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hw/arm/armsse: Add support for SSE variants with a system counter
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hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo
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hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
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hw/arm/armsse: Add SSE-300 support
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hw/arm/mps2-tz: Make UART overflow IRQ board-specific
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hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
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hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
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hw/misc/mps2-scc: Implement changes for AN547
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hw/arm/mps2-tz: Support running APB peripherals on different clock
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hw/arm/mps2-tz: Make initsvtor0 setting board-specific
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hw/arm/mps2-tz: Add new mps3-an547 board
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docs/system/arm/mps2.rst: Document the new mps3-an547 board
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tests/qtest/sse-timer-test: Add simple test of the SSE counter
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tests/qtest/sse-timer-test: Test the system timer
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tests/qtest/sse-timer-test: Test counter scaling changes
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hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
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hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
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target/arm/ptw.c | 11 ++++++-----
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Philippe Mathieu-Daudé (1):
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1 file changed, 6 insertions(+), 5 deletions(-)
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target/arm: Restrict v7A TCG cpus to TCG accel
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Xuzhou Cheng (5):
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hw/dma: Implement a Xilinx CSU DMA model
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hw/arm: xlnx-zynqmp: Clean up coding convention issues
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hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
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hw/ssi: xilinx_spips: Clean up coding convention issues
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hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
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docs/devel/clocks.rst | 71 ++-
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docs/system/arm/mps2.rst | 6 +-
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include/hw/arm/armsse-version.h | 42 ++
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include/hw/arm/armsse.h | 40 +-
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include/hw/arm/xlnx-zynqmp.h | 5 +-
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include/hw/clock.h | 63 ++-
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include/hw/dma/xlnx_csu_dma.h | 52 ++
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include/hw/misc/armsse-cpu-pwrctrl.h | 40 ++
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include/hw/misc/iotkit-secctl.h | 2 +
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include/hw/misc/iotkit-sysctl.h | 13 +-
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include/hw/misc/iotkit-sysinfo.h | 2 +
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include/hw/misc/mps2-fpgaio.h | 2 +
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include/hw/qdev-clock.h | 17 +-
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include/hw/ssi/xilinx_spips.h | 2 +-
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include/hw/timer/sse-counter.h | 105 ++++
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include/hw/timer/sse-timer.h | 53 ++
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hw/adc/npcm7xx_adc.c | 2 +-
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hw/arm/armsse.c | 1008 +++++++++++++++++++++++++---------
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hw/arm/mps2-tz.c | 168 +++++-
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hw/arm/xlnx-zynqmp.c | 21 +-
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hw/char/cadence_uart.c | 4 +-
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hw/char/ibex_uart.c | 4 +-
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hw/char/pl011.c | 5 +-
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hw/core/clock.c | 24 +-
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hw/core/qdev-clock.c | 8 +-
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hw/dma/xlnx_csu_dma.c | 745 +++++++++++++++++++++++++
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hw/mips/cps.c | 2 +-
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hw/misc/armsse-cpu-pwrctrl.c | 149 +++++
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hw/misc/bcm2835_cprman.c | 23 +-
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hw/misc/iotkit-secctl.c | 50 +-
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hw/misc/iotkit-sysctl.c | 522 +++++++++++++++---
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hw/misc/iotkit-sysinfo.c | 51 +-
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hw/misc/mps2-fpgaio.c | 52 +-
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hw/misc/mps2-scc.c | 15 +-
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hw/misc/npcm7xx_clk.c | 26 +-
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hw/misc/npcm7xx_pwm.c | 2 +-
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hw/misc/zynq_slcr.c | 5 +-
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hw/ssi/xilinx_spips.c | 33 +-
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hw/timer/cmsdk-apb-dualtimer.c | 5 +-
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hw/timer/cmsdk-apb-timer.c | 4 +-
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hw/timer/npcm7xx_timer.c | 6 +-
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hw/timer/renesas_tmr.c | 33 +-
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hw/timer/sse-counter.c | 474 ++++++++++++++++
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hw/timer/sse-timer.c | 470 ++++++++++++++++
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hw/watchdog/cmsdk-apb-watchdog.c | 5 +-
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target/arm/cpu.c | 335 -----------
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target/arm/cpu_tcg.c | 318 +++++++++++
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target/mips/cpu.c | 2 +-
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tests/qtest/sse-timer-test.c | 240 ++++++++
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MAINTAINERS | 7 +
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hw/arm/Kconfig | 10 +-
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hw/dma/Kconfig | 4 +
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hw/dma/meson.build | 1 +
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hw/misc/Kconfig | 9 +
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hw/misc/meson.build | 1 +
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hw/misc/trace-events | 4 +
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hw/timer/Kconfig | 6 +
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hw/timer/meson.build | 2 +
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hw/timer/trace-events | 12 +
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tests/qtest/meson.build | 1 +
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60 files changed, 4537 insertions(+), 846 deletions(-)
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create mode 100644 include/hw/arm/armsse-version.h
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create mode 100644 include/hw/dma/xlnx_csu_dma.h
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create mode 100644 include/hw/misc/armsse-cpu-pwrctrl.h
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create mode 100644 include/hw/timer/sse-counter.h
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create mode 100644 include/hw/timer/sse-timer.h
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create mode 100644 hw/dma/xlnx_csu_dma.c
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create mode 100644 hw/misc/armsse-cpu-pwrctrl.c
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create mode 100644 hw/timer/sse-counter.c
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create mode 100644 hw/timer/sse-timer.c
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create mode 100644 tests/qtest/sse-timer-test.c
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

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