[PULL 0/2] target-arm queue
[PULL v3 00/49] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v3: fix test failure on 32-bit hosts due to new board defaulting to 2GB RAM.
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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2
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 9a7beaad3dbba982f7a461d676b55a5c3851d312:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging (2021-03-05 10:47:46 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210308
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 50b52b18cdb9294ce83dd49bb60b8e55a6526ea0:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/arm/mps2: Update old infocenter.arm.com URLs (2021-03-08 11:54:16 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* sbsa-ref: remove cortex-a53 from list of supported cpus
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* sbsa-ref: add 'max' to list of allowed cpus
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* target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
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* npcm7xx: add EMC model
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* xlnx-zynqmp: Remove obsolete 'has_rpu' property
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* target/arm: Speed up aarch64 TBL/TBX
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* virtio-mmio: improve virtio-mmio get_dev_path alog
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* target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
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* target/arm: Restrict v8M IDAU to TCG
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* target/arm/cpu: Update coding style to make checkpatch.pl happy
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* musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces
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* Add new board: mps3-an524
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Doug Evans (3):
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target/arm: PTE bit GP only applies to stage1
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hw/net: Add npcm7xx emc model
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/arm: Add npcm7xx emc model
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tests/qtests: Add npcm7xx emc model test
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target/arm/ptw.c | 11 ++++++-----
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Marcin Juszkiewicz (2):
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1 file changed, 6 insertions(+), 5 deletions(-)
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sbsa-ref: remove cortex-a53 from list of supported cpus
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sbsa-ref: add 'max' to list of allowed cpus
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Peter Collingbourne (1):
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target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
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Peter Maydell (34):
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hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces
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hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces
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hw/display/tc6393xb: Expand out macros in template header
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hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite
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hw/display/omap_lcdc: Expand out macros in template header
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hw/display/omap_lcdc: Drop broken bigendian ifdef
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hw/display/omap_lcdc: Fix coding style issues in template header
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hw/display/omap_lcdc: Inline template header into C file
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hw/display/omap_lcdc: Delete unnecessary macro
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hw/display/tcx: Drop unnecessary code for handling BGR format outputs
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hw/arm/mps2-tz: Make SYSCLK frequency board-specific
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hw/misc/mps2-scc: Support configurable number of OSCCLK values
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hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511
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hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board
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hw/misc/mps2-fpgaio: Make number of LEDs configurable by board
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hw/misc/mps2-fpgaio: Support SWITCH register
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hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board
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hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type
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hw/arm/mps2-tz: Make number of IRQs board-specific
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hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
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hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI
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hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts
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hw/arm/mps2-tz: Move device IRQ info to data structures
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hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
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hw/arm/mps2-tz: Allow boards to have different PPCInfo data
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hw/arm/mps2-tz: Make RAM arrangement board-specific
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hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data
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hw/arm/mps2-tz: Support ROMs as well as RAMs
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hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo
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hw/arm/mps2-tz: Add new mps3-an524 board
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hw/arm/mps2-tz: Stub out USB controller for mps3-an524
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hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
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docs/system/arm/mps2.rst: Document the new mps3-an524 board
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hw/arm/mps2: Update old infocenter.arm.com URLs
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Philippe Mathieu-Daudé (4):
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hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property
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hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init()
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target/arm: Restrict v8M IDAU to TCG
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target/arm/cpu: Update coding style to make checkpatch.pl happy
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Rebecca Cran (3):
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target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
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target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
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target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU
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Richard Henderson (1):
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target/arm: Speed up aarch64 TBL/TBX
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schspa (1):
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virtio-mmio: improve virtio-mmio get_dev_path alog
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docs/system/arm/mps2.rst | 24 +-
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docs/system/arm/nuvoton.rst | 3 +-
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hw/display/omap_lcd_template.h | 169 --------
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hw/display/tc6393xb_template.h | 72 ----
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include/hw/arm/armsse.h | 4 +-
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include/hw/arm/npcm7xx.h | 2 +
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include/hw/arm/xlnx-zynqmp.h | 2 -
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include/hw/misc/armsse-cpuid.h | 2 +-
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include/hw/misc/armsse-mhu.h | 2 +-
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include/hw/misc/iotkit-secctl.h | 2 +-
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include/hw/misc/iotkit-sysctl.h | 2 +-
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include/hw/misc/iotkit-sysinfo.h | 2 +-
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include/hw/misc/mps2-fpgaio.h | 8 +-
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include/hw/misc/mps2-scc.h | 10 +-
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include/hw/net/npcm7xx_emc.h | 286 +++++++++++++
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target/arm/cpu.h | 15 +-
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target/arm/helper-a64.h | 2 +-
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target/arm/internals.h | 6 +
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hw/arm/mps2-tz.c | 642 ++++++++++++++++++++++++-----
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hw/arm/mps2.c | 5 +
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hw/arm/musicpal.c | 64 ++-
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hw/arm/npcm7xx.c | 50 ++-
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hw/arm/sbsa-ref.c | 2 +-
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hw/arm/xlnx-zynqmp.c | 6 -
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hw/display/omap_lcdc.c | 129 +++++-
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hw/display/tc6393xb.c | 48 +--
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hw/display/tcx.c | 31 +-
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hw/i2c/npcm7xx_smbus.c | 1 -
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hw/misc/armsse-cpuid.c | 2 +-
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hw/misc/armsse-mhu.c | 2 +-
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hw/misc/iotkit-sysctl.c | 2 +-
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hw/misc/iotkit-sysinfo.c | 2 +-
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hw/misc/mps2-fpgaio.c | 43 +-
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hw/misc/mps2-scc.c | 93 ++++-
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hw/net/npcm7xx_emc.c | 857 ++++++++++++++++++++++++++++++++++++++
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hw/virtio/virtio-mmio.c | 13 +-
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target/arm/cpu.c | 23 +-
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target/arm/cpu64.c | 5 +
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target/arm/cpu_tcg.c | 8 +
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target/arm/helper-a64.c | 32 --
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target/arm/helper.c | 39 +-
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target/arm/mte_helper.c | 13 +-
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target/arm/translate-a64.c | 70 +---
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target/arm/vec_helper.c | 48 +++
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tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++++++++
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hw/net/meson.build | 1 +
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hw/net/trace-events | 17 +
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tests/qtest/meson.build | 3 +-
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48 files changed, 3108 insertions(+), 618 deletions(-)
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delete mode 100644 hw/display/omap_lcd_template.h
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delete mode 100644 hw/display/tc6393xb_template.h
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create mode 100644 include/hw/net/npcm7xx_emc.h
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create mode 100644 hw/net/npcm7xx_emc.c
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create mode 100644 tests/qtest/npcm7xx_emc-test.c
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

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