[PULL 0/2] target-arm queue
[PULL v2 00/37] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v2: dropped the npcm7xx ethernet device, whose test case
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we were using uninitialized data for the guarded bit when
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fails weirdly on the 'build-disabled' gitlab CI job:
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combining stage 1 and stage 2 attrs.
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https://gitlab.com/qemu-project/qemu/-/jobs/1034174731#L12
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thanks
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The following changes since commit 8ba4bca570ace1e60614a0808631a517cf5df67a:
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2021-02-15 17:13:57 +0000)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210217
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 59c7a187dd8bd8ef675768dd8af9de11528ea7e2:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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MAINTAINERS: add myself maintainer for the clock framework (2021-02-16 14:16:17 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* Support ARMv8.5-MemTag for linux-user
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* ncpm7xx: Support SMBus
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* MAINTAINERS: add section for Clock framework
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Hao Wu (5):
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target/arm: PTE bit GP only applies to stage1
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hw/i2c: Implement NPCM7XX SMBus Module Single Mode
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/arm: Add I2C sensors for NPCM750 eval board
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hw/arm: Add I2C sensors and EEPROM for GSJ machine
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hw/i2c: Add a QTest for NPCM7XX SMBus Device
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hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode
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target/arm/ptw.c | 11 ++++++-----
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Luc Michel (1):
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1 file changed, 6 insertions(+), 5 deletions(-)
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MAINTAINERS: add myself maintainer for the clock framework
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Richard Henderson (31):
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tcg: Introduce target-specific page data for user-only
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linux-user: Introduce PAGE_ANON
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exec: Use uintptr_t for guest_base
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exec: Use uintptr_t in cpu_ldst.h
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exec: Improve types for guest_addr_valid
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linux-user: Check for overflow in access_ok
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linux-user: Tidy VERIFY_READ/VERIFY_WRITE
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bsd-user: Tidy VERIFY_READ/VERIFY_WRITE
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linux-user: Do not use guest_addr_valid for h2g_valid
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linux-user: Fix guest_addr_valid vs reserved_va
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exec: Introduce cpu_untagged_addr
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exec: Use cpu_untagged_addr in g2h; split out g2h_untagged
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linux-user: Explicitly untag memory management syscalls
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linux-user: Use guest_range_valid in access_ok
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exec: Rename guest_{addr,range}_valid to *_untagged
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linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged
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linux-user: Move lock_user et al out of line
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linux-user: Fix types in uaccess.c
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linux-user: Handle tags in lock_user/unlock_user
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linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
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target/arm: Improve gen_top_byte_ignore
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target/arm: Use the proper TBI settings for linux-user
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linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG
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linux-user/aarch64: Implement PROT_MTE
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target/arm: Split out syndrome.h from internals.h
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linux-user/aarch64: Pass syndrome to EXC_*_ABORT
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linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault
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linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error
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target/arm: Add allocation tag storage for user mode
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target/arm: Enable MTE for user-only
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tests/tcg/aarch64: Add mte smoke tests
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docs/system/arm/nuvoton.rst | 2 +-
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bsd-user/qemu.h | 17 +-
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include/exec/cpu-all.h | 47 +-
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include/exec/cpu_ldst.h | 39 +-
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include/exec/exec-all.h | 2 +-
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include/hw/arm/npcm7xx.h | 2 +
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include/hw/i2c/npcm7xx_smbus.h | 113 ++++
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linux-user/aarch64/target_signal.h | 3 +
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linux-user/aarch64/target_syscall.h | 13 +
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linux-user/qemu.h | 76 +--
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linux-user/syscall_defs.h | 1 +
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target/arm/cpu-param.h | 3 +
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target/arm/cpu.h | 32 +
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target/arm/internals.h | 249 +-------
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target/arm/syndrome.h | 273 +++++++++
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tests/tcg/aarch64/mte.h | 60 ++
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accel/tcg/translate-all.c | 32 +-
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accel/tcg/user-exec.c | 51 +-
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bsd-user/elfload.c | 2 +-
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bsd-user/main.c | 8 +-
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bsd-user/mmap.c | 23 +-
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hw/arm/npcm7xx.c | 68 ++-
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hw/arm/npcm7xx_boards.c | 46 ++
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hw/i2c/npcm7xx_smbus.c | 1099 +++++++++++++++++++++++++++++++++++
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linux-user/aarch64/cpu_loop.c | 38 +-
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linux-user/elfload.c | 18 +-
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linux-user/flatload.c | 2 +-
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linux-user/hppa/cpu_loop.c | 39 +-
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linux-user/i386/cpu_loop.c | 6 +-
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linux-user/i386/signal.c | 5 +-
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linux-user/main.c | 4 +-
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linux-user/mmap.c | 88 +--
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linux-user/ppc/signal.c | 4 +-
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linux-user/syscall.c | 165 ++++--
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linux-user/uaccess.c | 82 ++-
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target/arm/cpu.c | 25 +-
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target/arm/helper-a64.c | 4 +-
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target/arm/mte_helper.c | 39 +-
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target/arm/tlb_helper.c | 15 +-
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target/arm/translate-a64.c | 25 +-
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target/hppa/op_helper.c | 2 +-
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target/i386/tcg/mem_helper.c | 2 +-
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target/s390x/mem_helper.c | 4 +-
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tests/qtest/npcm7xx_smbus-test.c | 495 ++++++++++++++++
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tests/tcg/aarch64/mte-1.c | 28 +
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tests/tcg/aarch64/mte-2.c | 45 ++
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tests/tcg/aarch64/mte-3.c | 51 ++
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tests/tcg/aarch64/mte-4.c | 45 ++
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tests/tcg/aarch64/pauth-2.c | 1 -
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MAINTAINERS | 11 +
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hw/arm/Kconfig | 1 +
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hw/i2c/meson.build | 1 +
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hw/i2c/trace-events | 12 +
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tests/qtest/meson.build | 1 +
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tests/tcg/aarch64/Makefile.target | 6 +
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tests/tcg/configure.sh | 4 +
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56 files changed, 2976 insertions(+), 553 deletions(-)
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create mode 100644 include/hw/i2c/npcm7xx_smbus.h
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create mode 100644 target/arm/syndrome.h
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create mode 100644 tests/tcg/aarch64/mte.h
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create mode 100644 hw/i2c/npcm7xx_smbus.c
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create mode 100644 tests/qtest/npcm7xx_smbus-test.c
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create mode 100644 tests/tcg/aarch64/mte-1.c
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create mode 100644 tests/tcg/aarch64/mte-2.c
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create mode 100644 tests/tcg/aarch64/mte-3.c
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create mode 100644 tests/tcg/aarch64/mte-4.c
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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